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1/*
2 * Target-specific parts of the CPU object
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
21#include "qemu-common.h"
22#include "qapi/error.h"
23
24#include "exec/target_page.h"
25#include "hw/qdev-core.h"
26#include "hw/qdev-properties.h"
27#include "qemu/error-report.h"
28#include "migration/vmstate.h"
29#ifdef CONFIG_USER_ONLY
30#include "qemu.h"
31#else
8b80bd28 32#include "hw/core/sysemu-cpu-ops.h"
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33#include "exec/address-spaces.h"
34#endif
35#include "sysemu/tcg.h"
36#include "sysemu/kvm.h"
37#include "sysemu/replay.h"
3b9bd3f4 38#include "exec/translate-all.h"
d9f24bf5 39#include "exec/log.h"
30565f10 40#include "hw/core/accel-cpu.h"
ad1a706f 41#include "trace/trace-root.h"
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42
43uintptr_t qemu_host_page_size;
44intptr_t qemu_host_page_mask;
45
46#ifndef CONFIG_USER_ONLY
47static int cpu_common_post_load(void *opaque, int version_id)
48{
49 CPUState *cpu = opaque;
50
51 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
52 version_id is increased. */
53 cpu->interrupt_request &= ~0x01;
54 tlb_flush(cpu);
55
56 /* loadvm has just updated the content of RAM, bypassing the
57 * usual mechanisms that ensure we flush TBs for writes to
58 * memory we've translated code from. So we must flush all TBs,
59 * which will now be stale.
60 */
61 tb_flush(cpu);
62
63 return 0;
64}
65
66static int cpu_common_pre_load(void *opaque)
67{
68 CPUState *cpu = opaque;
69
70 cpu->exception_index = -1;
71
72 return 0;
73}
74
75static bool cpu_common_exception_index_needed(void *opaque)
76{
77 CPUState *cpu = opaque;
78
79 return tcg_enabled() && cpu->exception_index != -1;
80}
81
82static const VMStateDescription vmstate_cpu_common_exception_index = {
83 .name = "cpu_common/exception_index",
84 .version_id = 1,
85 .minimum_version_id = 1,
86 .needed = cpu_common_exception_index_needed,
87 .fields = (VMStateField[]) {
88 VMSTATE_INT32(exception_index, CPUState),
89 VMSTATE_END_OF_LIST()
90 }
91};
92
93static bool cpu_common_crash_occurred_needed(void *opaque)
94{
95 CPUState *cpu = opaque;
96
97 return cpu->crash_occurred;
98}
99
100static const VMStateDescription vmstate_cpu_common_crash_occurred = {
101 .name = "cpu_common/crash_occurred",
102 .version_id = 1,
103 .minimum_version_id = 1,
104 .needed = cpu_common_crash_occurred_needed,
105 .fields = (VMStateField[]) {
106 VMSTATE_BOOL(crash_occurred, CPUState),
107 VMSTATE_END_OF_LIST()
108 }
109};
110
111const VMStateDescription vmstate_cpu_common = {
112 .name = "cpu_common",
113 .version_id = 1,
114 .minimum_version_id = 1,
115 .pre_load = cpu_common_pre_load,
116 .post_load = cpu_common_post_load,
117 .fields = (VMStateField[]) {
118 VMSTATE_UINT32(halted, CPUState),
119 VMSTATE_UINT32(interrupt_request, CPUState),
120 VMSTATE_END_OF_LIST()
121 },
122 .subsections = (const VMStateDescription*[]) {
123 &vmstate_cpu_common_exception_index,
124 &vmstate_cpu_common_crash_occurred,
125 NULL
126 }
127};
128#endif
129
7df5e3d6 130void cpu_exec_realizefn(CPUState *cpu, Error **errp)
d9f24bf5 131{
feece4d0 132#ifndef CONFIG_USER_ONLY
d9f24bf5 133 CPUClass *cc = CPU_GET_CLASS(cpu);
feece4d0 134#endif
d9f24bf5 135
7df5e3d6 136 cpu_list_add(cpu);
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137 if (!accel_cpu_realizefn(cpu, errp)) {
138 return;
139 }
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140#ifdef CONFIG_TCG
141 /* NB: errp parameter is unused currently */
142 if (tcg_enabled()) {
143 tcg_exec_realizefn(cpu, errp);
144 }
145#endif /* CONFIG_TCG */
146
147#ifdef CONFIG_USER_ONLY
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148 assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
149 qdev_get_vmsd(DEVICE(cpu))->unmigratable);
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150#else
151 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
152 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
153 }
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154 if (cc->sysemu_ops->legacy_vmsd != NULL) {
155 vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
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156 }
157#endif /* CONFIG_USER_ONLY */
158}
159
160void cpu_exec_unrealizefn(CPUState *cpu)
161{
feece4d0 162#ifndef CONFIG_USER_ONLY
7df5e3d6 163 CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5 164
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165 if (cc->sysemu_ops->legacy_vmsd != NULL) {
166 vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
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167 }
168 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
169 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
170 }
d9f24bf5 171#endif
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172#ifdef CONFIG_TCG
173 /* NB: errp parameter is unused currently */
174 if (tcg_enabled()) {
175 tcg_exec_unrealizefn(cpu);
176 }
177#endif /* CONFIG_TCG */
178
179 cpu_list_remove(cpu);
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180}
181
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182void cpu_exec_initfn(CPUState *cpu)
183{
184 cpu->as = NULL;
185 cpu->num_ases = 0;
186
187#ifndef CONFIG_USER_ONLY
188 cpu->thread_id = qemu_get_thread_id();
189 cpu->memory = get_system_memory();
190 object_ref(OBJECT(cpu->memory));
191#endif
192}
193
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194const char *parse_cpu_option(const char *cpu_option)
195{
196 ObjectClass *oc;
197 CPUClass *cc;
198 gchar **model_pieces;
199 const char *cpu_type;
200
201 model_pieces = g_strsplit(cpu_option, ",", 2);
202 if (!model_pieces[0]) {
203 error_report("-cpu option cannot be empty");
204 exit(1);
205 }
206
207 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
208 if (oc == NULL) {
209 error_report("unable to find CPU model '%s'", model_pieces[0]);
210 g_strfreev(model_pieces);
211 exit(EXIT_FAILURE);
212 }
213
214 cpu_type = object_class_get_name(oc);
215 cc = CPU_CLASS(oc);
216 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
217 g_strfreev(model_pieces);
218 return cpu_type;
219}
220
221#if defined(CONFIG_USER_ONLY)
222void tb_invalidate_phys_addr(target_ulong addr)
223{
224 mmap_lock();
225 tb_invalidate_phys_page_range(addr, addr + 1);
226 mmap_unlock();
227}
228
229static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
230{
231 tb_invalidate_phys_addr(pc);
232}
233#else
234void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
235{
236 ram_addr_t ram_addr;
237 MemoryRegion *mr;
238 hwaddr l = 1;
239
240 if (!tcg_enabled()) {
241 return;
242 }
243
244 RCU_READ_LOCK_GUARD();
245 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
246 if (!(memory_region_is_ram(mr)
247 || memory_region_is_romd(mr))) {
248 return;
249 }
250 ram_addr = memory_region_get_ram_addr(mr) + addr;
251 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
252}
253
254static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
255{
256 /*
257 * There may not be a virtual to physical translation for the pc
258 * right now, but there may exist cached TB for this pc.
259 * Flush the whole TB cache to force re-translation of such TBs.
260 * This is heavyweight, but we're debugging anyway.
261 */
262 tb_flush(cpu);
263}
264#endif
265
266/* Add a breakpoint. */
267int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
268 CPUBreakpoint **breakpoint)
269{
270 CPUBreakpoint *bp;
271
272 bp = g_malloc(sizeof(*bp));
273
274 bp->pc = pc;
275 bp->flags = flags;
276
277 /* keep all GDB-injected breakpoints in front */
278 if (flags & BP_GDB) {
279 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
280 } else {
281 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
282 }
283
284 breakpoint_invalidate(cpu, pc);
285
286 if (breakpoint) {
287 *breakpoint = bp;
288 }
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289
290 trace_breakpoint_insert(cpu->cpu_index, pc, flags);
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291 return 0;
292}
293
294/* Remove a specific breakpoint. */
295int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
296{
297 CPUBreakpoint *bp;
298
299 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
300 if (bp->pc == pc && bp->flags == flags) {
301 cpu_breakpoint_remove_by_ref(cpu, bp);
302 return 0;
303 }
304 }
305 return -ENOENT;
306}
307
308/* Remove a specific breakpoint by reference. */
ad1a706f 309void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp)
d9f24bf5 310{
ad1a706f 311 QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);
d9f24bf5 312
ad1a706f 313 breakpoint_invalidate(cpu, bp->pc);
d9f24bf5 314
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315 trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
316 g_free(bp);
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317}
318
319/* Remove all matching breakpoints. */
320void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
321{
322 CPUBreakpoint *bp, *next;
323
324 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
325 if (bp->flags & mask) {
326 cpu_breakpoint_remove_by_ref(cpu, bp);
327 }
328 }
329}
330
331/* enable or disable single step mode. EXCP_DEBUG is returned by the
332 CPU loop after each instruction */
333void cpu_single_step(CPUState *cpu, int enabled)
334{
335 if (cpu->singlestep_enabled != enabled) {
336 cpu->singlestep_enabled = enabled;
337 if (kvm_enabled()) {
338 kvm_update_guest_debug(cpu, 0);
339 } else {
340 /* must flush all the translated code to avoid inconsistencies */
341 /* XXX: only flush what is necessary */
342 tb_flush(cpu);
343 }
ad1a706f 344 trace_breakpoint_singlestep(cpu->cpu_index, enabled);
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345 }
346}
347
348void cpu_abort(CPUState *cpu, const char *fmt, ...)
349{
350 va_list ap;
351 va_list ap2;
352
353 va_start(ap, fmt);
354 va_copy(ap2, ap);
355 fprintf(stderr, "qemu: fatal: ");
356 vfprintf(stderr, fmt, ap);
357 fprintf(stderr, "\n");
358 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
359 if (qemu_log_separate()) {
360 FILE *logfile = qemu_log_lock();
361 qemu_log("qemu: fatal: ");
362 qemu_log_vprintf(fmt, ap2);
363 qemu_log("\n");
364 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
365 qemu_log_flush();
366 qemu_log_unlock(logfile);
367 qemu_log_close();
368 }
369 va_end(ap2);
370 va_end(ap);
371 replay_finish();
372#if defined(CONFIG_USER_ONLY)
373 {
374 struct sigaction act;
375 sigfillset(&act.sa_mask);
376 act.sa_handler = SIG_DFL;
377 act.sa_flags = 0;
378 sigaction(SIGABRT, &act, NULL);
379 }
380#endif
381 abort();
382}
383
384/* physical memory access (slow version, mainly for debug) */
385#if defined(CONFIG_USER_ONLY)
386int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
387 void *ptr, target_ulong len, bool is_write)
388{
389 int flags;
390 target_ulong l, page;
391 void * p;
392 uint8_t *buf = ptr;
393
394 while (len > 0) {
395 page = addr & TARGET_PAGE_MASK;
396 l = (page + TARGET_PAGE_SIZE) - addr;
397 if (l > len)
398 l = len;
399 flags = page_get_flags(page);
400 if (!(flags & PAGE_VALID))
401 return -1;
402 if (is_write) {
403 if (!(flags & PAGE_WRITE))
404 return -1;
405 /* XXX: this code should not depend on lock_user */
406 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
407 return -1;
408 memcpy(p, buf, l);
409 unlock_user(p, addr, l);
410 } else {
411 if (!(flags & PAGE_READ))
412 return -1;
413 /* XXX: this code should not depend on lock_user */
414 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
415 return -1;
416 memcpy(buf, p, l);
417 unlock_user(p, addr, 0);
418 }
419 len -= l;
420 buf += l;
421 addr += l;
422 }
423 return 0;
424}
425#endif
426
427bool target_words_bigendian(void)
428{
429#if defined(TARGET_WORDS_BIGENDIAN)
430 return true;
431#else
432 return false;
433#endif
434}
435
436void page_size_init(void)
437{
438 /* NOTE: we can always suppose that qemu_host_page_size >=
439 TARGET_PAGE_SIZE */
440 if (qemu_host_page_size == 0) {
441 qemu_host_page_size = qemu_real_host_page_size;
442 }
443 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
444 qemu_host_page_size = TARGET_PAGE_SIZE;
445 }
446 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
447}