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i386: Update new x86_apicid parsing rules with die_offset support
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b9adb4a6 1/* ppc-dis.c -- Disassemble PowerPC instructions
ee8ae9e4 2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
eca8f888 3 Free Software Foundation, Inc.
b9adb4a6
FB		 4 Written by Ian Lance Taylor, Cygnus Support
5
6This file is part of GDB, GAS, and the GNU binutils.
7
8GDB, GAS, and the GNU binutils are free software; you can redistribute
9them and/or modify them under the terms of the GNU General Public
10License as published by the Free Software Foundation; either version
112, or (at your option) any later version.
12
13GDB, GAS, and the GNU binutils are distributed in the hope that they
14will be useful, but WITHOUT ANY WARRANTY; without even the implied
15warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16the GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
8167ee88
BS		 19along with this file; see the file COPYING. If not,
20see <http://www.gnu.org/licenses/>. */
0d75590d 21#include "qemu/osdep.h"
3979fca4 22#include "disas/dis-asm.h"
eca8f888 23#define BFD_DEFAULT_TARGET_SIZE 64
b9adb4a6
FB		 24
25/* ppc.h -- Header file for PowerPC opcode table
ee8ae9e4
BS		 26 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
27 2007 Free Software Foundation, Inc.
b9adb4a6
FB		 28 Written by Ian Lance Taylor, Cygnus Support
29
30This file is part of GDB, GAS, and the GNU binutils.
31
32GDB, GAS, and the GNU binutils are free software; you can redistribute
33them and/or modify them under the terms of the GNU General Public
34License as published by the Free Software Foundation; either version
351, or (at your option) any later version.
36
37GDB, GAS, and the GNU binutils are distributed in the hope that they
38will be useful, but WITHOUT ANY WARRANTY; without even the implied
39warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
40the GNU General Public License for more details.
41
42You should have received a copy of the GNU General Public License
8167ee88
BS		 43along with this file; see the file COPYING. If not,
44see <http://www.gnu.org/licenses/>. */
b9adb4a6
FB		 45
46/* The opcode table is an array of struct powerpc_opcode. */
47
48struct powerpc_opcode
49{
50 /* The opcode name. */
51 const char *name;
52
53 /* The opcode itself. Those bits which will be filled in with
54 operands are zeroes. */
eca8f888 55 unsigned long opcode;
b9adb4a6
FB		 56
57 /* The opcode mask. This is used by the disassembler. This is a
58 mask containing ones indicating those bits which must match the
59 opcode field, and zeroes indicating those bits which need not
60 match (and are presumably filled in by operands). */
eca8f888 61 unsigned long mask;
b9adb4a6
FB		 62
63 /* One bit flags for the opcode. These are used to indicate which
64 specific processors support the instructions. The defined values
65 are listed below. */
eca8f888 66 unsigned long flags;
b9adb4a6
FB		 67
68 /* An array of operand codes. Each code is an index into the
69 operand table. They appear in the order which the operands must
70 appear in assembly code, and are terminated by a zero. */
71 unsigned char operands[8];
72};
73
74/* The table itself is sorted by major opcode number, and is otherwise
75 in the order in which the disassembler should consider
76 instructions. */
77extern const struct powerpc_opcode powerpc_opcodes[];
78extern const int powerpc_num_opcodes;
79
80/* Values defined for the flags field of a struct powerpc_opcode. */
81
82/* Opcode is defined for the PowerPC architecture. */
eca8f888 83#define PPC_OPCODE_PPC 1
b9adb4a6
FB		 84
85/* Opcode is defined for the POWER (RS/6000) architecture. */
eca8f888 86#define PPC_OPCODE_POWER 2
b9adb4a6
FB		 87
88/* Opcode is defined for the POWER2 (Rios 2) architecture. */
eca8f888 89#define PPC_OPCODE_POWER2 4
b9adb4a6
FB		 90
91/* Opcode is only defined on 32 bit architectures. */
eca8f888 92#define PPC_OPCODE_32 8
b9adb4a6
FB		 93
94/* Opcode is only defined on 64 bit architectures. */
eca8f888 95#define PPC_OPCODE_64 0x10
b9adb4a6
FB		 96
97/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
98 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
99 but it also supports many additional POWER instructions. */
eca8f888
BS		 100#define PPC_OPCODE_601 0x20
101
102/* Opcode is supported in both the Power and PowerPC architectures
103 (ie, compiler's -mcpu=common or assembler's -mcom). */
104#define PPC_OPCODE_COMMON 0x40
105
106/* Opcode is supported for any Power or PowerPC platform (this is
107 for the assembler's -many option, and it eliminates duplicates). */
108#define PPC_OPCODE_ANY 0x80
109
110/* Opcode is supported as part of the 64-bit bridge. */
111#define PPC_OPCODE_64_BRIDGE 0x100
112
113/* Opcode is supported by Altivec Vector Unit */
114#define PPC_OPCODE_ALTIVEC 0x200
115
116/* Opcode is supported by PowerPC 403 processor. */
117#define PPC_OPCODE_403 0x400
118
119/* Opcode is supported by PowerPC BookE processor. */
120#define PPC_OPCODE_BOOKE 0x800
121
122/* Opcode is only supported by 64-bit PowerPC BookE processor. */
123#define PPC_OPCODE_BOOKE64 0x1000
124
125/* Opcode is supported by PowerPC 440 processor. */
126#define PPC_OPCODE_440 0x2000
127
128/* Opcode is only supported by Power4 architecture. */
129#define PPC_OPCODE_POWER4 0x4000
130
131/* Opcode isn't supported by Power4 architecture. */
132#define PPC_OPCODE_NOPOWER4 0x8000
133
134/* Opcode is only supported by POWERPC Classic architecture. */
135#define PPC_OPCODE_CLASSIC 0x10000
136
137/* Opcode is only supported by e500x2 Core. */
138#define PPC_OPCODE_SPE 0x20000
139
140/* Opcode is supported by e500x2 Integer select APU. */
141#define PPC_OPCODE_ISEL 0x40000
142
143/* Opcode is an e500 SPE floating point instruction. */
144#define PPC_OPCODE_EFS 0x80000
145
146/* Opcode is supported by branch locking APU. */
147#define PPC_OPCODE_BRLOCK 0x100000
148
149/* Opcode is supported by performance monitor APU. */
150#define PPC_OPCODE_PMR 0x200000
151
152/* Opcode is supported by cache locking APU. */
153#define PPC_OPCODE_CACHELCK 0x400000
154
155/* Opcode is supported by machine check APU. */
156#define PPC_OPCODE_RFMCI 0x800000
157
158/* Opcode is only supported by Power5 architecture. */
ee8ae9e4 159#define PPC_OPCODE_POWER5 0x1000000
eca8f888
BS		 160
161/* Opcode is supported by PowerPC e300 family. */
ee8ae9e4
BS		 162#define PPC_OPCODE_E300 0x2000000
163
164/* Opcode is only supported by Power6 architecture. */
165#define PPC_OPCODE_POWER6 0x4000000
166
167/* Opcode is only supported by PowerPC Cell family. */
168#define PPC_OPCODE_CELL 0x8000000
b9adb4a6
FB		 169
170/* A macro to extract the major opcode from an instruction. */
171#define PPC_OP(i) (((i) >> 26) & 0x3f)
172\f
173/* The operands table is an array of struct powerpc_operand. */
174
175struct powerpc_operand
176{
ee8ae9e4
BS		 177 /* A bitmask of bits in the operand. */
178 unsigned int bitm;
b9adb4a6 179
ee8ae9e4
BS		 180 /* How far the operand is left shifted in the instruction.
181 -1 to indicate that BITM and SHIFT cannot be used to determine
182 where the operand goes in the insn. */
b9adb4a6
FB		 183 int shift;
184
185 /* Insertion function. This is used by the assembler. To insert an
186 operand value into an instruction, check this field.
187
188 If it is NULL, execute
ee8ae9e4 189 i |= (op & o->bitm) << o->shift;
b9adb4a6 190 (i is the instruction which we are filling in, o is a pointer to
ee8ae9e4 191 this structure, and op is the operand value).
b9adb4a6
FB		 192
193 If this field is not NULL, then simply call it with the
194 instruction and the operand value. It will return the new value
195 of the instruction. If the ERRMSG argument is not NULL, then if
196 the operand value is illegal, *ERRMSG will be set to a warning
197 string (the operand will be inserted in any case). If the
198 operand value is legal, *ERRMSG will be unchanged (most operands
199 can accept any value). */
eca8f888
BS		 200 unsigned long (*insert)
201 (unsigned long instruction, long op, int dialect, const char **errmsg);
b9adb4a6
FB		 202
203 /* Extraction function. This is used by the disassembler. To
204 extract this operand type from an instruction, check this field.
205
206 If it is NULL, compute
ee8ae9e4
BS		 207 op = (i >> o->shift) & o->bitm;
208 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
209 sign_extend (op);
b9adb4a6 210 (i is the instruction, o is a pointer to this structure, and op
ee8ae9e4 211 is the result).
b9adb4a6
FB		 212
213 If this field is not NULL, then simply call it with the
214 instruction value. It will return the value of the operand. If
215 the INVALID argument is not NULL, *INVALID will be set to
216 non-zero if this operand type can not actually be extracted from
217 this operand (i.e., the instruction does not match). If the
218 operand is valid, *INVALID will not be changed. */
eca8f888 219 long (*extract) (unsigned long instruction, int dialect, int *invalid);
b9adb4a6
FB		 220
221 /* One bit syntax flags. */
eca8f888 222 unsigned long flags;
b9adb4a6
FB		 223};
224
225/* Elements in the table are retrieved by indexing with values from
226 the operands field of the powerpc_opcodes table. */
227
228extern const struct powerpc_operand powerpc_operands[];
ee8ae9e4 229extern const unsigned int num_powerpc_operands;
b9adb4a6
FB		 230
231/* Values defined for the flags field of a struct powerpc_operand. */
232
233/* This operand takes signed values. */
ee8ae9e4 234#define PPC_OPERAND_SIGNED (0x1)
b9adb4a6
FB		 235
236/* This operand takes signed values, but also accepts a full positive
237 range of values when running in 32 bit mode. That is, if bits is
238 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
239 this flag is ignored. */
ee8ae9e4 240#define PPC_OPERAND_SIGNOPT (0x2)
b9adb4a6
FB		 241
242/* This operand does not actually exist in the assembler input. This
243 is used to support extended mnemonics such as mr, for which two
244 operands fields are identical. The assembler should call the
245 insert function with any op value. The disassembler should call
246 the extract function, ignore the return value, and check the value
247 placed in the valid argument. */
ee8ae9e4 248#define PPC_OPERAND_FAKE (0x4)
b9adb4a6
FB		 249
250/* The next operand should be wrapped in parentheses rather than
251 separated from this one by a comma. This is used for the load and
252 store instructions which want their operands to look like
253 reg,displacement(reg)
254 */
ee8ae9e4 255#define PPC_OPERAND_PARENS (0x8)
b9adb4a6
FB		 256
257/* This operand may use the symbolic names for the CR fields, which
258 are
259 lt 0 gt 1 eq 2 so 3 un 3
260 cr0 0 cr1 1 cr2 2 cr3 3
261 cr4 4 cr5 5 cr6 6 cr7 7
262 These may be combined arithmetically, as in cr2*4+gt. These are
263 only supported on the PowerPC, not the POWER. */
ee8ae9e4 264#define PPC_OPERAND_CR (0x10)
b9adb4a6
FB		 265
266/* This operand names a register. The disassembler uses this to print
267 register names with a leading 'r'. */
ee8ae9e4 268#define PPC_OPERAND_GPR (0x20)
b9adb4a6 269
eca8f888 270/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
ee8ae9e4 271#define PPC_OPERAND_GPR_0 (0x40)
eca8f888 272
b9adb4a6
FB		 273/* This operand names a floating point register. The disassembler
274 prints these with a leading 'f'. */
ee8ae9e4 275#define PPC_OPERAND_FPR (0x80)
b9adb4a6
FB		 276
277/* This operand is a relative branch displacement. The disassembler
278 prints these symbolically if possible. */
ee8ae9e4 279#define PPC_OPERAND_RELATIVE (0x100)
b9adb4a6
FB		 280
281/* This operand is an absolute branch address. The disassembler
282 prints these symbolically if possible. */
ee8ae9e4 283#define PPC_OPERAND_ABSOLUTE (0x200)
b9adb4a6
FB		 284
285/* This operand is optional, and is zero if omitted. This is used for
eca8f888 286 example, in the optional BF field in the comparison instructions. The
b9adb4a6
FB		 287 assembler must count the number of operands remaining on the line,
288 and the number of operands remaining for the opcode, and decide
289 whether this operand is present or not. The disassembler should
290 print this operand out only if it is not zero. */
ee8ae9e4 291#define PPC_OPERAND_OPTIONAL (0x400)
b9adb4a6
FB		 292
293/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
294 is omitted, then for the next operand use this operand value plus
295 1, ignoring the next operand field for the opcode. This wretched
296 hack is needed because the Power rotate instructions can take
297 either 4 or 5 operands. The disassembler should print this operand
298 out regardless of the PPC_OPERAND_OPTIONAL field. */
ee8ae9e4 299#define PPC_OPERAND_NEXT (0x800)
b9adb4a6
FB		 300
301/* This operand should be regarded as a negative number for the
302 purposes of overflow checking (i.e., the normal most negative
303 number is disallowed and one more than the normal most positive
304 number is allowed). This flag will only be set for a signed
305 operand. */
ee8ae9e4 306#define PPC_OPERAND_NEGATIVE (0x1000)
eca8f888
BS		 307
308/* This operand names a vector unit register. The disassembler
309 prints these with a leading 'v'. */
ee8ae9e4 310#define PPC_OPERAND_VR (0x2000)
eca8f888
BS		 311
312/* This operand is for the DS field in a DS form instruction. */
ee8ae9e4 313#define PPC_OPERAND_DS (0x4000)
eca8f888
BS		 314
315/* This operand is for the DQ field in a DQ form instruction. */
ee8ae9e4
BS		 316#define PPC_OPERAND_DQ (0x8000)
317
318/* Valid range of operand is 0..n rather than 0..n-1. */
319#define PPC_OPERAND_PLUS1 (0x10000)
b9adb4a6
FB		 320\f
321/* The POWER and PowerPC assemblers use a few macros. We keep them
322 with the operands table for simplicity. The macro table is an
323 array of struct powerpc_macro. */
324
325struct powerpc_macro
326{
327 /* The macro name. */
328 const char *name;
329
330 /* The number of operands the macro takes. */
331 unsigned int operands;
332
333 /* One bit flags for the opcode. These are used to indicate which
334 specific processors support the instructions. The values are the
335 same as those for the struct powerpc_opcode flags field. */
eca8f888 336 unsigned long flags;
b9adb4a6
FB		 337
338 /* A format string to turn the macro into a normal instruction.
339 Each %N in the string is replaced with operand number N (zero
340 based). */
341 const char *format;
342};
343
344extern const struct powerpc_macro powerpc_macros[];
345extern const int powerpc_num_macros;
346
347/* ppc-opc.c -- PowerPC opcode list
eca8f888 348 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
ee8ae9e4 349 2005, 2006, 2007 Free Software Foundation, Inc.
b9adb4a6
FB		 350 Written by Ian Lance Taylor, Cygnus Support
351
eca8f888 352 This file is part of GDB, GAS, and the GNU binutils.
b9adb4a6 353
eca8f888
BS		 354 GDB, GAS, and the GNU binutils are free software; you can redistribute
355 them and/or modify them under the terms of the GNU General Public
356 License as published by the Free Software Foundation; either version
357 2, or (at your option) any later version.
b9adb4a6 358
eca8f888
BS		 359 GDB, GAS, and the GNU binutils are distributed in the hope that they
360 will be useful, but WITHOUT ANY WARRANTY; without even the implied
361 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
362 the GNU General Public License for more details.
b9adb4a6 363
eca8f888 364 You should have received a copy of the GNU General Public License
8167ee88
BS		 365 along with this file; see the file COPYING.
366 If not, see <http://www.gnu.org/licenses/>. */
b9adb4a6
FB		 367
368/* This file holds the PowerPC opcode table. The opcode table
369 includes almost all of the extended instruction mnemonics. This
370 permits the disassembler to use them, and simplifies the assembler
371 logic, at the cost of increasing the table size. The table is
372 strictly constant data, so the compiler should be able to put it in
373 the .text section.
374
375 This file also holds the operand table. All knowledge about
376 inserting operands into instructions and vice-versa is kept in this
377 file. */
378\f
379/* Local insertion and extraction functions. */
380
eca8f888
BS		 381static unsigned long insert_bat (unsigned long, long, int, const char **);
382static long extract_bat (unsigned long, int, int *);
383static unsigned long insert_bba (unsigned long, long, int, const char **);
384static long extract_bba (unsigned long, int, int *);
eca8f888
BS		 385static unsigned long insert_bdm (unsigned long, long, int, const char **);
386static long extract_bdm (unsigned long, int, int *);
387static unsigned long insert_bdp (unsigned long, long, int, const char **);
388static long extract_bdp (unsigned long, int, int *);
389static unsigned long insert_bo (unsigned long, long, int, const char **);
390static long extract_bo (unsigned long, int, int *);
391static unsigned long insert_boe (unsigned long, long, int, const char **);
392static long extract_boe (unsigned long, int, int *);
eca8f888
BS		 393static unsigned long insert_fxm (unsigned long, long, int, const char **);
394static long extract_fxm (unsigned long, int, int *);
eca8f888
BS		 395static unsigned long insert_mbe (unsigned long, long, int, const char **);
396static long extract_mbe (unsigned long, int, int *);
397static unsigned long insert_mb6 (unsigned long, long, int, const char **);
398static long extract_mb6 (unsigned long, int, int *);
eca8f888
BS		 399static long extract_nb (unsigned long, int, int *);
400static unsigned long insert_nsi (unsigned long, long, int, const char **);
401static long extract_nsi (unsigned long, int, int *);
402static unsigned long insert_ral (unsigned long, long, int, const char **);
403static unsigned long insert_ram (unsigned long, long, int, const char **);
404static unsigned long insert_raq (unsigned long, long, int, const char **);
405static unsigned long insert_ras (unsigned long, long, int, const char **);
406static unsigned long insert_rbs (unsigned long, long, int, const char **);
407static long extract_rbs (unsigned long, int, int *);
eca8f888
BS		 408static unsigned long insert_sh6 (unsigned long, long, int, const char **);
409static long extract_sh6 (unsigned long, int, int *);
410static unsigned long insert_spr (unsigned long, long, int, const char **);
411static long extract_spr (unsigned long, int, int *);
412static unsigned long insert_sprg (unsigned long, long, int, const char **);
413static long extract_sprg (unsigned long, int, int *);
414static unsigned long insert_tbr (unsigned long, long, int, const char **);
415static long extract_tbr (unsigned long, int, int *);
b9adb4a6
FB		 416\f
417/* The operands table.
418
ee8ae9e4 419 The fields are bitm, shift, insert, extract, flags.
eca8f888
BS		 420
421 We used to put parens around the various additions, like the one
422 for BA just below. However, that caused trouble with feeble
423 compilers with a limit on depth of a parenthesized expression, like
424 (reportedly) the compiler in Microsoft Developer Studio 5. So we
425 omit the parens, since the macros are never used in a context where
426 the addition will be ambiguous. */
b9adb4a6
FB		 427
428const struct powerpc_operand powerpc_operands[] =
429{
430 /* The zero index is used to indicate the end of the list of
431 operands. */
eca8f888
BS		 432#define UNUSED 0
433 { 0, 0, NULL, NULL, 0 },
b9adb4a6
FB		 434
435 /* The BA field in an XL form instruction. */
eca8f888 436#define BA UNUSED + 1
ee8ae9e4
BS		 437 /* The BI field in a B form or XL form instruction. */
438#define BI BA
439#define BI_MASK (0x1f << 16)
440 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
b9adb4a6
FB		 441
442 /* The BA field in an XL form instruction when it must be the same
443 as the BT field in the same instruction. */
eca8f888 444#define BAT BA + 1
ee8ae9e4 445 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
b9adb4a6
FB		 446
447 /* The BB field in an XL form instruction. */
eca8f888 448#define BB BAT + 1
b9adb4a6 449#define BB_MASK (0x1f << 11)
ee8ae9e4 450 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
b9adb4a6
FB		 451
452 /* The BB field in an XL form instruction when it must be the same
453 as the BA field in the same instruction. */
eca8f888 454#define BBA BB + 1
ee8ae9e4 455 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
b9adb4a6
FB		 456
457 /* The BD field in a B form instruction. The lower two bits are
458 forced to zero. */
eca8f888 459#define BD BBA + 1
ee8ae9e4 460 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
b9adb4a6
FB		 461
462 /* The BD field in a B form instruction when absolute addressing is
463 used. */
eca8f888 464#define BDA BD + 1
ee8ae9e4 465 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
b9adb4a6
FB		 466
467 /* The BD field in a B form instruction when the - modifier is used.
468 This sets the y bit of the BO field appropriately. */
eca8f888 469#define BDM BDA + 1
ee8ae9e4 470 { 0xfffc, 0, insert_bdm, extract_bdm,
b9adb4a6
FB		 471 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
472
473 /* The BD field in a B form instruction when the - modifier is used
474 and absolute address is used. */
eca8f888 475#define BDMA BDM + 1
ee8ae9e4 476 { 0xfffc, 0, insert_bdm, extract_bdm,
b9adb4a6
FB		 477 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
478
479 /* The BD field in a B form instruction when the + modifier is used.
480 This sets the y bit of the BO field appropriately. */
eca8f888 481#define BDP BDMA + 1
ee8ae9e4 482 { 0xfffc, 0, insert_bdp, extract_bdp,
b9adb4a6
FB		 483 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
484
485 /* The BD field in a B form instruction when the + modifier is used
486 and absolute addressing is used. */
eca8f888 487#define BDPA BDP + 1
ee8ae9e4 488 { 0xfffc, 0, insert_bdp, extract_bdp,
b9adb4a6
FB		 489 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
490
491 /* The BF field in an X or XL form instruction. */
eca8f888 492#define BF BDPA + 1
ee8ae9e4
BS		 493 /* The CRFD field in an X form instruction. */
494#define CRFD BF
495 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
496
497 /* The BF field in an X or XL form instruction. */
498#define BFF BF + 1
499 { 0x7, 23, NULL, NULL, 0 },
b9adb4a6
FB		 500
501 /* An optional BF field. This is used for comparison instructions,
502 in which an omitted BF field is taken as zero. */
ee8ae9e4
BS		 503#define OBF BFF + 1
504 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 505
506 /* The BFA field in an X or XL form instruction. */
eca8f888 507#define BFA OBF + 1
ee8ae9e4 508 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
b9adb4a6
FB		 509
510 /* The BO field in a B form instruction. Certain values are
511 illegal. */
ee8ae9e4 512#define BO BFA + 1
b9adb4a6 513#define BO_MASK (0x1f << 21)
ee8ae9e4 514 { 0x1f, 21, insert_bo, extract_bo, 0 },
b9adb4a6
FB		 515
516 /* The BO field in a B form instruction when the + or - modifier is
517 used. This is like the BO field, but it must be even. */
eca8f888 518#define BOE BO + 1
ee8ae9e4 519 { 0x1e, 21, insert_boe, extract_boe, 0 },
b9adb4a6 520
eca8f888 521#define BH BOE + 1
ee8ae9e4 522 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
eca8f888 523
b9adb4a6 524 /* The BT field in an X or XL form instruction. */
eca8f888 525#define BT BH + 1
ee8ae9e4 526 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
b9adb4a6
FB		 527
528 /* The condition register number portion of the BI field in a B form
529 or XL form instruction. This is used for the extended
530 conditional branch mnemonics, which set the lower two bits of the
531 BI field. This field is optional. */
eca8f888 532#define CR BT + 1
ee8ae9e4 533 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
eca8f888
BS		 534
535 /* The CRB field in an X form instruction. */
536#define CRB CR + 1
ee8ae9e4
BS		 537 /* The MB field in an M form instruction. */
538#define MB CRB
539#define MB_MASK (0x1f << 6)
540 { 0x1f, 6, NULL, NULL, 0 },
eca8f888
BS		 541
542 /* The CRFS field in an X form instruction. */
ee8ae9e4
BS		 543#define CRFS CRB + 1
544 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
eca8f888
BS		 545
546 /* The CT field in an X form instruction. */
547#define CT CRFS + 1
ee8ae9e4
BS		 548 /* The MO field in an mbar instruction. */
549#define MO CT
550 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 551
552 /* The D field in a D form instruction. This is a displacement off
553 a register, and implies that the next operand is a register in
554 parentheses. */
eca8f888 555#define D CT + 1
ee8ae9e4 556 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
eca8f888
BS		 557
558 /* The DE field in a DE form instruction. This is like D, but is 12
559 bits only. */
560#define DE D + 1
ee8ae9e4 561 { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
eca8f888
BS		 562
563 /* The DES field in a DES form instruction. This is like DS, but is 14
564 bits only (12 stored.) */
565#define DES DE + 1
ee8ae9e4 566 { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
eca8f888
BS		 567
568 /* The DQ field in a DQ form instruction. This is like D, but the
569 lower four bits are forced to zero. */
570#define DQ DES + 1
ee8ae9e4
BS		 571 { 0xfff0, 0, NULL, NULL,
572 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
b9adb4a6
FB		 573
574 /* The DS field in a DS form instruction. This is like D, but the
575 lower two bits are forced to zero. */
aba1d00a 576#undef DS
eca8f888 577#define DS DQ + 1
ee8ae9e4
BS		 578 { 0xfffc, 0, NULL, NULL,
579 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
eca8f888
BS		 580
581 /* The E field in a wrteei instruction. */
582#define E DS + 1
ee8ae9e4 583 { 0x1, 15, NULL, NULL, 0 },
b9adb4a6
FB		 584
585 /* The FL1 field in a POWER SC form instruction. */
eca8f888 586#define FL1 E + 1
ee8ae9e4
BS		 587 /* The U field in an X form instruction. */
588#define U FL1
589 { 0xf, 12, NULL, NULL, 0 },
b9adb4a6
FB		 590
591 /* The FL2 field in a POWER SC form instruction. */
eca8f888 592#define FL2 FL1 + 1
ee8ae9e4 593 { 0x7, 2, NULL, NULL, 0 },
b9adb4a6
FB		 594
595 /* The FLM field in an XFL form instruction. */
eca8f888 596#define FLM FL2 + 1
ee8ae9e4 597 { 0xff, 17, NULL, NULL, 0 },
b9adb4a6
FB		 598
599 /* The FRA field in an X or A form instruction. */
eca8f888 600#define FRA FLM + 1
b9adb4a6 601#define FRA_MASK (0x1f << 16)
ee8ae9e4 602 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
b9adb4a6
FB		 603
604 /* The FRB field in an X or A form instruction. */
eca8f888 605#define FRB FRA + 1
b9adb4a6 606#define FRB_MASK (0x1f << 11)
ee8ae9e4 607 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
b9adb4a6
FB		 608
609 /* The FRC field in an A form instruction. */
eca8f888 610#define FRC FRB + 1
b9adb4a6 611#define FRC_MASK (0x1f << 6)
ee8ae9e4 612 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
b9adb4a6
FB		 613
614 /* The FRS field in an X form instruction or the FRT field in a D, X
615 or A form instruction. */
eca8f888
BS		 616#define FRS FRC + 1
617#define FRT FRS
ee8ae9e4 618 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
b9adb4a6
FB		 619
620 /* The FXM field in an XFX instruction. */
eca8f888 621#define FXM FRS + 1
ee8ae9e4 622 { 0xff, 12, insert_fxm, extract_fxm, 0 },
eca8f888
BS		 623
624 /* Power4 version for mfcr. */
625#define FXM4 FXM + 1
ee8ae9e4 626 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 627
628 /* The L field in a D or X form instruction. */
eca8f888 629#define L FXM4 + 1
ee8ae9e4 630 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
b9adb4a6 631
eca8f888
BS		 632 /* The LEV field in a POWER SVC form instruction. */
633#define SVC_LEV L + 1
ee8ae9e4 634 { 0x7f, 5, NULL, NULL, 0 },
eca8f888
BS		 635
636 /* The LEV field in an SC form instruction. */
637#define LEV SVC_LEV + 1
ee8ae9e4 638 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 639
640 /* The LI field in an I form instruction. The lower two bits are
641 forced to zero. */
eca8f888 642#define LI LEV + 1
ee8ae9e4 643 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
b9adb4a6
FB		 644
645 /* The LI field in an I form instruction when used as an absolute
646 address. */
eca8f888 647#define LIA LI + 1
ee8ae9e4 648 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
b9adb4a6 649
eca8f888
BS		 650 /* The LS field in an X (sync) form instruction. */
651#define LS LIA + 1
ee8ae9e4 652 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 653
654 /* The ME field in an M form instruction. */
ee8ae9e4 655#define ME LS + 1
b9adb4a6 656#define ME_MASK (0x1f << 1)
ee8ae9e4 657 { 0x1f, 1, NULL, NULL, 0 },
b9adb4a6
FB		 658
659 /* The MB and ME fields in an M form instruction expressed a single
660 operand which is a bitmask indicating which bits to select. This
661 is a two operand form using PPC_OPERAND_NEXT. See the
662 description in opcode/ppc.h for what this means. */
eca8f888 663#define MBE ME + 1
ee8ae9e4
BS		 664 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
665 { -1, 0, insert_mbe, extract_mbe, 0 },
b9adb4a6
FB		 666
667 /* The MB or ME field in an MD or MDS form instruction. The high
668 bit is wrapped to the low end. */
eca8f888
BS		 669#define MB6 MBE + 2
670#define ME6 MB6
b9adb4a6 671#define MB6_MASK (0x3f << 5)
ee8ae9e4 672 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
eca8f888 673
b9adb4a6
FB		 674 /* The NB field in an X form instruction. The value 32 is stored as
675 0. */
ee8ae9e4
BS		 676#define NB MB6 + 1
677 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
b9adb4a6
FB		 678
679 /* The NSI field in a D form instruction. This is the same as the
680 SI field, only negated. */
eca8f888 681#define NSI NB + 1
ee8ae9e4 682 { 0xffff, 0, insert_nsi, extract_nsi,
b9adb4a6
FB		 683 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
684
eca8f888
BS		 685 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
686#define RA NSI + 1
b9adb4a6 687#define RA_MASK (0x1f << 16)
ee8ae9e4 688 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
eca8f888
BS		 689
690 /* As above, but 0 in the RA field means zero, not r0. */
691#define RA0 RA + 1
ee8ae9e4 692 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
eca8f888
BS		 693
694 /* The RA field in the DQ form lq instruction, which has special
695 value restrictions. */
696#define RAQ RA0 + 1
ee8ae9e4 697 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
b9adb4a6
FB		 698
699 /* The RA field in a D or X form instruction which is an updating
700 load, which means that the RA field may not be zero and may not
701 equal the RT field. */
eca8f888 702#define RAL RAQ + 1
ee8ae9e4 703 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
b9adb4a6
FB		 704
705 /* The RA field in an lmw instruction, which has special value
706 restrictions. */
eca8f888 707#define RAM RAL + 1
ee8ae9e4 708 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
b9adb4a6
FB		 709
710 /* The RA field in a D or X form instruction which is an updating
711 store or an updating floating point load, which means that the RA
712 field may not be zero. */
eca8f888 713#define RAS RAM + 1
ee8ae9e4 714 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
eca8f888
BS		 715
716 /* The RA field of the tlbwe instruction, which is optional. */
717#define RAOPT RAS + 1
ee8ae9e4 718 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 719
720 /* The RB field in an X, XO, M, or MDS form instruction. */
eca8f888 721#define RB RAOPT + 1
b9adb4a6 722#define RB_MASK (0x1f << 11)
ee8ae9e4 723 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
b9adb4a6
FB		 724
725 /* The RB field in an X form instruction when it must be the same as
726 the RS field in the instruction. This is used for extended
727 mnemonics like mr. */
eca8f888 728#define RBS RB + 1
ee8ae9e4 729 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
b9adb4a6
FB		 730
731 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
732 instruction or the RT field in a D, DS, X, XFX or XO form
733 instruction. */
eca8f888
BS		 734#define RS RBS + 1
735#define RT RS
b9adb4a6 736#define RT_MASK (0x1f << 21)
ee8ae9e4 737 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
eca8f888 738
ee8ae9e4
BS		 739 /* The RS and RT fields of the DS form stq instruction, which have
740 special value restrictions. */
eca8f888 741#define RSQ RS + 1
ee8ae9e4
BS		 742#define RTQ RSQ
743 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
eca8f888
BS		 744
745 /* The RS field of the tlbwe instruction, which is optional. */
ee8ae9e4 746#define RSO RSQ + 1
eca8f888 747#define RTO RSO
ee8ae9e4 748 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 749
750 /* The SH field in an X or M form instruction. */
eca8f888 751#define SH RSO + 1
b9adb4a6 752#define SH_MASK (0x1f << 11)
ee8ae9e4
BS		 753 /* The other UIMM field in a EVX form instruction. */
754#define EVUIMM SH
755 { 0x1f, 11, NULL, NULL, 0 },
b9adb4a6
FB		 756
757 /* The SH field in an MD form instruction. This is split. */
eca8f888 758#define SH6 SH + 1
b9adb4a6 759#define SH6_MASK ((0x1f << 11) | (1 << 1))
ee8ae9e4 760 { 0x3f, -1, insert_sh6, extract_sh6, 0 },
b9adb4a6 761
eca8f888
BS		 762 /* The SH field of the tlbwe instruction, which is optional. */
763#define SHO SH6 + 1
ee8ae9e4 764 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
eca8f888 765
b9adb4a6 766 /* The SI field in a D form instruction. */
eca8f888 767#define SI SHO + 1
ee8ae9e4 768 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
b9adb4a6
FB		 769
770 /* The SI field in a D form instruction when we accept a wide range
771 of positive values. */
eca8f888 772#define SISIGNOPT SI + 1
ee8ae9e4 773 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
b9adb4a6
FB		 774
775 /* The SPR field in an XFX form instruction. This is flipped--the
776 lower 5 bits are stored in the upper 5 and vice- versa. */
eca8f888
BS		 777#define SPR SISIGNOPT + 1
778#define PMR SPR
b9adb4a6 779#define SPR_MASK (0x3ff << 11)
ee8ae9e4 780 { 0x3ff, 11, insert_spr, extract_spr, 0 },
b9adb4a6
FB		 781
782 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
eca8f888 783#define SPRBAT SPR + 1
b9adb4a6 784#define SPRBAT_MASK (0x3 << 17)
ee8ae9e4 785 { 0x3, 17, NULL, NULL, 0 },
b9adb4a6
FB		 786
787 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
eca8f888 788#define SPRG SPRBAT + 1
ee8ae9e4 789 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
b9adb4a6
FB		 790
791 /* The SR field in an X form instruction. */
eca8f888 792#define SR SPRG + 1
ee8ae9e4 793 { 0xf, 16, NULL, NULL, 0 },
eca8f888
BS		 794
795 /* The STRM field in an X AltiVec form instruction. */
796#define STRM SR + 1
ee8ae9e4 797 { 0x3, 21, NULL, NULL, 0 },
b9adb4a6
FB		 798
799 /* The SV field in a POWER SC form instruction. */
eca8f888 800#define SV STRM + 1
ee8ae9e4 801 { 0x3fff, 2, NULL, NULL, 0 },
b9adb4a6
FB		 802
803 /* The TBR field in an XFX form instruction. This is like the SPR
804 field, but it is optional. */
eca8f888 805#define TBR SV + 1
ee8ae9e4 806 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
b9adb4a6
FB		 807
808 /* The TO field in a D or X form instruction. */
eca8f888 809#define TO TBR + 1
b9adb4a6 810#define TO_MASK (0x1f << 21)
ee8ae9e4 811 { 0x1f, 21, NULL, NULL, 0 },
b9adb4a6
FB		 812
813 /* The UI field in a D form instruction. */
ee8ae9e4
BS		 814#define UI TO + 1
815 { 0xffff, 0, NULL, NULL, 0 },
eca8f888
BS		 816
817 /* The VA field in a VA, VX or VXR form instruction. */
818#define VA UI + 1
ee8ae9e4 819 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
eca8f888
BS		 820
821 /* The VB field in a VA, VX or VXR form instruction. */
822#define VB VA + 1
ee8ae9e4 823 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
eca8f888
BS		 824
825 /* The VC field in a VA form instruction. */
826#define VC VB + 1
ee8ae9e4 827 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
eca8f888
BS		 828
829 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
830#define VD VC + 1
831#define VS VD
ee8ae9e4 832 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
eca8f888
BS		 833
834 /* The SIMM field in a VX form instruction. */
835#define SIMM VD + 1
ee8ae9e4 836 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
eca8f888 837
ee8ae9e4 838 /* The UIMM field in a VX form instruction, and TE in Z form. */
eca8f888 839#define UIMM SIMM + 1
ee8ae9e4
BS		 840#define TE UIMM
841 { 0x1f, 16, NULL, NULL, 0 },
eca8f888
BS		 842
843 /* The SHB field in a VA form instruction. */
844#define SHB UIMM + 1
ee8ae9e4 845 { 0xf, 6, NULL, NULL, 0 },
eca8f888
BS		 846
847 /* The other UIMM field in a half word EVX form instruction. */
ee8ae9e4
BS		 848#define EVUIMM_2 SHB + 1
849 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
eca8f888
BS		 850
851 /* The other UIMM field in a word EVX form instruction. */
852#define EVUIMM_4 EVUIMM_2 + 1
ee8ae9e4 853 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
eca8f888
BS		 854
855 /* The other UIMM field in a double EVX form instruction. */
856#define EVUIMM_8 EVUIMM_4 + 1
ee8ae9e4 857 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
eca8f888
BS		 858
859 /* The WS field. */
860#define WS EVUIMM_8 + 1
ee8ae9e4
BS		 861 { 0x7, 11, NULL, NULL, 0 },
862
863 /* The L field in an mtmsrd or A form instruction or W in an X form. */
864#define A_L WS + 1
865#define W A_L
866 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
867
868#define RMC A_L + 1
869 { 0x3, 9, NULL, NULL, 0 },
870
871#define R RMC + 1
872 { 0x1, 16, NULL, NULL, 0 },
eca8f888 873
ee8ae9e4
BS		 874#define SP R + 1
875 { 0x3, 19, NULL, NULL, 0 },
eca8f888 876
ee8ae9e4
BS		 877#define S SP + 1
878 { 0x1, 20, NULL, NULL, 0 },
879
880 /* SH field starting at bit position 16. */
881#define SH16 S + 1
882 /* The DCM and DGM fields in a Z form instruction. */
883#define DCM SH16
884#define DGM DCM
885 { 0x3f, 10, NULL, NULL, 0 },
886
887 /* The EH field in larx instruction. */
888#define EH SH16 + 1
889 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
890
891 /* The L field in an mtfsf or XFL form instruction. */
892#define XFL_L EH + 1
893 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
b9adb4a6
FB		 894};
895
ee8ae9e4
BS		 896const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
897 / sizeof (powerpc_operands[0]));
898
b9adb4a6
FB		 899/* The functions used to insert and extract complicated operands. */
900
901/* The BA field in an XL form instruction when it must be the same as
902 the BT field in the same instruction. This operand is marked FAKE.
903 The insertion function just copies the BT field into the BA field,
904 and the extraction function just checks that the fields are the
905 same. */
906
5fafdf24 907static unsigned long
eca8f888
BS		 908insert_bat (unsigned long insn,
909 long value ATTRIBUTE_UNUSED,
910 int dialect ATTRIBUTE_UNUSED,
911 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 912{
913 return insn | (((insn >> 21) & 0x1f) << 16);
914}
915
916static long
eca8f888
BS		 917extract_bat (unsigned long insn,
918 int dialect ATTRIBUTE_UNUSED,
919 int *invalid)
b9adb4a6 920{
eca8f888 921 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
b9adb4a6
FB		 922 *invalid = 1;
923 return 0;
924}
925
926/* The BB field in an XL form instruction when it must be the same as
927 the BA field in the same instruction. This operand is marked FAKE.
928 The insertion function just copies the BA field into the BB field,
929 and the extraction function just checks that the fields are the
930 same. */
931
b9adb4a6 932static unsigned long
eca8f888
BS		 933insert_bba (unsigned long insn,
934 long value ATTRIBUTE_UNUSED,
935 int dialect ATTRIBUTE_UNUSED,
936 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 937{
938 return insn | (((insn >> 16) & 0x1f) << 11);
939}
940
941static long
eca8f888
BS		 942extract_bba (unsigned long insn,
943 int dialect ATTRIBUTE_UNUSED,
944 int *invalid)
b9adb4a6 945{
eca8f888 946 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
b9adb4a6
FB		 947 *invalid = 1;
948 return 0;
949}
950
b9adb4a6
FB		 951/* The BD field in a B form instruction when the - modifier is used.
952 This modifier means that the branch is not expected to be taken.
eca8f888
BS		 953 For chips built to versions of the architecture prior to version 2
954 (ie. not Power4 compatible), we set the y bit of the BO field to 1
955 if the offset is negative. When extracting, we require that the y
956 bit be 1 and that the offset be positive, since if the y bit is 0
957 we just want to print the normal form of the instruction.
958 Power4 compatible targets use two bits, "a", and "t", instead of
959 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
960 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
961 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
ee8ae9e4
BS		 962 for branch on CTR. We only handle the taken/not-taken hint here.
963 Note that we don't relax the conditions tested here when
964 disassembling with -Many because insns using extract_bdm and
965 extract_bdp always occur in pairs. One or the other will always
966 be valid. */
b9adb4a6 967
b9adb4a6 968static unsigned long
eca8f888
BS		 969insert_bdm (unsigned long insn,
970 long value,
971 int dialect,
972 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6 973{
eca8f888
BS		 974 if ((dialect & PPC_OPCODE_POWER4) == 0)
975 {
976 if ((value & 0x8000) != 0)
977 insn |= 1 << 21;
978 }
979 else
980 {
981 if ((insn & (0x14 << 21)) == (0x04 << 21))
982 insn |= 0x02 << 21;
983 else if ((insn & (0x14 << 21)) == (0x10 << 21))
984 insn |= 0x08 << 21;
985 }
b9adb4a6
FB		 986 return insn | (value & 0xfffc);
987}
988
989static long
eca8f888
BS		 990extract_bdm (unsigned long insn,
991 int dialect,
992 int *invalid)
b9adb4a6 993{
eca8f888
BS		 994 if ((dialect & PPC_OPCODE_POWER4) == 0)
995 {
996 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
997 *invalid = 1;
998 }
b9adb4a6 999 else
eca8f888
BS		 1000 {
1001 if ((insn & (0x17 << 21)) != (0x06 << 21)
1002 && (insn & (0x1d << 21)) != (0x18 << 21))
1003 *invalid = 1;
1004 }
1005
1006 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
b9adb4a6
FB		 1007}
1008
1009/* The BD field in a B form instruction when the + modifier is used.
1010 This is like BDM, above, except that the branch is expected to be
1011 taken. */
1012
b9adb4a6 1013static unsigned long
eca8f888
BS		 1014insert_bdp (unsigned long insn,
1015 long value,
1016 int dialect,
1017 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6 1018{
eca8f888
BS		 1019 if ((dialect & PPC_OPCODE_POWER4) == 0)
1020 {
1021 if ((value & 0x8000) == 0)
1022 insn |= 1 << 21;
1023 }
1024 else
1025 {
1026 if ((insn & (0x14 << 21)) == (0x04 << 21))
1027 insn |= 0x03 << 21;
1028 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1029 insn |= 0x09 << 21;
1030 }
b9adb4a6
FB		 1031 return insn | (value & 0xfffc);
1032}
1033
1034static long
eca8f888
BS		 1035extract_bdp (unsigned long insn,
1036 int dialect,
1037 int *invalid)
b9adb4a6 1038{
eca8f888
BS		 1039 if ((dialect & PPC_OPCODE_POWER4) == 0)
1040 {
1041 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1042 *invalid = 1;
1043 }
b9adb4a6 1044 else
eca8f888
BS		 1045 {
1046 if ((insn & (0x17 << 21)) != (0x07 << 21)
1047 && (insn & (0x1d << 21)) != (0x19 << 21))
1048 *invalid = 1;
1049 }
1050
1051 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
b9adb4a6
FB		 1052}
1053
1054/* Check for legal values of a BO field. */
1055
1056static int
ee8ae9e4 1057valid_bo (long value, int dialect, int extract)
eca8f888
BS		 1058{
1059 if ((dialect & PPC_OPCODE_POWER4) == 0)
1060 {
ee8ae9e4 1061 int valid;
eca8f888
BS		 1062 /* Certain encodings have bits that are required to be zero.
1063 These are (z must be zero, y may be anything):
1064 001zy
1065 011zy
1066 1z00y
1067 1z01y
1068 1z1zz
1069 */
1070 switch (value & 0x14)
1071 {
1072 default:
1073 case 0:
ee8ae9e4
BS		 1074 valid = 1;
1075 break;
eca8f888 1076 case 0x4:
ee8ae9e4
BS		 1077 valid = (value & 0x2) == 0;
1078 break;
eca8f888 1079 case 0x10:
ee8ae9e4
BS		 1080 valid = (value & 0x8) == 0;
1081 break;
eca8f888 1082 case 0x14:
ee8ae9e4
BS		 1083 valid = value == 0x14;
1084 break;
eca8f888 1085 }
ee8ae9e4
BS		 1086 /* When disassembling with -Many, accept power4 encodings too. */
1087 if (valid
1088 || (dialect & PPC_OPCODE_ANY) == 0
1089 || !extract)
1090 return valid;
eca8f888 1091 }
ee8ae9e4
BS		 1092
1093 /* Certain encodings have bits that are required to be zero.
1094 These are (z must be zero, a & t may be anything):
1095 0000z
1096 0001z
1097 0100z
1098 0101z
1099 001at
1100 011at
1101 1a00t
1102 1a01t
1103 1z1zz
1104 */
1105 if ((value & 0x14) == 0)
1106 return (value & 0x1) == 0;
1107 else if ((value & 0x14) == 0x14)
1108 return value == 0x14;
eca8f888 1109 else
ee8ae9e4 1110 return 1;
b9adb4a6
FB		 1111}
1112
1113/* The BO field in a B form instruction. Warn about attempts to set
1114 the field to an illegal value. */
1115
1116static unsigned long
eca8f888
BS		 1117insert_bo (unsigned long insn,
1118 long value,
1119 int dialect,
1120 const char **errmsg)
1121{
ee8ae9e4 1122 if (!valid_bo (value, dialect, 0))
ca66f1a1 1123 *errmsg = "invalid conditional option";
b9adb4a6
FB		 1124 return insn | ((value & 0x1f) << 21);
1125}
1126
1127static long
eca8f888
BS		 1128extract_bo (unsigned long insn,
1129 int dialect,
1130 int *invalid)
b9adb4a6 1131{
eca8f888 1132 long value;
b9adb4a6
FB		 1133
1134 value = (insn >> 21) & 0x1f;
ee8ae9e4 1135 if (!valid_bo (value, dialect, 1))
b9adb4a6
FB		 1136 *invalid = 1;
1137 return value;
1138}
1139
1140/* The BO field in a B form instruction when the + or - modifier is
1141 used. This is like the BO field, but it must be even. When
1142 extracting it, we force it to be even. */
1143
1144static unsigned long
eca8f888
BS		 1145insert_boe (unsigned long insn,
1146 long value,
1147 int dialect,
1148 const char **errmsg)
b9adb4a6 1149{
ee8ae9e4 1150 if (!valid_bo (value, dialect, 0))
ca66f1a1 1151 *errmsg = "invalid conditional option";
eca8f888 1152 else if ((value & 1) != 0)
ca66f1a1 1153 *errmsg = "attempt to set y bit when using + or - modifier";
eca8f888 1154
b9adb4a6
FB		 1155 return insn | ((value & 0x1f) << 21);
1156}
1157
1158static long
eca8f888
BS		 1159extract_boe (unsigned long insn,
1160 int dialect,
1161 int *invalid)
b9adb4a6 1162{
eca8f888 1163 long value;
b9adb4a6
FB		 1164
1165 value = (insn >> 21) & 0x1f;
ee8ae9e4 1166 if (!valid_bo (value, dialect, 1))
b9adb4a6
FB		 1167 *invalid = 1;
1168 return value & 0x1e;
1169}
1170
eca8f888
BS		 1171/* FXM mask in mfcr and mtcrf instructions. */
1172
1173static unsigned long
1174insert_fxm (unsigned long insn,
1175 long value,
1176 int dialect,
1177 const char **errmsg)
1178{
1179 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1180 one bit of the mask field is set. */
1181 if ((insn & (1 << 20)) != 0)
1182 {
1183 if (value == 0 || (value & -value) != value)
1184 {
ca66f1a1 1185 *errmsg = "invalid mask field";
eca8f888
BS		 1186 value = 0;
1187 }
1188 }
1189
1190 /* If the optional field on mfcr is missing that means we want to use
1191 the old form of the instruction that moves the whole cr. In that
1192 case we'll have VALUE zero. There doesn't seem to be a way to
1193 distinguish this from the case where someone writes mfcr %r3,0. */
1194 else if (value == 0)
1195 ;
1196
1197 /* If only one bit of the FXM field is set, we can use the new form
1198 of the instruction, which is faster. Unlike the Power4 branch hint
1199 encoding, this is not backward compatible. Do not generate the
1200 new form unless -mpower4 has been given, or -many and the two
1201 operand form of mfcr was used. */
1202 else if ((value & -value) == value
1203 && ((dialect & PPC_OPCODE_POWER4) != 0
1204 || ((dialect & PPC_OPCODE_ANY) != 0
1205 && (insn & (0x3ff << 1)) == 19 << 1)))
1206 insn |= 1 << 20;
1207
1208 /* Any other value on mfcr is an error. */
1209 else if ((insn & (0x3ff << 1)) == 19 << 1)
1210 {
ca66f1a1 1211 *errmsg = "ignoring invalid mfcr mask";
eca8f888
BS		 1212 value = 0;
1213 }
1214
1215 return insn | ((value & 0xff) << 12);
1216}
1217
1218static long
1219extract_fxm (unsigned long insn,
1220 int dialect ATTRIBUTE_UNUSED,
1221 int *invalid)
1222{
1223 long mask = (insn >> 12) & 0xff;
1224
1225 /* Is this a Power4 insn? */
1226 if ((insn & (1 << 20)) != 0)
1227 {
1228 /* Exactly one bit of MASK should be set. */
1229 if (mask == 0 || (mask & -mask) != mask)
1230 *invalid = 1;
1231 }
1232
1233 /* Check that non-power4 form of mfcr has a zero MASK. */
1234 else if ((insn & (0x3ff << 1)) == 19 << 1)
1235 {
1236 if (mask != 0)
1237 *invalid = 1;
1238 }
1239
1240 return mask;
b9adb4a6
FB		 1241}
1242
b9adb4a6
FB		 1243/* The MB and ME fields in an M form instruction expressed as a single
1244 operand which is itself a bitmask. The extraction function always
1245 marks it as invalid, since we never want to recognize an
1246 instruction which uses a field of this type. */
1247
1248static unsigned long
eca8f888
BS		 1249insert_mbe (unsigned long insn,
1250 long value,
1251 int dialect ATTRIBUTE_UNUSED,
1252 const char **errmsg)
b9adb4a6 1253{
eca8f888
BS		 1254 unsigned long uval, mask;
1255 int mb, me, mx, count, last;
b9adb4a6
FB		 1256
1257 uval = value;
1258
1259 if (uval == 0)
1260 {
ca66f1a1 1261 *errmsg = "illegal bitmask";
b9adb4a6
FB		 1262 return insn;
1263 }
1264
eca8f888
BS		 1265 mb = 0;
1266 me = 32;
1267 if ((uval & 1) != 0)
1268 last = 1;
1269 else
1270 last = 0;
1271 count = 0;
b9adb4a6 1272
eca8f888
BS		 1273 /* mb: location of last 0->1 transition */
1274 /* me: location of last 1->0 transition */
1275 /* count: # transitions */
b9adb4a6 1276
eca8f888 1277 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
b9adb4a6 1278 {
eca8f888
BS		 1279 if ((uval & mask) && !last)
1280 {
1281 ++count;
1282 mb = mx;
1283 last = 1;
1284 }
1285 else if (!(uval & mask) && last)
1286 {
1287 ++count;
1288 me = mx;
1289 last = 0;
1290 }
b9adb4a6 1291 }
eca8f888
BS		 1292 if (me == 0)
1293 me = 32;
b9adb4a6 1294
eca8f888 1295 if (count != 2 && (count != 0 || ! last))
ca66f1a1 1296 *errmsg = "illegal bitmask";
eca8f888
BS		 1297
1298 return insn | (mb << 6) | ((me - 1) << 1);
b9adb4a6
FB		 1299}
1300
1301static long
eca8f888
BS		 1302extract_mbe (unsigned long insn,
1303 int dialect ATTRIBUTE_UNUSED,
1304 int *invalid)
b9adb4a6
FB		 1305{
1306 long ret;
1307 int mb, me;
1308 int i;
1309
eca8f888 1310 *invalid = 1;
b9adb4a6 1311
b9adb4a6
FB		 1312 mb = (insn >> 6) & 0x1f;
1313 me = (insn >> 1) & 0x1f;
eca8f888
BS		 1314 if (mb < me + 1)
1315 {
1316 ret = 0;
1317 for (i = mb; i <= me; i++)
1318 ret |= 1L << (31 - i);
1319 }
1320 else if (mb == me + 1)
1321 ret = ~0;
1322 else /* (mb > me + 1) */
1323 {
1324 ret = ~0;
1325 for (i = me + 1; i < mb; i++)
1326 ret &= ~(1L << (31 - i));
1327 }
b9adb4a6
FB		 1328 return ret;
1329}
1330
1331/* The MB or ME field in an MD or MDS form instruction. The high bit
1332 is wrapped to the low end. */
1333
b9adb4a6 1334static unsigned long
eca8f888
BS		 1335insert_mb6 (unsigned long insn,
1336 long value,
1337 int dialect ATTRIBUTE_UNUSED,
1338 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1339{
1340 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1341}
1342
b9adb4a6 1343static long
eca8f888
BS		 1344extract_mb6 (unsigned long insn,
1345 int dialect ATTRIBUTE_UNUSED,
1346 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1347{
1348 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1349}
1350
1351/* The NB field in an X form instruction. The value 32 is stored as
1352 0. */
1353
b9adb4a6 1354static long
eca8f888
BS		 1355extract_nb (unsigned long insn,
1356 int dialect ATTRIBUTE_UNUSED,
1357 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1358{
1359 long ret;
1360
1361 ret = (insn >> 11) & 0x1f;
1362 if (ret == 0)
1363 ret = 32;
1364 return ret;
1365}
1366
1367/* The NSI field in a D form instruction. This is the same as the SI
1368 field, only negated. The extraction function always marks it as
1369 invalid, since we never want to recognize an instruction which uses
1370 a field of this type. */
1371
b9adb4a6 1372static unsigned long
eca8f888
BS		 1373insert_nsi (unsigned long insn,
1374 long value,
1375 int dialect ATTRIBUTE_UNUSED,
1376 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6 1377{
eca8f888 1378 return insn | (-value & 0xffff);
b9adb4a6
FB		 1379}
1380
1381static long
eca8f888
BS		 1382extract_nsi (unsigned long insn,
1383 int dialect ATTRIBUTE_UNUSED,
1384 int *invalid)
b9adb4a6 1385{
eca8f888
BS		 1386 *invalid = 1;
1387 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
b9adb4a6
FB		 1388}
1389
1390/* The RA field in a D or X form instruction which is an updating
1391 load, which means that the RA field may not be zero and may not
1392 equal the RT field. */
1393
1394static unsigned long
eca8f888
BS		 1395insert_ral (unsigned long insn,
1396 long value,
1397 int dialect ATTRIBUTE_UNUSED,
1398 const char **errmsg)
b9adb4a6
FB		 1399{
1400 if (value == 0
eca8f888 1401 || (unsigned long) value == ((insn >> 21) & 0x1f))
b9adb4a6
FB		 1402 *errmsg = "invalid register operand when updating";
1403 return insn | ((value & 0x1f) << 16);
1404}
1405
1406/* The RA field in an lmw instruction, which has special value
1407 restrictions. */
1408
1409static unsigned long
eca8f888
BS		 1410insert_ram (unsigned long insn,
1411 long value,
1412 int dialect ATTRIBUTE_UNUSED,
1413 const char **errmsg)
b9adb4a6 1414{
eca8f888 1415 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
ca66f1a1 1416 *errmsg = "index register in load range";
eca8f888
BS		 1417 return insn | ((value & 0x1f) << 16);
1418}
1419
1420/* The RA field in the DQ form lq instruction, which has special
1421 value restrictions. */
1422
1423static unsigned long
1424insert_raq (unsigned long insn,
1425 long value,
1426 int dialect ATTRIBUTE_UNUSED,
1427 const char **errmsg)
1428{
1429 long rtvalue = (insn & RT_MASK) >> 21;
1430
1431 if (value == rtvalue)
ca66f1a1 1432 *errmsg = "source and target register operands must be different";
b9adb4a6
FB		 1433 return insn | ((value & 0x1f) << 16);
1434}
1435
1436/* The RA field in a D or X form instruction which is an updating
1437 store or an updating floating point load, which means that the RA
1438 field may not be zero. */
1439
1440static unsigned long
eca8f888
BS		 1441insert_ras (unsigned long insn,
1442 long value,
1443 int dialect ATTRIBUTE_UNUSED,
1444 const char **errmsg)
b9adb4a6
FB		 1445{
1446 if (value == 0)
ca66f1a1 1447 *errmsg = "invalid register operand when updating";
b9adb4a6
FB		 1448 return insn | ((value & 0x1f) << 16);
1449}
1450
1451/* The RB field in an X form instruction when it must be the same as
1452 the RS field in the instruction. This is used for extended
1453 mnemonics like mr. This operand is marked FAKE. The insertion
1454 function just copies the BT field into the BA field, and the
1455 extraction function just checks that the fields are the same. */
1456
5fafdf24 1457static unsigned long
eca8f888
BS		 1458insert_rbs (unsigned long insn,
1459 long value ATTRIBUTE_UNUSED,
1460 int dialect ATTRIBUTE_UNUSED,
1461 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1462{
1463 return insn | (((insn >> 21) & 0x1f) << 11);
1464}
1465
1466static long
eca8f888
BS		 1467extract_rbs (unsigned long insn,
1468 int dialect ATTRIBUTE_UNUSED,
1469 int *invalid)
b9adb4a6 1470{
eca8f888 1471 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
b9adb4a6
FB		 1472 *invalid = 1;
1473 return 0;
1474}
1475
1476/* The SH field in an MD form instruction. This is split. */
1477
b9adb4a6 1478static unsigned long
eca8f888
BS		 1479insert_sh6 (unsigned long insn,
1480 long value,
1481 int dialect ATTRIBUTE_UNUSED,
1482 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1483{
1484 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1485}
1486
b9adb4a6 1487static long
eca8f888
BS		 1488extract_sh6 (unsigned long insn,
1489 int dialect ATTRIBUTE_UNUSED,
1490 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1491{
1492 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1493}
1494
1495/* The SPR field in an XFX form instruction. This is flipped--the
1496 lower 5 bits are stored in the upper 5 and vice- versa. */
1497
1498static unsigned long
eca8f888
BS		 1499insert_spr (unsigned long insn,
1500 long value,
1501 int dialect ATTRIBUTE_UNUSED,
1502 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1503{
1504 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1505}
1506
1507static long
eca8f888
BS		 1508extract_spr (unsigned long insn,
1509 int dialect ATTRIBUTE_UNUSED,
1510 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1511{
1512 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1513}
1514
eca8f888
BS		 1515/* Some dialects have 8 SPRG registers instead of the standard 4. */
1516
1517static unsigned long
1518insert_sprg (unsigned long insn,
1519 long value,
1520 int dialect,
1521 const char **errmsg)
1522{
1523 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1524 as a synonym. If ever a 405 specific dialect is added this
1525 check should use that instead. */
1526 if (value > 7
1527 || (value > 3
1528 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
ca66f1a1 1529 *errmsg = "invalid sprg number";
eca8f888
BS		 1530
1531 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1532 user mode. Anything else must use spr 272..279. */
1533 if (value <= 3 || (insn & 0x100) != 0)
1534 value |= 0x10;
1535
1536 return insn | ((value & 0x17) << 16);
1537}
1538
1539static long
1540extract_sprg (unsigned long insn,
1541 int dialect,
1542 int *invalid)
1543{
1544 unsigned long val = (insn >> 16) & 0x1f;
1545
1546 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1547 If not BOOKE or 405, then both use only 272..275. */
1548 if (val <= 3
1549 || (val < 0x10 && (insn & 0x100) != 0)
1550 || (val - 0x10 > 3
1551 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1552 *invalid = 1;
1553 return val & 7;
1554}
1555
b9adb4a6
FB		 1556/* The TBR field in an XFX instruction. This is just like SPR, but it
1557 is optional. When TBR is omitted, it must be inserted as 268 (the
1558 magic number of the TB register). These functions treat 0
1559 (indicating an omitted optional operand) as 268. This means that
1560 ``mftb 4,0'' is not handled correctly. This does not matter very
1561 much, since the architecture manual does not define mftb as
1562 accepting any values other than 268 or 269. */
1563
1564#define TB (268)
1565
1566static unsigned long
eca8f888
BS		 1567insert_tbr (unsigned long insn,
1568 long value,
1569 int dialect ATTRIBUTE_UNUSED,
1570 const char **errmsg ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1571{
1572 if (value == 0)
1573 value = TB;
1574 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1575}
1576
1577static long
eca8f888
BS		 1578extract_tbr (unsigned long insn,
1579 int dialect ATTRIBUTE_UNUSED,
1580 int *invalid ATTRIBUTE_UNUSED)
b9adb4a6
FB		 1581{
1582 long ret;
1583
1584 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1585 if (ret == TB)
1586 ret = 0;
1587 return ret;
1588}
1589\f
1590/* Macros used to form opcodes. */
1591
1592/* The main opcode. */
eca8f888 1593#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
b9adb4a6
FB		 1594#define OP_MASK OP (0x3f)
1595
1596/* The main opcode combined with a trap code in the TO field of a D
1597 form instruction. Used for extended mnemonics for the trap
1598 instructions. */
eca8f888 1599#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
b9adb4a6
FB		 1600#define OPTO_MASK (OP_MASK | TO_MASK)
1601
1602/* The main opcode combined with a comparison size bit in the L field
1603 of a D form or X form instruction. Used for extended mnemonics for
1604 the comparison instructions. */
eca8f888 1605#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
b9adb4a6
FB		 1606#define OPL_MASK OPL (0x3f,1)
1607
1608/* An A form instruction. */
eca8f888 1609#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
b9adb4a6
FB		 1610#define A_MASK A (0x3f, 0x1f, 1)
1611
1612/* An A_MASK with the FRB field fixed. */
1613#define AFRB_MASK (A_MASK | FRB_MASK)
1614
1615/* An A_MASK with the FRC field fixed. */
1616#define AFRC_MASK (A_MASK | FRC_MASK)
1617
1618/* An A_MASK with the FRA and FRC fields fixed. */
1619#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1620
ee8ae9e4
BS		 1621/* An AFRAFRC_MASK, but with L bit clear. */
1622#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1623
b9adb4a6 1624/* A B form instruction. */
eca8f888 1625#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
b9adb4a6
FB		 1626#define B_MASK B (0x3f, 1, 1)
1627
1628/* A B form instruction setting the BO field. */
eca8f888 1629#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
b9adb4a6
FB		 1630#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1631
1632/* A BBO_MASK with the y bit of the BO field removed. This permits
1633 matching a conditional branch regardless of the setting of the y
eca8f888
BS		 1634 bit. Similarly for the 'at' bits used for power4 branch hints. */
1635#define Y_MASK (((unsigned long) 1) << 21)
1636#define AT1_MASK (((unsigned long) 3) << 21)
1637#define AT2_MASK (((unsigned long) 9) << 21)
1638#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1639#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
b9adb4a6
FB		 1640
1641/* A B form instruction setting the BO field and the condition bits of
1642 the BI field. */
1643#define BBOCB(op, bo, cb, aa, lk) \
eca8f888 1644 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
b9adb4a6
FB		 1645#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1646
1647/* A BBOCB_MASK with the y bit of the BO field removed. */
1648#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
eca8f888
BS		 1649#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1650#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
b9adb4a6
FB		 1651
1652/* A BBOYCB_MASK in which the BI field is fixed. */
1653#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
eca8f888
BS		 1654#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1655
bd97a59e 1656/* A Context form instruction. */
eca8f888
BS		 1657#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1658#define CTX_MASK CTX(0x3f, 0x7)
1659
bd97a59e 1660/* A User Context form instruction. */
eca8f888
BS		 1661#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1662#define UCTX_MASK UCTX(0x3f, 0x1f)
b9adb4a6
FB		 1663
1664/* The main opcode mask with the RA field clear. */
1665#define DRA_MASK (OP_MASK | RA_MASK)
1666
1667/* A DS form instruction. */
1668#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1669#define DS_MASK DSO (0x3f, 3)
1670
eca8f888
BS		 1671/* A DE form instruction. */
1672#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1673#define DE_MASK DEO (0x3e, 0xf)
1674
1675/* An EVSEL form instruction. */
1676#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1677#define EVSEL_MASK EVSEL(0x3f, 0xff)
1678
b9adb4a6
FB		 1679/* An M form instruction. */
1680#define M(op, rc) (OP (op) | ((rc) & 1))
1681#define M_MASK M (0x3f, 1)
1682
1683/* An M form instruction with the ME field specified. */
eca8f888 1684#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
b9adb4a6
FB		 1685
1686/* An M_MASK with the MB and ME fields fixed. */
1687#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1688
1689/* An M_MASK with the SH and ME fields fixed. */
1690#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1691
1692/* An MD form instruction. */
eca8f888 1693#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
b9adb4a6
FB		 1694#define MD_MASK MD (0x3f, 0x7, 1)
1695
1696/* An MD_MASK with the MB field fixed. */
1697#define MDMB_MASK (MD_MASK | MB6_MASK)
1698
1699/* An MD_MASK with the SH field fixed. */
1700#define MDSH_MASK (MD_MASK | SH6_MASK)
1701
1702/* An MDS form instruction. */
eca8f888 1703#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
b9adb4a6
FB		 1704#define MDS_MASK MDS (0x3f, 0xf, 1)
1705
1706/* An MDS_MASK with the MB field fixed. */
1707#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1708
1709/* An SC form instruction. */
eca8f888
BS		 1710#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1711#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1712
bd97a59e 1713/* A VX form instruction. */
eca8f888
BS		 1714#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1715
1716/* The mask for an VX form instruction. */
1717#define VX_MASK VX(0x3f, 0x7ff)
1718
bd97a59e 1719/* A VA form instruction. */
eca8f888
BS		 1720#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1721
bd97a59e 1722/* The mask for a VA form instruction. */
eca8f888
BS		 1723#define VXA_MASK VXA(0x3f, 0x3f)
1724
bd97a59e 1725/* A VXR form instruction. */
eca8f888
BS		 1726#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1727
1728/* The mask for a VXR form instruction. */
1729#define VXR_MASK VXR(0x3f, 0x3ff, 1)
b9adb4a6
FB		 1730
1731/* An X form instruction. */
eca8f888 1732#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
b9adb4a6 1733
ee8ae9e4
BS		 1734/* A Z form instruction. */
1735#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1736
b9adb4a6
FB		 1737/* An X form instruction with the RC bit specified. */
1738#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1739
ee8ae9e4
BS		 1740/* A Z form instruction with the RC bit specified. */
1741#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1742
b9adb4a6
FB		 1743/* The mask for an X form instruction. */
1744#define X_MASK XRC (0x3f, 0x3ff, 1)
1745
ee8ae9e4
BS		 1746/* The mask for a Z form instruction. */
1747#define Z_MASK ZRC (0x3f, 0x1ff, 1)
1748#define Z2_MASK ZRC (0x3f, 0xff, 1)
1749
b9adb4a6
FB		 1750/* An X_MASK with the RA field fixed. */
1751#define XRA_MASK (X_MASK | RA_MASK)
1752
ee8ae9e4
BS		 1753/* An XRA_MASK with the W field clear. */
1754#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1755
b9adb4a6
FB		 1756/* An X_MASK with the RB field fixed. */
1757#define XRB_MASK (X_MASK | RB_MASK)
1758
1759/* An X_MASK with the RT field fixed. */
1760#define XRT_MASK (X_MASK | RT_MASK)
1761
ee8ae9e4
BS		 1762/* An XRT_MASK mask with the L bits clear. */
1763#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1764
b9adb4a6
FB		 1765/* An X_MASK with the RA and RB fields fixed. */
1766#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1767
eca8f888
BS		 1768/* An XRARB_MASK, but with the L bit clear. */
1769#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1770
b9adb4a6
FB		 1771/* An X_MASK with the RT and RA fields fixed. */
1772#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1773
eca8f888
BS		 1774/* An XRTRA_MASK, but with L bit clear. */
1775#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1776
1777/* An X form instruction with the L bit specified. */
1778#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
b9adb4a6
FB		 1779
1780/* The mask for an X form comparison instruction. */
eca8f888 1781#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
b9adb4a6
FB		 1782
1783/* The mask for an X form comparison instruction with the L field
1784 fixed. */
eca8f888 1785#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
b9adb4a6
FB		 1786
1787/* An X form trap instruction with the TO field specified. */
eca8f888 1788#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
b9adb4a6
FB		 1789#define XTO_MASK (X_MASK | TO_MASK)
1790
eca8f888
BS		 1791/* An X form tlb instruction with the SH field specified. */
1792#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1793#define XTLB_MASK (X_MASK | SH_MASK)
1794
1795/* An X form sync instruction. */
1796#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1797
1798/* An X form sync instruction with everything filled in except the LS field. */
1799#define XSYNC_MASK (0xff9fffff)
1800
ee8ae9e4
BS		 1801/* An X_MASK, but with the EH bit clear. */
1802#define XEH_MASK (X_MASK & ~((unsigned long )1))
1803
eca8f888
BS		 1804/* An X form AltiVec dss instruction. */
1805#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1806#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1807
b9adb4a6 1808/* An XFL form instruction. */
eca8f888 1809#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
ee8ae9e4 1810#define XFL_MASK XFL (0x3f, 0x3ff, 1)
eca8f888
BS		 1811
1812/* An X form isel instruction. */
1813#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1814#define XISEL_MASK XISEL(0x3f, 0x1f)
b9adb4a6
FB		 1815
1816/* An XL form instruction with the LK field set to 0. */
eca8f888 1817#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
b9adb4a6
FB		 1818
1819/* An XL form instruction which uses the LK field. */
1820#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1821
1822/* The mask for an XL form instruction. */
1823#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1824
1825/* An XL form instruction which explicitly sets the BO field. */
1826#define XLO(op, bo, xop, lk) \
eca8f888 1827 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
b9adb4a6
FB		 1828#define XLO_MASK (XL_MASK | BO_MASK)
1829
1830/* An XL form instruction which explicitly sets the y bit of the BO
1831 field. */
eca8f888 1832#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
b9adb4a6
FB		 1833#define XLYLK_MASK (XL_MASK | Y_MASK)
1834
1835/* An XL form instruction which sets the BO field and the condition
1836 bits of the BI field. */
1837#define XLOCB(op, bo, cb, xop, lk) \
eca8f888 1838 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
b9adb4a6
FB		 1839#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1840
1841/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1842#define XLBB_MASK (XL_MASK | BB_MASK)
1843#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1844#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1845
eca8f888
BS		 1846/* A mask for branch instructions using the BH field. */
1847#define XLBH_MASK (XL_MASK | (0x1c << 11))
1848
b9adb4a6
FB		 1849/* An XL_MASK with the BO and BB fields fixed. */
1850#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1851
1852/* An XL_MASK with the BO, BI and BB fields fixed. */
1853#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1854
1855/* An XO form instruction. */
1856#define XO(op, xop, oe, rc) \
eca8f888 1857 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
b9adb4a6
FB		 1858#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1859
1860/* An XO_MASK with the RB field fixed. */
1861#define XORB_MASK (XO_MASK | RB_MASK)
1862
1863/* An XS form instruction. */
eca8f888 1864#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
b9adb4a6
FB		 1865#define XS_MASK XS (0x3f, 0x1ff, 1)
1866
1867/* A mask for the FXM version of an XFX form instruction. */
eca8f888 1868#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
b9adb4a6
FB		 1869
1870/* An XFX form instruction with the FXM field filled in. */
eca8f888
BS		 1871#define XFXM(op, xop, fxm, p4) \
1872 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1873 | ((unsigned long)(p4) << 20))
b9adb4a6
FB		 1874
1875/* An XFX form instruction with the SPR field filled in. */
1876#define XSPR(op, xop, spr) \
eca8f888 1877 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
b9adb4a6
FB		 1878#define XSPR_MASK (X_MASK | SPR_MASK)
1879
1880/* An XFX form instruction with the SPR field filled in except for the
1881 SPRBAT field. */
1882#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1883
1884/* An XFX form instruction with the SPR field filled in except for the
1885 SPRG field. */
ee8ae9e4 1886#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
eca8f888
BS		 1887
1888/* An X form instruction with everything filled in except the E field. */
1889#define XE_MASK (0xffff7fff)
1890
1891/* An X form user context instruction. */
1892#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1893#define XUC_MASK XUC(0x3f, 0x1f)
b9adb4a6
FB		 1894
1895/* The BO encodings used in extended conditional branch mnemonics. */
1896#define BODNZF (0x0)
1897#define BODNZFP (0x1)
1898#define BODZF (0x2)
1899#define BODZFP (0x3)
b9adb4a6
FB		 1900#define BODNZT (0x8)
1901#define BODNZTP (0x9)
1902#define BODZT (0xa)
1903#define BODZTP (0xb)
eca8f888
BS		 1904
1905#define BOF (0x4)
1906#define BOFP (0x5)
1907#define BOFM4 (0x6)
1908#define BOFP4 (0x7)
b9adb4a6
FB		 1909#define BOT (0xc)
1910#define BOTP (0xd)
eca8f888
BS		 1911#define BOTM4 (0xe)
1912#define BOTP4 (0xf)
1913
b9adb4a6
FB		 1914#define BODNZ (0x10)
1915#define BODNZP (0x11)
1916#define BODZ (0x12)
1917#define BODZP (0x13)
eca8f888
BS		 1918#define BODNZM4 (0x18)
1919#define BODNZP4 (0x19)
1920#define BODZM4 (0x1a)
1921#define BODZP4 (0x1b)
1922
b9adb4a6
FB		 1923#define BOU (0x14)
1924
1925/* The BI condition bit encodings used in extended conditional branch
1926 mnemonics. */
1927#define CBLT (0)
1928#define CBGT (1)
1929#define CBEQ (2)
1930#define CBSO (3)
1931
1932/* The TO encodings used in extended trap mnemonics. */
1933#define TOLGT (0x1)
1934#define TOLLT (0x2)
1935#define TOEQ (0x4)
1936#define TOLGE (0x5)
1937#define TOLNL (0x5)
1938#define TOLLE (0x6)
1939#define TOLNG (0x6)
1940#define TOGT (0x8)
1941#define TOGE (0xc)
1942#define TONL (0xc)
1943#define TOLT (0x10)
1944#define TOLE (0x14)
1945#define TONG (0x14)
1946#define TONE (0x18)
1947#define TOU (0x1f)
1948\f
1949/* Smaller names for the flags so each entry in the opcodes table will
1950 fit on a single line. */
eca8f888
BS		 1951#undef PPC
1952#define PPC PPC_OPCODE_PPC
1953#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1954#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1955#define POWER4 PPC_OPCODE_POWER4
1956#define POWER5 PPC_OPCODE_POWER5
ee8ae9e4 1957#define POWER6 PPC_OPCODE_POWER6
8d8dd793
RH		 1958/* Documentation purposes only; we don't actually check the isa for disas. */
1959#define POWER7 PPC_OPCODE_POWER6
1960#define POWER9 PPC_OPCODE_POWER6
ee8ae9e4 1961#define CELL PPC_OPCODE_CELL
eca8f888
BS		 1962#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1963#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1964#define PPC403 PPC_OPCODE_403
1965#define PPC405 PPC403
1966#define PPC440 PPC_OPCODE_440
1967#define PPC750 PPC
1968#define PPC860 PPC
1969#define PPCVEC PPC_OPCODE_ALTIVEC
1970#define POWER PPC_OPCODE_POWER
1971#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1972#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1973#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1974#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1975#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1976#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1977#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1978#define MFDEC1 PPC_OPCODE_POWER
1979#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1980#define BOOKE PPC_OPCODE_BOOKE
1981#define BOOKE64 PPC_OPCODE_BOOKE64
1982#define CLASSIC PPC_OPCODE_CLASSIC
1983#define PPCE300 PPC_OPCODE_E300
1984#define PPCSPE PPC_OPCODE_SPE
1985#define PPCISEL PPC_OPCODE_ISEL
1986#define PPCEFS PPC_OPCODE_EFS
1987#define PPCBRLK PPC_OPCODE_BRLOCK
1988#define PPCPMR PPC_OPCODE_PMR
1989#define PPCCHLK PPC_OPCODE_CACHELCK
1990#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1991#define PPCRFMCI PPC_OPCODE_RFMCI
b9adb4a6
FB		 1992\f
1993/* The opcode table.
1994
1995 The format of the opcode table is:
1996
1997 NAME OPCODE MASK FLAGS { OPERANDS }
1998
1999 NAME is the name of the instruction.
2000 OPCODE is the instruction opcode.
2001 MASK is the opcode mask; this is used to tell the disassembler
2002 which bits in the actual opcode must match OPCODE.
2003 FLAGS are flags indicated what processors support the instruction.
2004 OPERANDS is the list of operands.
2005
2006 The disassembler reads the table in order and prints the first
2007 instruction which matches, so this table is sorted to put more
2008 specific instructions before more general instructions. It is also
2009 sorted by major opcode. */
2010
2011const struct powerpc_opcode powerpc_opcodes[] = {
eca8f888
BS		 2012{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
2013{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
2014{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
2015{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
2016{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
2017{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
2018{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2019{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
2020{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
2021{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
2022{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
2023{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
2024{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
2025{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
2026{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
2027{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
2028
2029{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
2030{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
2031{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
2032{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
2033{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
2034{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
2035{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
2036{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
2037{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
2038{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
2039{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2040{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
2041{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
2042{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
2043{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
2044{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
2045{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
2046{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
2047{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
2048{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
2049{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
2050{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
2051{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
2052{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
2053{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
2054{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
2055{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
2056{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
2057{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
2058{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2059
2060{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2061{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2062{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2063{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2064{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2065{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2066{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2067{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2068{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2069{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2070{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2071{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2072{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2073{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2074{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2075{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2076{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2077{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2078{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2079{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2080{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2081{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2082{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2083{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2084{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2085{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2086{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2087{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2088{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2089{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2090{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2091{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2092{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2093{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2094{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2095{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2096{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2097{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2098{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2099{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2100{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2101{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2102{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2103{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2104{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2105{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2106{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2107{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2108{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2109{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2110{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2111{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2112{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2113{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2114{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2115{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2116{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2117{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2118{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2119{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2120{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2121{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2122{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2123{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2124{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2125{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2126{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2127{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2128{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2129{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2130{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2131{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2132{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2133{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2134{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2135{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2136{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2137{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2138{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2139{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2140{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2141{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2142{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2143{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2144{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
2145{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
2146
2147 /* Double-precision opcodes. */
2148 /* Some of these conflict with AltiVec, so move them before, since
2149 PPCVEC includes the PPC_OPCODE_PPC set. */
2150{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
2151{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2152{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2153{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2154{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2155{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2156{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2157{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2158{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2159{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2160{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2161{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2162{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2163{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2164{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2165{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2166{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2167{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2168{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2169{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2170{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2171{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2172{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2173{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2174{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2175{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2176{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2177{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2178{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2179 /* End of double-precision opcodes. */
2180
2181{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2182{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2183{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2184{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2185{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2186{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2187{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2188{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2189{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2190{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2191{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2192{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2193{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2194{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2195{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2196{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2197{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2198{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2199{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2200{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2201{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2202{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2203{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2204{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2205{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2206{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2207{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2208{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2209{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2210{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2211{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2212{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2213{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2214{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2215{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2216{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2217{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2218{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2219{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2220{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2221{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2222{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2223{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2224{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2225{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2226{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2227{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2228{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2229{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2230{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2231{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2232{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2233{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2234{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2235{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2236{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2237{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2238{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2239{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2240{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2241{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2242{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2243{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2244{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2245{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2246{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2247{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2248{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2249{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2250{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2251{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2252{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2253{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2254{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2255{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2256{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2257{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2258{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2259{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2260{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2261{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2262{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2263{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2264{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2265{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2266{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2267{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2268{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2269{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2270{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2271{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2272{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2273{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2274{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2275{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2276{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2277{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2278{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2279{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2280{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2281{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2282{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2283{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2284{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2285{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2286{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2287{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2288{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2289{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2290{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2291{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
3e00884f 2292{ "vrldmi", VX(4, 197), VX_MASK, PPCVEC, { VD, VA, VB } },
09a245e1 2293{ "vrldnm", VX(4, 453), VX_MASK, PPCVEC, { VD, VA, VB } },
3e00884f 2294{ "vrlwmi", VX(4, 133), VX_MASK, PPCVEC, { VD, VA, VB} },
09a245e1 2295{ "vrlwnm", VX(4, 389), VX_MASK, PPCVEC, { VD, VA, VB } },
eca8f888
BS		 2296{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2297{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2298{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2299{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2300{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2301{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2302{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2303{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2304{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2305{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2306{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2307{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2308{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2309{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2310{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2311{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2312{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2313{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2314{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2315{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2316{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2317{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2318{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2319{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2320{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2321{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2322{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2323{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2324{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2325{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2326{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2327{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2328{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2329{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2330{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2331{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2332{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2333{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2334{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2335{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2336{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2337{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2338{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2339{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2340
2341{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2342{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2343{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2344{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2345{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2346{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2347{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2348{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2349{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2350{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2351{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2352{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2353{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2354
2355{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2356
2357{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2358{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2359{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2360{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2361{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2362{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2363{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2364{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2365{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2366{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2367
2368{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2369{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2370{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2371{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2372{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2373{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2374{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2375{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2376{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2377{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2378{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2379{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2380{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2381{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2382
2383{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2384{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2385{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2386{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2387{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2388{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2389
2390{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2391{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2392{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2393{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2394{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2395{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2396{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2397{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2398{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2399{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2400{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2401{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2402{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2403{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2404{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2405{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2406{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2407{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2408{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2409{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2410{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2411{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2412
2413{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2414{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2415{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2416{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2417{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2418{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2419{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2420{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2421{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2422{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2423{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2424{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2425{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2426{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2427
2428{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2429{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2430{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2431{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2432{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2433{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2434{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2435{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2436{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2437{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2438{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2439{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2440{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2441{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2442{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2443{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2444{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2445{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2446{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2447{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2448{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2449{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2450{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2451
2452{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2453{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2454{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2455{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2456{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2457{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2458{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2459{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2460{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2461{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2462{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2463{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2464{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2465{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2466{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2467{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2468{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2469{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2470{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2471{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2472{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2473{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2474{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2475
2476{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2477{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2478{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2479{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2480{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2481{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2482{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2483{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2484{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2485{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2486{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2487{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2488{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2489{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2490{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2491{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2492
2493{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2494{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2495{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2496{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2497{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2498{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2499{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2500{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2501{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2502{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2503{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2504{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2505
2506{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2507{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2508{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2509{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2510{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2511{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2512{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2513{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2514{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2515{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2516{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2517{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2518
2519{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2520{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2521{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2522{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2523{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2524{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2525
2526{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2527{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2528{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2529{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2530{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2531{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2532
2533{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2534{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2535{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2536{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2537{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2538{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2539{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2540{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2541
2542{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2543{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2544
2545{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2546{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2547{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2548{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2549
2550{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2551{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2552{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2553{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2554
2555{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2556{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2557{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2558{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2559{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2560{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2561{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2562{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2563
2564{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2565{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2566{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2567{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2568
2569{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2570{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2571{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2572{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2573
2574{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2575{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2576{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2577{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2578
2579{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2580{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2581{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2582{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2583
2584{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2585
2586{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2587{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2588
2589{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2590{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2591
2592{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2593{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2594
2595{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2596
2597{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2598{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2599{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2600{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2601
2602{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2603{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
b9adb4a6 2604{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
eca8f888 2605{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
b9adb4a6 2606
eca8f888
BS		 2607{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2608{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
b9adb4a6 2609{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
eca8f888
BS		 2610{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2611
2612{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2613{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2614{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2615
2616{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2617{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2618{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2619
2620{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2621{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2622{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2623{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2624{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2625{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2626
2627{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2628{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2629{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2630{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2631{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2632
2633{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2634{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2635{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2636{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2637{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2638{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2639{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2640{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2641{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2642{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2643{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2644{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2645{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2646{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2647{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2648{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2649{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2650{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2651{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2652{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2653{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2654{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2655{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2656{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2657{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2658{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2659{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2660{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2661{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2662{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2663{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2664{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2665{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2666{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2667{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2668{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2669{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2670{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2671{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2672{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2673{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2674{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2675{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2676{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2677{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2678{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2679{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2680{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2681{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2682{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2683{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2684{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2685{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2686{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2687{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2688{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2689{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2690{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2691{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2692{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2693{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2694{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2695{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2696{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2697{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2698{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2699{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2700{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2701{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2702{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2703{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2704{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2705{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2706{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2707{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2708{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2709{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2710{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2711{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2712{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2713{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2714{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2715{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2716{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2717{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2718{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2719{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2720{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2721{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2722{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2723{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2724{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2725{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2726{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2727{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2728{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2729{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2730{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2731{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2732{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2733{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2734{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2735{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2736{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2737{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2738{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2739{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2740{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2741{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2742{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2743{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2744{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2745{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2746{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2747{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2748{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2749{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2750{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2751{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2752{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2753{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2754{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2755{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2756{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2757{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2758{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2759{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2760{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2761{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2762{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2763{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2764{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2765{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2766{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2767{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2768{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2769{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2770{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2771{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2772{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2773{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2774{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2775{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2776{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2777{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2778{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2779{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2780{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2781{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2782{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2783{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2784{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2785{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2786{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2787{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2788{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2789{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2790{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2791{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2792{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2793{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2794{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2795{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2796{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2797{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2798{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2799{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2800{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2801{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2802{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2803{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2804{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2805{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2806{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2807{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2808{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2809{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2810{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2811{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2812{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2813{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2814{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2815{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2816{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2817{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2818{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2819{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2820{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2821{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2822{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2823{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2824{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2825{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2826{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2827{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2828{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2829{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2830{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2831{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2832{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2833{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2834{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2835{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2836{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2837{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2838{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2839{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2840{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2841{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2842{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2843{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2844{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2845{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2846{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2847{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2848{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2849{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2850{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2851{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2852{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2853{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2854{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2855{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2856{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2857{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2858{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2859{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2860{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2861{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2862{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2863{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2864{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2865{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2866{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2867{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2868{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2869{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2870{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2871{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2872{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2873{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2874{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2875{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2876{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2877{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2878{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2879{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2880{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2881{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2882{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2883{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2884{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2885{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2886{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2887{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2888{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2889{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2890{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2891{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2892{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2893{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2894{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2895{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2896{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2897
2898{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
2899{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2900{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2901{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
b9adb4a6
FB		 2902{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2903
eca8f888
BS		 2904{ "b", B(18,0,0), B_MASK, COM, { LI } },
2905{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2906{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2907{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
2908
2909{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2910
2911{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2912{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2913{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2914{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2915{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2916{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2917{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2918{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2919{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2920{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2921{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2922{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2923{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2924{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2925{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2926{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2927{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2928{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2929{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2930{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2931{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2932{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2933{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2934{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2935{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2936{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2937{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2938{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2939{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2940{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2941{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2942{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2943{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2944{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2945{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2946{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2947{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2948{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2949{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2950{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2951{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2952{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2953{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2954{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2955{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2956{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2957{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2958{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2959{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2960{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2961{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2962{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2963{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2964{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2965{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2966{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2967{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2968{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2969{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2970{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2971{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2972{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2973{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2974{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2975{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2976{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2977{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2978{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2979{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2980{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2981{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2982{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2983{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2984{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2985{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2986{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2987{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2988{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2989{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2990{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2991{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2992{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2993{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2994{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2995{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2996{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2997{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2998{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2999{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3000{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3001{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3002{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3003{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3004{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3005{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3006{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3007{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3008{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3009{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3010{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3011{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3012{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3013{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3014{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3015{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3016{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3017{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3018{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3019{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3020{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3021{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3022{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3023{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3024{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3025{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3026{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3027{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3028{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3029{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3030{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3031{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3032{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3033{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3034{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3035{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3036{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3037{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3038{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3039{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3040{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3041{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3042{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3043{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3044{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3045{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3046{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3047{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3048{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3049{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3050{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3051{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3052{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3053{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3054{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3055{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3056{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3057{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3058{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3059{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3060{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3061{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3062{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3063{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3064{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3065{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3066{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3067{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3068{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3069{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3070{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3071{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3072{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3073{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3074{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3075{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3076{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3077{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3078{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3079{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3080{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
3081{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3082{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3083{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3084{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3085{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3086{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
3087{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3088{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3089{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3090{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3091{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3092{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
3093{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3094{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3095{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3096{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3097{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3098{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
3099{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3100{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3101{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3102{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3103{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3104{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3105{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3106{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3107{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3108{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3109{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3110{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3111{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3112{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3113{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3114{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3115{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3116{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3117{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3118{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3119{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3120{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3121{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3122{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3123{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3124{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3125{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3126{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3127{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3128{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3129{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
3130{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
3131{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
3132{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
3133
3134{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
3135
3136{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
3137{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
3138{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
3139
3140{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
3141{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
b9adb4a6
FB		 3142
3143{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
3144
eca8f888
BS		 3145{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
3146
3147{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
3148{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
3149
3150{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3151{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
3152
3153{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
3154
3155{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
3156
ee8ae9e4 3157{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } },
eca8f888
BS		 3158
3159{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3160{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
3161
ee8ae9e4
BS		 3162{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } },
3163
eca8f888
BS		 3164{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
3165
ee8ae9e4
BS		 3166{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } },
3167
eca8f888
BS		 3168{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
3169{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
3170
ee8ae9e4
BS		 3171{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } },
3172{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } },
3173
eca8f888
BS		 3174{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
3175{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
3176{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3177{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3178{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3179{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3180{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3181{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3182{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3183{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3184{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3185{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3186{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3187{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3188{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3189{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3190{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3191{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3192{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3193{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3194{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3195{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3196{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3197{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3198{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3199{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3200{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3201{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3202{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3203{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3204{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3205{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3206{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3207{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3208{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3209{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3210{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3211{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3212{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3213{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3214{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3215{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3216{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3217{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3218{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3219{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3220{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3221{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3222{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3223{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3224{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3225{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3226{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3227{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3228{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3229{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3230{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3231{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3232{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3233{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3234{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3235{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3236{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3237{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3238{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3239{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3240{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3241{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3242{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3243{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3244{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3245{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3246{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3247{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3248{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3249{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3250{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3251{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3252{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3253{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3254{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3255{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3256{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3257{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3258{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3259{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3260{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3261{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3262{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3263{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3264{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3265{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3266{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3267{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3268{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3269{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3270{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3271{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3272{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3273{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3274{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3275{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3276{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3277{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3278{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3279{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3280{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3281{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3282{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3283{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3284{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3285{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3286{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3287{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3288{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3289{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3290{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3291{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3292{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3293{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3294{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3295{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3296{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3297{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3298{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3299{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3300{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3301{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3302{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3303{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3304{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3305{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3306{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3307{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3308{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3309{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3310{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3311{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3312{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3313{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3314{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3315{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3316{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3317{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3318{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3319{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3320{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3321{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3322{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3323{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
ee8ae9e4
BS		 3324{ "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } },
3325{ "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } },
eca8f888
BS		 3326
3327{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3328{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3329
3330{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3331{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3332
3333{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3334{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3335{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3336{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3337{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3338{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3339{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3340{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3341
3342{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3343{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3344
3345{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3346{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3347{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3348{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3349
3350{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3351{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3352{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3353{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3354{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3355{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3356
3357{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3358{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3359{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3360
3361{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3362{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3363
3364{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3365{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3366
3367{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3368{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3369
3370{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3371{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3372
3373{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3374{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3375
3376{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3377{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3378{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3379{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3380{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3381{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3382
3383{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3384{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3385
3386{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3387{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3388
3389{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3390{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3391
3392{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3393{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3394{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3395{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3396
3397{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3398{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3399
3400{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3401{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
b9adb4a6 3402{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
eca8f888
BS		 3403{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3404
3405{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3406{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3407{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3408{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3409{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3410{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3411{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3412{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3413{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3414{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3415{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3416{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3417{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3418{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3419{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3420{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3421{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3422{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3423{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3424{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3425{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3426{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3427{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3428{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3429{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3430{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3431{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3432{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3433{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3434{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3435{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3436
3437{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3438{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 3439{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
eca8f888
BS		 3440{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3441{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3442{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3443{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3444{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 3445{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
eca8f888
BS		 3446{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3447{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6
FB		 3448{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3449
eca8f888
BS		 3450{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3451{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
b9adb4a6 3452
eca8f888
BS		 3453{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3454{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3455{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3456{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3457{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3458{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3459{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3460{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6
FB		 3461
3462{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3463{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3464
eca8f888
BS		 3465{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3466{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3467{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3468{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3469
3470{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
ee8ae9e4 3471{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
eca8f888
BS		 3472{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3473
ee8ae9e4 3474{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
eca8f888
BS		 3475
3476{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3477
3478{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
3479{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
b9adb4a6 3480
eca8f888
BS		 3481{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3482{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 3483
eca8f888
BS		 3484{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3485{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3486{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3487{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
b9adb4a6 3488
eca8f888
BS		 3489{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3490{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3491{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3492{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
b9adb4a6 3493
eca8f888
BS		 3494{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3495{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
b9adb4a6 3496
eca8f888
BS		 3497{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3498{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
b9adb4a6 3499
eca8f888
BS		 3500{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3501{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 3502
eca8f888 3503{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
b9adb4a6 3504
eca8f888 3505{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
b9adb4a6 3506
eca8f888
BS		 3507{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3508{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3509{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3510{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
b9adb4a6
FB		 3511
3512{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3513{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3514{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3515{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3516{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3517{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3518{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3519{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3520
eca8f888 3521{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
b9adb4a6
FB		 3522
3523{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3524
eca8f888
BS		 3525{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3526{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3527
3528{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3529
3530{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3531
3532{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3533{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3534
3535{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3536{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3537
3538{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3539{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3540{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3541{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3542{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3543{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3544{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3545{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3546{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3547{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3548{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3549{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3550{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3551{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3552{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3553
3554{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3555{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
b9adb4a6
FB		 3556
3557{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3558{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3559
eca8f888
BS		 3560{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3561{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
b9adb4a6 3562
eca8f888
BS		 3563{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3564
3565{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3566
ee8ae9e4 3567{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
b9adb4a6 3568
ee8ae9e4
BS		 3569{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
3570{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } },
b9adb4a6 3571
eca8f888
BS		 3572{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3573
3574{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3575
3576{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3577
3578{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3579{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3580{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3581{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3582
3583{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3584{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3585{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3586{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3587
3588{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3589
3590{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3591
3592{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3593
3594{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
8d8dd793
RH		 3595{ "popcntw", X(31,378), XRB_MASK, POWER7, { RA, RS } },
3596{ "popcntd", X(31,506), XRB_MASK, POWER7, { RA, RS } },
3597
3598{ "cnttzw", XRC(31,538,0), XRB_MASK, POWER9, { RA, RS } },
3599{ "cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, { RA, RS } },
3600{ "cnttzd", XRC(31,570,0), XRB_MASK, POWER9, { RA, RS } },
3601{ "cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, { RA, RS } },
eca8f888
BS		 3602
3603{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3604{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3605{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3606{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3607
3608{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3609
3610{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3611
3612{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3613
3614{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3615
3616{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3617{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3618{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3619{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3620{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3621{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3622{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3623{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3624
3625{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3626{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3627{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3628{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3629{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3630{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3631{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3632{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3633
3634{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3635
3636{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3637{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
3638{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3639
3640{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3641
3642{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3643
3644{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3645
3646{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3647{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3648
3649{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3650
3651{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
b9adb4a6 3652
eca8f888
BS		 3653{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3654{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 3655
eca8f888
BS		 3656{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3657{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 3658
ee8ae9e4
BS		 3659{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
3660
eca8f888 3661{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
b9adb4a6 3662
eca8f888
BS		 3663{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3664{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
b9adb4a6 3665
ee8ae9e4 3666{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
b9adb4a6 3667
eca8f888 3668{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
b9adb4a6 3669
eca8f888
BS		 3670{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3671{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
b9adb4a6 3672
eca8f888
BS		 3673{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3674{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
b9adb4a6 3675
ee8ae9e4
BS		 3676{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
3677
eca8f888 3678{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
b9adb4a6 3679
eca8f888
BS		 3680{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3681{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3682{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3683{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3684{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3685{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3686{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3687{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
b9adb4a6 3688
eca8f888
BS		 3689{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3690{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3691{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3692{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3693{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3694{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3695{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3696{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
b9adb4a6 3697
eca8f888 3698{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
b9adb4a6 3699
eca8f888 3700{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
b9adb4a6 3701
eca8f888 3702{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
b9adb4a6 3703
eca8f888
BS		 3704{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3705{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 3706
eca8f888
BS		 3707{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3708{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 3709
eca8f888 3710{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
b9adb4a6 3711
eca8f888 3712{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
b9adb4a6 3713
eca8f888
BS		 3714{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3715{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3716{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3717{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3718{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3719{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3720{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3721{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
b9adb4a6 3722
eca8f888
BS		 3723{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3724{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3725{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3726{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
b9adb4a6 3727
eca8f888
BS		 3728{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3729{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3730{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3731{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3732{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3733{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3734{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3735{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
b9adb4a6 3736
4c5920af
SJS		 3737{ "addex", XO(31,170,0,0), XO_MASK, POWER9, { RT, RA, RB } },
3738
eca8f888
BS		 3739{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3740{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3741{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3742{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3743{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3744{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3745{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3746{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 3747
eca8f888
BS		 3748{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3749{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3750{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
b9adb4a6 3751
eca8f888 3752{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
b9adb4a6 3753
eca8f888
BS		 3754{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3755
3756{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3757{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3758
3759{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3760
3761{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3762
3763{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3764
3765{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3766{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3767{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3768{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3769
3770{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3771{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3772{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3773{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3774{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3775{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3776{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3777{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3778
3779{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3780
3781{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3782
3783{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3784{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3785
ee8ae9e4 3786{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
eca8f888
BS		 3787
3788{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3789
3790{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3791{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3792
3793{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3794
3795{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3796
3797{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3798{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
b9adb4a6
FB		 3799
3800{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3801
eca8f888
BS		 3802{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3803
3804{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3805{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3806
3807{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3808
3809{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3810{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3811{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3812{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3813{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3814{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3815{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3816{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3817{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3818{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3819{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3820{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3821{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3822{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3823{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3824{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3825{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3826{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3827{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3828{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3829{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3830{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3831{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3832{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3833{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3834{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3835{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3836{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3837{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3838{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3839{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3840{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3841{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3842{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3843{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3844
3845{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3846{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3847{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3848{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3849
3850{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3851
3852{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3853{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3854{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3855{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3856{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3857{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3858{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3859{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3860{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3861{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3862{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3863{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3864{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3865{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3866{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
ee8ae9e4 3867{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
eca8f888
BS		 3868{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3869{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3870{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3871{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3872{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3873{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3874{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3875{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3876{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3877{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3878{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3879{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3880{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3881{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3882{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3883{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3884{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3885{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3886{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3887{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3888{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3889{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3890{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3891{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3892{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3893{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3894{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3895{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3896{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3897{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3898{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3899{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3900{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3901{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
3902{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3903{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3904{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3905{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3906{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3907{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3908{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3909{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
3910{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3911{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3912{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3913{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3914{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3915{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3916{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3917{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3918{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3919{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3920{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3921{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3922{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3923{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3924{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3925{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3926{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3927{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3928{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3929{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3930{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3931{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3932{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3933{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3934{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3935{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3936{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3937{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3938{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3939{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3940{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3941{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3942{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3943{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3944{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3945{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3946{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3947{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3948{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3949{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3950{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3951{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3952{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3953{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3954{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3955{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3956{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3957{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3958{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3959{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3960{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3961{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3962{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3963{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3964{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3965{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3966{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3967{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3968{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3969{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3970{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3971{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3972{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3973{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3974{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3975{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3976{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3977{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3978{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3979{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3980{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3981{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3982{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3983{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3984{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3985{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3986{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3987{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3988{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3989{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3990{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3991{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3992{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3993{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3994{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3995{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3996{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3997{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3998{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3999{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
4000{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
4001{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
4002{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
4003{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
4004{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
4005{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
4006{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
4007{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
4008{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
4009{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
4010{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
4011{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
4012{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
4013{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
4014{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
4015{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
4016{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
4017{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
4018{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
4019{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
4020{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
4021{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
4022{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
4023{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
4024{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
4025{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
4026{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
4027{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
4028{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
4029{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
4030{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
4031{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
4032{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
4033{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
4034{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
4035{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
4036{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
4037{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
4038{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
4039{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
4040
4041{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
4042
4043{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4044{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4045
4046{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
4047
4048{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
4049
4050{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4051{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4052
4053{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
4054
4055{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
4056{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
4057{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
4058{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
4059
4060{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
4061{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
4062{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
4063{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
b9adb4a6
FB		 4064
4065{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
4066
eca8f888
BS		 4067{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
4068
4069{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
4070
4071{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
4072
4073{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
4074
4075{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
b9adb4a6 4076
eca8f888
BS		 4077{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4078{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
b9adb4a6 4079
eca8f888
BS		 4080{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4081{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
b9adb4a6 4082
eca8f888
BS		 4083{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
4084
4085{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
4086
4087{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
b9adb4a6 4088
ee8ae9e4
BS		 4089{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
4090
b9adb4a6
FB		 4091{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4092
ee8ae9e4
BS		 4093{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4094
b9adb4a6
FB		 4095{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4096
4097{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4098
ee8ae9e4
BS		 4099{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
4100
b9adb4a6
FB		 4101{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4102
eca8f888
BS		 4103{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
4104{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
b9adb4a6 4105
eca8f888
BS		 4106{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
4107{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
b9adb4a6 4108
eca8f888 4109{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
b9adb4a6 4110
eca8f888 4111{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
b9adb4a6 4112
eca8f888 4113{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
b9adb4a6 4114
eca8f888
BS		 4115{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
4116
4117{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4118
ee8ae9e4
BS		 4119{ "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }},
4120{ "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }},
4121{ "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }},
4122{ "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }},
4123{ "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }},
4124{ "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }},
4125{ "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }},
eca8f888
BS		 4126{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
4127{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4128{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
4129{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
4130
4131{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
4132{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
4133{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
4134{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
4135{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
4136{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
4137{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
4138{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
4139{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
4140{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
4141{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
4142{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
4143{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
4144{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
4145{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
4146{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
4147{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
4148{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
4149{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
4150{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
4151{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
4152{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
4153{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
4154{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
4155{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
4156{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
4157{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
4158{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
4159{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
4160{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
4161{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
4162{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
4163{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
4164{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
4165{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
4166
4167{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4168{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4169
4170{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4171{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4172{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4173{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4174
4175{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4176{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
b9adb4a6
FB		 4177
4178{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4179{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4180{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4181{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4182
eca8f888
BS		 4183{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
4184{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
4185{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
4186{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
4187{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
4188{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
4189{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
4190{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
4191{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
4192{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
4193{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
4194{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
4195{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
4196{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
ee8ae9e4 4197{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
eca8f888
BS		 4198{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
4199{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
4200{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
4201{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
4202{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
4203{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
4204{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
4205{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
4206{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
4207{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
4208{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
4209{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
4210{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
4211{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
4212{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
4213{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
4214{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
4215{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
4216{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
4217{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
4218{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
4219{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
4220{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
4221{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
4222{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
4223{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
4224{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
4225{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
4226{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
4227{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
4228{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
4229{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
4230{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
4231{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
4232{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
4233{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
4234{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
4235{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4236{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4237{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4238{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4239{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
4240{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
4241{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
4242{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
4243{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
4244{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
4245{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4246{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
4247{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
4248{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
4249{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
4250{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
4251{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
4252{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
4253{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
4254{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
4255{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
4256{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
4257{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
4258{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
4259{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
4260{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
4261{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
4262{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
4263{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
4264{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4265{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
4266{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4267{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4268{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4269{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4270{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4271{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4272{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4273{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4274{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4275{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4276{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4277{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4278{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4279{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4280{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4281{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4282{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4283{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4284{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4285{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4286{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4287{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
4288{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4289{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4290{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4291{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4292{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4293{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4294{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4295{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4296{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4297{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4298{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4299{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4300{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4301{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4302{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4303{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4304{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4305{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4306{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4307{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4308{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4309{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4310{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4311{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4312{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4313{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4314{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4315{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4316{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4317{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4318{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4319{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4320{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4321{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4322{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4323{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4324{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4325{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4326{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4327{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4328{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4329{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4330{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4331{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4332{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4333{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4334{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4335{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
b9adb4a6
FB		 4336
4337{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4338
eca8f888
BS		 4339{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4340{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
b9adb4a6 4341
eca8f888 4342{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
b9adb4a6 4343
eca8f888
BS		 4344{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4345
4346{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4347
4348{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4349
4350{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4351{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4352{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4353{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4354{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4355{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4356
4357{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4358{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4359{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4360{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4361
4362{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4363{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
b9adb4a6
FB		 4364
4365{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4366{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4367{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4368{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4369
eca8f888
BS		 4370{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4371
4372{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
b9adb4a6
FB		 4373
4374{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4375
eca8f888
BS		 4376{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4377
4378{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
b9adb4a6 4379
eca8f888
BS		 4380{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4381{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
b9adb4a6 4382
eca8f888 4383{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
b9adb4a6 4384
ee8ae9e4
BS		 4385{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4386
eca8f888
BS		 4387{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4388{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 4389
eca8f888
BS		 4390{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4391{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 4392
eca8f888 4393{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
b9adb4a6 4394
eca8f888
BS		 4395{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4396{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4397{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4398{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
b9adb4a6 4399
eca8f888
BS		 4400{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4401{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4402
eca8f888
BS		 4403{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4404{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4405
4406{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4407{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4408
4409{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4410
4411{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4412
4413{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
b9adb4a6
FB		 4414
4415{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4416
eca8f888
BS		 4417{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4418
4419{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4420
4421{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4422
4423{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4424{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4425
4426{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4427{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4428{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4429{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4430{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4431
4432{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4433
4434{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4435
ee8ae9e4
BS		 4436{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
4437
eca8f888
BS		 4438{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4439
4440{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4441
4442{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4443
4444{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4445
4446{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4447
ee8ae9e4
BS		 4448{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4449
eca8f888
BS		 4450{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4451{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4452
4453{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4454{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4455
4456{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
b9adb4a6 4457
eca8f888
BS		 4458{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4459{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4460
eca8f888
BS		 4461{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4462{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4463
eca8f888 4464{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
b9adb4a6 4465
eca8f888 4466{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
b9adb4a6 4467
eca8f888 4468{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
b9adb4a6 4469
eca8f888
BS		 4470{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4471{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
b9adb4a6 4472
eca8f888 4473{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
b9adb4a6 4474
eca8f888
BS		 4475{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4476{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
b9adb4a6 4477
eca8f888 4478{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
b9adb4a6 4479
eca8f888
BS		 4480{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4481{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4482
eca8f888
BS		 4483{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4484{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4485
eca8f888 4486{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
b9adb4a6 4487
ee8ae9e4
BS		 4488{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
4489
eca8f888 4490{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
b9adb4a6 4491
eca8f888 4492{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
b9adb4a6 4493
eca8f888
BS		 4494{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4495{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
b9adb4a6 4496
eca8f888 4497{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
b9adb4a6 4498
eca8f888 4499{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
b9adb4a6 4500
eca8f888
BS		 4501{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4502{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
b9adb4a6 4503
ee8ae9e4
BS		 4504{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4505
eca8f888 4506{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
b9adb4a6 4507
eca8f888
BS		 4508{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4509{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4510{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4511{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
b9adb4a6 4512
eca8f888
BS		 4513{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4514{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
b9adb4a6 4515
eca8f888 4516{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
b9adb4a6 4517
eca8f888
BS		 4518{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4519{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
b9adb4a6 4520
eca8f888 4521{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
b9adb4a6 4522
ee8ae9e4
BS		 4523{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4524
eca8f888
BS		 4525{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4526{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
b9adb4a6 4527
eca8f888
BS		 4528{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4529{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4530{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4531{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
b9adb4a6 4532
eca8f888
BS		 4533{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4534
ee8ae9e4
BS		 4535{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4536
eca8f888 4537{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
b9adb4a6
FB		 4538{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4539
ee8ae9e4
BS		 4540{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4541
4542{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4543
eca8f888
BS		 4544{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4545{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
ee8ae9e4
BS		 4546{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } },
4547{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } },
eca8f888
BS		 4548
4549{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4550
ee8ae9e4
BS		 4551{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4552
eca8f888
BS		 4553{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4554
4555{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4556{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4557
eca8f888
BS		 4558{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4559{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
b9adb4a6 4560
eca8f888
BS		 4561{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4562{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4563{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4564{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
b9adb4a6 4565
eca8f888 4566{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
b9adb4a6 4567
eca8f888
BS		 4568{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4569
4570{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4571{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4572{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4573
ee8ae9e4
BS		 4574{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4575
eca8f888
BS		 4576{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4577{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
b9adb4a6
FB		 4578
4579{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4580{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4581
eca8f888
BS		 4582{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4583
4584{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4585
4586{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4587{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4588{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4589{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
b9adb4a6 4590
ee8ae9e4
BS		 4591{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4592
b9adb4a6
FB		 4593{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4594
eca8f888
BS		 4595{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4596
4597{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4598{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4599
4600{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
b9adb4a6 4601
eca8f888
BS		 4602{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4603{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
b9adb4a6 4604
eca8f888
BS		 4605{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4606
ee8ae9e4
BS		 4607{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4608
eca8f888 4609{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
b9adb4a6
FB		 4610{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4611{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4612
eca8f888
BS		 4613{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4614
4615{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4616{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4617{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4618{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4619{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4620{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4621{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4622{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4623{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4624{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4625{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4626{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4627
ee8ae9e4
BS		 4628/* New load/store left/right index vector instructions that are in the Cell only. */
4629{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4630{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4631{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4632{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4633{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4634{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4635{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4636{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4637
eca8f888
BS		 4638{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4639{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
b9adb4a6 4640
eca8f888
BS		 4641{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4642{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
b9adb4a6 4643
eca8f888 4644{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
b9adb4a6 4645
eca8f888 4646{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
b9adb4a6 4647
eca8f888
BS		 4648{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4649{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
b9adb4a6 4650
eca8f888
BS		 4651{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4652{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
b9adb4a6 4653
eca8f888 4654{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
b9adb4a6 4655
eca8f888 4656{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
b9adb4a6 4657
eca8f888 4658{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
b9adb4a6 4659
eca8f888 4660{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
b9adb4a6 4661
eca8f888 4662{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
b9adb4a6 4663
eca8f888 4664{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
b9adb4a6 4665
eca8f888 4666{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
b9adb4a6 4667
eca8f888 4668{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
b9adb4a6 4669
eca8f888
BS		 4670{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4671{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
b9adb4a6 4672
eca8f888
BS		 4673{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4674{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
b9adb4a6 4675
eca8f888 4676{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
b9adb4a6 4677
eca8f888 4678{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
b9adb4a6 4679
eca8f888 4680{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
b9adb4a6 4681
eca8f888 4682{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
b9adb4a6 4683
eca8f888 4684{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
b9adb4a6 4685
eca8f888 4686{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
b9adb4a6 4687
eca8f888 4688{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
b9adb4a6 4689
eca8f888 4690{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
b9adb4a6 4691
eca8f888 4692{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
b9adb4a6 4693
eca8f888 4694{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
b9adb4a6 4695
eca8f888 4696{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
b9adb4a6 4697
ee8ae9e4
BS		 4698{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4699
eca8f888
BS		 4700{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4701{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4702{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4703{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4704{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4705{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4706{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4707{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4708{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4709{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4710{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4711{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4712{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4713{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
b9adb4a6 4714
eca8f888
BS		 4715{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4716
4717{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4718
4719{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
b9adb4a6 4720
ee8ae9e4
BS		 4721{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4722{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4723
4724{ "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4725{ "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4726
b9adb4a6
FB		 4727{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4728{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4729
4730{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4731{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4732
4733{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4734{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4735
4736{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4737{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4738
ee8ae9e4
BS		 4739{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4740{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
b9adb4a6
FB		 4741
4742{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4743{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4744
ee8ae9e4
BS		 4745{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4746{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
eca8f888 4747
b9adb4a6
FB		 4748{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4749{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4750
4751{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4752{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4753
4754{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4755{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4756
4757{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4758{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4759
ee8ae9e4
BS		 4760{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4761{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4762
4763{ "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4764{ "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4765
4766{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4767{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4768
4769{ "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4770{ "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4771
4772{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4773{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4774
4775{ "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4776{ "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4777
4778{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
4779
4780{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
4781{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4782{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4783
4784{ "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4785{ "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4786
4787{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
4788{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
4789
4790{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
4791{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
4792
4793{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4794{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4795
4796{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
4797{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
4798
4799{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4800{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4801
4802{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4803{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4804
4805{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
4806
4807{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
4808
4809{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
4810{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
4811
4812{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
4813{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
4814
4815{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4816{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4817
4818{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4819{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4820
b9adb4a6
FB		 4821{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4822
4823{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4824
ee8ae9e4
BS		 4825{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
4826
eca8f888
BS		 4827{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4828{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4829{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4830{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4831{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4832{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4833{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4834{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4835{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4836{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4837{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4838{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
b9adb4a6 4839
eca8f888 4840{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
b9adb4a6 4841
eca8f888 4842{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
b9adb4a6 4843
eca8f888 4844{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
b9adb4a6 4845
eca8f888
BS		 4846{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4847
ee8ae9e4
BS		 4848{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4849{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4850
4851{ "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4852{ "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4853
4854{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4855{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4856
eca8f888
BS		 4857{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4858{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4859
4860{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
b9adb4a6 4861{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
eca8f888 4862{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
b9adb4a6
FB		 4863{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4864
eca8f888 4865{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
b9adb4a6 4866{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
eca8f888 4867{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
b9adb4a6
FB		 4868{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4869
eca8f888
BS		 4870{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4871{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4872{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4873{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
b9adb4a6 4874
eca8f888
BS		 4875{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4876{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4877{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4878{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
b9adb4a6 4879
eca8f888
BS		 4880{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4881{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4882{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4883{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
b9adb4a6 4884
eca8f888
BS		 4885{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4886{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
b9adb4a6
FB		 4887
4888{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4889{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4890
ee8ae9e4
BS		 4891{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4892{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
eca8f888
BS		 4893
4894{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4895{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4896{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4897{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
b9adb4a6 4898
ee8ae9e4
BS		 4899{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4900{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
b9adb4a6 4901
eca8f888
BS		 4902{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4903{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4904{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4905{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
b9adb4a6 4906
eca8f888
BS		 4907{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4908{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4909{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4910{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
b9adb4a6 4911
eca8f888
BS		 4912{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4913{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4914{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4915{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
b9adb4a6 4916
eca8f888
BS		 4917{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4918{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4919{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4920{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
b9adb4a6 4921
eca8f888 4922{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
b9adb4a6 4923
ee8ae9e4
BS		 4924{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4925{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4926
4927{ "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4928{ "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4929
eca8f888
BS		 4930{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4931{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
b9adb4a6 4932
eca8f888
BS		 4933{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4934{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
b9adb4a6 4935
eca8f888 4936{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
b9adb4a6 4937
ee8ae9e4
BS		 4938{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4939{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4940
4941{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4942{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4943
eca8f888
BS		 4944{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4945{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
b9adb4a6 4946
eca8f888
BS		 4947{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4948{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
b9adb4a6 4949
ee8ae9e4
BS		 4950{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4951{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4952
4953{ "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4954{ "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4955
4956{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
4957
4958{ "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
4959{ "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
b9adb4a6 4960
eca8f888
BS		 4961{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4962{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
b9adb4a6 4963
ee8ae9e4
BS		 4964{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
4965{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4966{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4967
4968{ "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4969{ "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4970
4971{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
4972{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
4973
eca8f888
BS		 4974{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4975{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
b9adb4a6 4976
ee8ae9e4
BS		 4977{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
4978{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
4979
4980{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4981{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4982
4983{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
4984{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
4985
eca8f888
BS		 4986{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
4987{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
4988{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
4989{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
4990{ "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
4991{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
4992{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
4993{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
b9adb4a6 4994
ee8ae9e4
BS		 4995{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4996{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4997
4998{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4999{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
5000
eca8f888
BS		 5001{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
5002{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
b9adb4a6 5003
ee8ae9e4
BS		 5004{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
5005
5006{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
5007
5008{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
5009{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
5010
5011{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
5012{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
5013
5014{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
5015{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
b9adb4a6 5016
eca8f888
BS		 5017{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
5018{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
b9adb4a6 5019
eca8f888
BS		 5020{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
5021{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
5022
ee8ae9e4
BS		 5023{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
5024{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
5025
eca8f888
BS		 5026{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
5027{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
b9adb4a6 5028
ee8ae9e4
BS		 5029{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
5030{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
5031
b9adb4a6
FB		 5032};
5033
5034const int powerpc_num_opcodes =
5035 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
5036\f
5037/* The macro table. This is only used by the assembler. */
5038
eca8f888
BS		 5039/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
5040 when x=0; 32-x when x is between 1 and 31; are negative if x is
5041 negative; and are 32 or more otherwise. This is what you want
5042 when, for instance, you are emulating a right shift by a
5043 rotate-left-and-mask, because the underlying instructions support
5044 shifts of size 0 but not shifts of size 32. By comparison, when
5045 extracting x bits from some word you want to use just 32-x, because
5046 the underlying instructions don't support extracting 0 bits but do
5047 support extracting the whole word (32 bits in this case). */
b9adb4a6 5048
eca8f888
BS		 5049const struct powerpc_macro powerpc_macros[] = {
5050{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
5051{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
5052{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
5053{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
5054{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
5055{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
5056{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
5057{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
5058{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
5059{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
5060{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
5061{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
5062{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
5063{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
5064{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
5065{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
5066
5067{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
5068{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
5069{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
5070{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
5071{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
5072{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5073{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
5074{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5075{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
5076{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
5077{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
5078{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
5079{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
5080{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
5081{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5082{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5083{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5084{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5085{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
5086{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
5087{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
5088{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
b9adb4a6
FB		 5089};
5090
5091const int powerpc_num_macros =
5092 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
5093
ee8ae9e4 5094
eca8f888
BS		 5095/* This file provides several disassembler functions, all of which use
5096 the disassembler interface defined in dis-asm.h. Several functions
5097 are provided because this file handles disassembly for the PowerPC
5098 in both big and little endian mode and also for the POWER (RS/6000)
5099 chip. */
5100
5101static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int);
5102
5103/* Determine which set of machines to disassemble for. PPC403/601 or
5104 BookE. For convenience, also disassemble instructions supported
5105 by the AltiVec vector unit. */
5106
43ef9eb2 5107static int
eca8f888
BS		 5108powerpc_dialect (struct disassemble_info *info)
5109{
5110 int dialect = PPC_OPCODE_PPC;
5111
5112 if (BFD_DEFAULT_TARGET_SIZE == 64)
5113 dialect |= PPC_OPCODE_64;
5114
5115 if (info->disassembler_options
5116 && strstr (info->disassembler_options, "booke") != NULL)
5117 dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
5118 else if ((info->mach == bfd_mach_ppc_e500)
5119 || (info->disassembler_options
5120 && strstr (info->disassembler_options, "e500") != NULL))
5121 dialect |= (PPC_OPCODE_BOOKE
5122 | PPC_OPCODE_SPE | PPC_OPCODE_ISEL
5123 | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
5124 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
5125 | PPC_OPCODE_RFMCI);
5126 else if (info->disassembler_options
5127 && strstr (info->disassembler_options, "efs") != NULL)
5128 dialect |= PPC_OPCODE_EFS;
5129 else if (info->disassembler_options
5130 && strstr (info->disassembler_options, "e300") != NULL)
5131 dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON;
ee8ae9e4
BS		 5132 else if (info->disassembler_options
5133 && strstr (info->disassembler_options, "440") != NULL)
5134 dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32
5135 | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI;
eca8f888
BS		 5136 else
5137 dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
5138 | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC);
5139
5140 if (info->disassembler_options
5141 && strstr (info->disassembler_options, "power4") != NULL)
5142 dialect |= PPC_OPCODE_POWER4;
5143
5144 if (info->disassembler_options
5145 && strstr (info->disassembler_options, "power5") != NULL)
5146 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
5147
ee8ae9e4
BS		 5148 if (info->disassembler_options
5149 && strstr (info->disassembler_options, "cell") != NULL)
5150 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;
5151
5152 if (info->disassembler_options
5153 && strstr (info->disassembler_options, "power6") != NULL)
5154 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
5155
eca8f888
BS		 5156 if (info->disassembler_options
5157 && strstr (info->disassembler_options, "any") != NULL)
5158 dialect |= PPC_OPCODE_ANY;
5159
5160 if (info->disassembler_options)
5161 {
5162 if (strstr (info->disassembler_options, "32") != NULL)
5163 dialect &= ~PPC_OPCODE_64;
5164 else if (strstr (info->disassembler_options, "64") != NULL)
5165 dialect |= PPC_OPCODE_64;
a2458627 5166 }
eca8f888
BS		 5167
5168 info->private_data = (char *) 0 + dialect;
5169 return dialect;
5170}
5171
5cbdb3a3 5172/* QEMU default */
eca8f888
BS		 5173int
5174print_insn_ppc (bfd_vma memaddr, struct disassemble_info *info)
5175{
5176 int dialect = (char *) info->private_data - (char *) 0;
95f5b6e3
AB		 5177 return print_insn_powerpc (memaddr, info, info->endian == BFD_ENDIAN_BIG,
5178 dialect);
eca8f888
BS		 5179}
5180
5181/* Print a big endian PowerPC instruction. */
5182
5183int
5184print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
5185{
5186 int dialect = (char *) info->private_data - (char *) 0;
5187 return print_insn_powerpc (memaddr, info, 1, dialect);
5188}
5189
5190/* Print a little endian PowerPC instruction. */
5191
5192int
5193print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
5194{
5195 int dialect = (char *) info->private_data - (char *) 0;
5196 return print_insn_powerpc (memaddr, info, 0, dialect);
5197}
5198
5199/* Print a POWER (RS/6000) instruction. */
5200
5201int
5202print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
5203{
5204 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
b9adb4a6
FB		 5205}
5206
ee8ae9e4
BS		 5207/* Extract the operand value from the PowerPC or POWER instruction. */
5208
5209static long
5210operand_value_powerpc (const struct powerpc_operand *operand,
5211 unsigned long insn, int dialect)
5212{
5213 long value;
5214 int invalid;
5215 /* Extract the value from the instruction. */
5216 if (operand->extract)
5217 value = (*operand->extract) (insn, dialect, &invalid);
5218 else
5219 {
5220 value = (insn >> operand->shift) & operand->bitm;
5221 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
5222 {
5223 /* BITM is always some number of zeros followed by some
5224 number of ones, followed by some numer of zeros. */
5225 unsigned long top = operand->bitm;
5226 /* top & -top gives the rightmost 1 bit, so this
5227 fills in any trailing zeros. */
5228 top |= (top & -top) - 1;
5229 top &= ~(top >> 1);
5230 value = (value ^ top) - top;
5231 }
5232 }
5233
5234 return value;
5235}
5236
5237/* Determine whether the optional operand(s) should be printed. */
5238
5239static int
5240skip_optional_operands (const unsigned char *opindex,
5241 unsigned long insn, int dialect)
5242{
5243 const struct powerpc_operand *operand;
5244
5245 for (; *opindex != 0; opindex++)
5246 {
5247 operand = &powerpc_operands[*opindex];
5248 if ((operand->flags & PPC_OPERAND_NEXT) != 0
5249 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
5250 && operand_value_powerpc (operand, insn, dialect) != 0))
5251 return 0;
5252 }
5253
5254 return 1;
5255}
5256
b9adb4a6
FB		 5257/* Print a PowerPC or POWER instruction. */
5258
7c08dbf3 5259static int
eca8f888
BS		 5260print_insn_powerpc (bfd_vma memaddr,
5261 struct disassemble_info *info,
5262 int bigendian,
b9adb4a6
FB		 5263 int dialect)
5264{
eca8f888
BS		 5265 bfd_byte buffer[4];
5266 int status;
5267 unsigned long insn;
b9adb4a6
FB		 5268 const struct powerpc_opcode *opcode;
5269 const struct powerpc_opcode *opcode_end;
eca8f888
BS		 5270 unsigned long op;
5271
5272 if (dialect == 0)
5273 dialect = powerpc_dialect (info);
5274
5275 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
5276 if (status != 0)
5277 {
5278 (*info->memory_error_func) (status, memaddr, info);
5279 return -1;
5280 }
5281
5282 if (bigendian)
5283 insn = bfd_getb32 (buffer);
5284 else
5285 insn = bfd_getl32 (buffer);
b9adb4a6
FB		 5286
5287 /* Get the major opcode of the instruction. */
5288 op = PPC_OP (insn);
5289
5290 /* Find the first match in the opcode table. We could speed this up
5291 a bit by doing a binary search on the major opcode. */
5292 opcode_end = powerpc_opcodes + powerpc_num_opcodes;
eca8f888 5293 again:
b9adb4a6
FB		 5294 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
5295 {
eca8f888 5296 unsigned long table_op;
b9adb4a6
FB		 5297 const unsigned char *opindex;
5298 const struct powerpc_operand *operand;
5299 int invalid;
5300 int need_comma;
5301 int need_paren;
ee8ae9e4 5302 int skip_optional;
b9adb4a6
FB		 5303
5304 table_op = PPC_OP (opcode->opcode);
5305 if (op < table_op)
eca8f888 5306 break;
b9adb4a6 5307 if (op > table_op)
eca8f888 5308 continue;
b9adb4a6
FB		 5309
5310 if ((insn & opcode->mask) != opcode->opcode
5311 || (opcode->flags & dialect) == 0)
eca8f888 5312 continue;
b9adb4a6
FB		 5313
5314 /* Make two passes over the operands. First see if any of them
eca8f888
BS		 5315 have extraction functions, and, if they do, make sure the
5316 instruction is valid. */
b9adb4a6
FB		 5317 invalid = 0;
5318 for (opindex = opcode->operands; *opindex != 0; opindex++)
eca8f888
BS		 5319 {
5320 operand = powerpc_operands + *opindex;
5321 if (operand->extract)
5322 (*operand->extract) (insn, dialect, &invalid);
5323 }
b9adb4a6 5324 if (invalid)
eca8f888 5325 continue;
b9adb4a6
FB		 5326
5327 /* The instruction is valid. */
b9adb4a6 5328 if (opcode->operands[0] != 0)
eca8f888
BS		 5329 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
5330 else
5331 (*info->fprintf_func) (info->stream, "%s", opcode->name);
b9adb4a6
FB		 5332
5333 /* Now extract and print the operands. */
5334 need_comma = 0;
5335 need_paren = 0;
ee8ae9e4 5336 skip_optional = -1;
b9adb4a6 5337 for (opindex = opcode->operands; *opindex != 0; opindex++)
eca8f888
BS		 5338 {
5339 long value;
5340
5341 operand = powerpc_operands + *opindex;
5342
5343 /* Operands that are marked FAKE are simply ignored. We
5344 already made sure that the extract function considered
5345 the instruction to be valid. */
5346 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
5347 continue;
5348
ee8ae9e4
BS		 5349 /* If all of the optional operands have the value zero,
5350 then don't print any of them. */
5351 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
eca8f888 5352 {
ee8ae9e4
BS		 5353 if (skip_optional < 0)
5354 skip_optional = skip_optional_operands (opindex, insn,
5355 dialect);
5356 if (skip_optional)
5357 continue;
eca8f888
BS		 5358 }
5359
ee8ae9e4 5360 value = operand_value_powerpc (operand, insn, dialect);
eca8f888
BS		 5361
5362 if (need_comma)
5363 {
5364 (*info->fprintf_func) (info->stream, ",");
5365 need_comma = 0;
5366 }
5367
5368 /* Print the operand as directed by the flags. */
5369 if ((operand->flags & PPC_OPERAND_GPR) != 0
5370 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
5371 (*info->fprintf_func) (info->stream, "r%ld", value);
5372 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
5373 (*info->fprintf_func) (info->stream, "f%ld", value);
5374 else if ((operand->flags & PPC_OPERAND_VR) != 0)
5375 (*info->fprintf_func) (info->stream, "v%ld", value);
5376 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
5377 (*info->print_address_func) (memaddr + value, info);
5378 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
5379 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
5380 else if ((operand->flags & PPC_OPERAND_CR) == 0
5381 || (dialect & PPC_OPCODE_PPC) == 0)
5382 (*info->fprintf_func) (info->stream, "%ld", value);
5383 else
5384 {
ee8ae9e4 5385 if (operand->bitm == 7)
eca8f888
BS		 5386 (*info->fprintf_func) (info->stream, "cr%ld", value);
5387 else
b9adb4a6 5388 {
eca8f888
BS		 5389 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
5390 int cr;
5391 int cc;
5392
5393 cr = value >> 2;
5394 if (cr != 0)
5395 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
5396 cc = value & 3;
5397 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
5398 }
b9adb4a6
FB		 5399 }
5400
5401 if (need_paren)
5402 {
eca8f888 5403 (*info->fprintf_func) (info->stream, ")");
b9adb4a6
FB		 5404 need_paren = 0;
5405 }
5406
5407 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
5408 need_comma = 1;
5409 else
5410 {
eca8f888 5411 (*info->fprintf_func) (info->stream, "(");
b9adb4a6
FB		 5412 need_paren = 1;
5413 }
5414 }
5415
5416 /* We have found and printed an instruction; return. */
5417 return 4;
5418 }
5419
eca8f888
BS		 5420 if ((dialect & PPC_OPCODE_ANY) != 0)
5421 {
5422 dialect = ~PPC_OPCODE_ANY;
5423 goto again;
5424 }
5425
b9adb4a6 5426 /* We could not find a match. */
eca8f888 5427 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
b9adb4a6
FB		 5428
5429 return 4;
5430}
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