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Commit | Line | Data |
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54936004 | 1 | /* |
fd6ce8f6 | 2 | * virtual page mapping and translated block handling |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
67b915a5 | 20 | #include "config.h" |
d5a8f07c | 21 | #ifdef _WIN32 |
4fddf62a | 22 | #define WIN32_LEAN_AND_MEAN |
d5a8f07c FB |
23 | #include <windows.h> |
24 | #else | |
a98d49b1 | 25 | #include <sys/types.h> |
d5a8f07c FB |
26 | #include <sys/mman.h> |
27 | #endif | |
54936004 FB |
28 | #include <stdlib.h> |
29 | #include <stdio.h> | |
30 | #include <stdarg.h> | |
31 | #include <string.h> | |
32 | #include <errno.h> | |
33 | #include <unistd.h> | |
34 | #include <inttypes.h> | |
35 | ||
6180a181 FB |
36 | #include "cpu.h" |
37 | #include "exec-all.h" | |
ca10f867 | 38 | #include "qemu-common.h" |
b67d9a52 | 39 | #include "tcg.h" |
b3c7724c | 40 | #include "hw/hw.h" |
74576198 | 41 | #include "osdep.h" |
7ba1e619 | 42 | #include "kvm.h" |
53a5960a PB |
43 | #if defined(CONFIG_USER_ONLY) |
44 | #include <qemu.h> | |
45 | #endif | |
54936004 | 46 | |
fd6ce8f6 | 47 | //#define DEBUG_TB_INVALIDATE |
66e85a21 | 48 | //#define DEBUG_FLUSH |
9fa3e853 | 49 | //#define DEBUG_TLB |
67d3b957 | 50 | //#define DEBUG_UNASSIGNED |
fd6ce8f6 FB |
51 | |
52 | /* make various TB consistency checks */ | |
5fafdf24 TS |
53 | //#define DEBUG_TB_CHECK |
54 | //#define DEBUG_TLB_CHECK | |
fd6ce8f6 | 55 | |
1196be37 | 56 | //#define DEBUG_IOPORT |
db7b5426 | 57 | //#define DEBUG_SUBPAGE |
1196be37 | 58 | |
99773bd4 PB |
59 | #if !defined(CONFIG_USER_ONLY) |
60 | /* TB consistency checks only implemented for usermode emulation. */ | |
61 | #undef DEBUG_TB_CHECK | |
62 | #endif | |
63 | ||
9fa3e853 FB |
64 | #define SMC_BITMAP_USE_THRESHOLD 10 |
65 | ||
66 | #define MMAP_AREA_START 0x00000000 | |
67 | #define MMAP_AREA_END 0xa8000000 | |
fd6ce8f6 | 68 | |
108c49b8 FB |
69 | #if defined(TARGET_SPARC64) |
70 | #define TARGET_PHYS_ADDR_SPACE_BITS 41 | |
5dcb6b91 BS |
71 | #elif defined(TARGET_SPARC) |
72 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 | |
bedb69ea JM |
73 | #elif defined(TARGET_ALPHA) |
74 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 | |
75 | #define TARGET_VIRT_ADDR_SPACE_BITS 42 | |
108c49b8 FB |
76 | #elif defined(TARGET_PPC64) |
77 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 | |
00f82b8a AJ |
78 | #elif defined(TARGET_X86_64) && !defined(USE_KQEMU) |
79 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 | |
80 | #elif defined(TARGET_I386) && !defined(USE_KQEMU) | |
81 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 | |
108c49b8 FB |
82 | #else |
83 | /* Note: for compatibility with kqemu, we use 32 bits for x86_64 */ | |
84 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
85 | #endif | |
86 | ||
bdaf78e0 | 87 | static TranslationBlock *tbs; |
26a5f13b | 88 | int code_gen_max_blocks; |
9fa3e853 | 89 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bdaf78e0 | 90 | static int nb_tbs; |
eb51d102 FB |
91 | /* any access to the tbs or the page table must use this lock */ |
92 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; | |
fd6ce8f6 | 93 | |
141ac468 BS |
94 | #if defined(__arm__) || defined(__sparc_v9__) |
95 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 | |
96 | have limited branch ranges (possibly also PPC) so place it in a | |
d03d860b BS |
97 | section close to code segment. */ |
98 | #define code_gen_section \ | |
99 | __attribute__((__section__(".gen_code"))) \ | |
100 | __attribute__((aligned (32))) | |
101 | #else | |
102 | #define code_gen_section \ | |
103 | __attribute__((aligned (32))) | |
104 | #endif | |
105 | ||
106 | uint8_t code_gen_prologue[1024] code_gen_section; | |
bdaf78e0 BS |
107 | static uint8_t *code_gen_buffer; |
108 | static unsigned long code_gen_buffer_size; | |
26a5f13b | 109 | /* threshold to flush the translated code buffer */ |
bdaf78e0 | 110 | static unsigned long code_gen_buffer_max_size; |
fd6ce8f6 FB |
111 | uint8_t *code_gen_ptr; |
112 | ||
e2eef170 | 113 | #if !defined(CONFIG_USER_ONLY) |
00f82b8a | 114 | ram_addr_t phys_ram_size; |
9fa3e853 FB |
115 | int phys_ram_fd; |
116 | uint8_t *phys_ram_base; | |
1ccde1cb | 117 | uint8_t *phys_ram_dirty; |
74576198 | 118 | static int in_migration; |
e9a1ab19 | 119 | static ram_addr_t phys_ram_alloc_offset = 0; |
e2eef170 | 120 | #endif |
9fa3e853 | 121 | |
6a00d601 FB |
122 | CPUState *first_cpu; |
123 | /* current CPU in the current thread. It is only valid inside | |
124 | cpu_exec() */ | |
5fafdf24 | 125 | CPUState *cpu_single_env; |
2e70f6ef | 126 | /* 0 = Do not count executed instructions. |
bf20dc07 | 127 | 1 = Precise instruction counting. |
2e70f6ef PB |
128 | 2 = Adaptive rate instruction counting. */ |
129 | int use_icount = 0; | |
130 | /* Current instruction counter. While executing translated code this may | |
131 | include some instructions that have not yet been executed. */ | |
132 | int64_t qemu_icount; | |
6a00d601 | 133 | |
54936004 | 134 | typedef struct PageDesc { |
92e873b9 | 135 | /* list of TBs intersecting this ram page */ |
fd6ce8f6 | 136 | TranslationBlock *first_tb; |
9fa3e853 FB |
137 | /* in order to optimize self modifying code, we count the number |
138 | of lookups we do to a given page to use a bitmap */ | |
139 | unsigned int code_write_count; | |
140 | uint8_t *code_bitmap; | |
141 | #if defined(CONFIG_USER_ONLY) | |
142 | unsigned long flags; | |
143 | #endif | |
54936004 FB |
144 | } PageDesc; |
145 | ||
92e873b9 | 146 | typedef struct PhysPageDesc { |
0f459d16 | 147 | /* offset in host memory of the page + io_index in the low bits */ |
00f82b8a | 148 | ram_addr_t phys_offset; |
92e873b9 FB |
149 | } PhysPageDesc; |
150 | ||
54936004 | 151 | #define L2_BITS 10 |
bedb69ea JM |
152 | #if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS) |
153 | /* XXX: this is a temporary hack for alpha target. | |
154 | * In the future, this is to be replaced by a multi-level table | |
155 | * to actually be able to handle the complete 64 bits address space. | |
156 | */ | |
157 | #define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS) | |
158 | #else | |
03875444 | 159 | #define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS) |
bedb69ea | 160 | #endif |
54936004 FB |
161 | |
162 | #define L1_SIZE (1 << L1_BITS) | |
163 | #define L2_SIZE (1 << L2_BITS) | |
164 | ||
83fb7adf FB |
165 | unsigned long qemu_real_host_page_size; |
166 | unsigned long qemu_host_page_bits; | |
167 | unsigned long qemu_host_page_size; | |
168 | unsigned long qemu_host_page_mask; | |
54936004 | 169 | |
92e873b9 | 170 | /* XXX: for system emulation, it could just be an array */ |
54936004 | 171 | static PageDesc *l1_map[L1_SIZE]; |
bdaf78e0 | 172 | static PhysPageDesc **l1_phys_map; |
54936004 | 173 | |
e2eef170 PB |
174 | #if !defined(CONFIG_USER_ONLY) |
175 | static void io_mem_init(void); | |
176 | ||
33417e70 | 177 | /* io memory support */ |
33417e70 FB |
178 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
179 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 180 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
33417e70 | 181 | static int io_mem_nb; |
6658ffb8 PB |
182 | static int io_mem_watch; |
183 | #endif | |
33417e70 | 184 | |
34865134 | 185 | /* log support */ |
d9b630fd | 186 | static const char *logfilename = "/tmp/qemu.log"; |
34865134 FB |
187 | FILE *logfile; |
188 | int loglevel; | |
e735b91c | 189 | static int log_append = 0; |
34865134 | 190 | |
e3db7226 FB |
191 | /* statistics */ |
192 | static int tlb_flush_count; | |
193 | static int tb_flush_count; | |
194 | static int tb_phys_invalidate_count; | |
195 | ||
db7b5426 BS |
196 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
197 | typedef struct subpage_t { | |
198 | target_phys_addr_t base; | |
3ee89922 BS |
199 | CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4]; |
200 | CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4]; | |
201 | void *opaque[TARGET_PAGE_SIZE][2][4]; | |
db7b5426 BS |
202 | } subpage_t; |
203 | ||
7cb69cae FB |
204 | #ifdef _WIN32 |
205 | static void map_exec(void *addr, long size) | |
206 | { | |
207 | DWORD old_protect; | |
208 | VirtualProtect(addr, size, | |
209 | PAGE_EXECUTE_READWRITE, &old_protect); | |
210 | ||
211 | } | |
212 | #else | |
213 | static void map_exec(void *addr, long size) | |
214 | { | |
4369415f | 215 | unsigned long start, end, page_size; |
7cb69cae | 216 | |
4369415f | 217 | page_size = getpagesize(); |
7cb69cae | 218 | start = (unsigned long)addr; |
4369415f | 219 | start &= ~(page_size - 1); |
7cb69cae FB |
220 | |
221 | end = (unsigned long)addr + size; | |
4369415f FB |
222 | end += page_size - 1; |
223 | end &= ~(page_size - 1); | |
7cb69cae FB |
224 | |
225 | mprotect((void *)start, end - start, | |
226 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
227 | } | |
228 | #endif | |
229 | ||
b346ff46 | 230 | static void page_init(void) |
54936004 | 231 | { |
83fb7adf | 232 | /* NOTE: we can always suppose that qemu_host_page_size >= |
54936004 | 233 | TARGET_PAGE_SIZE */ |
15ed71ba | 234 | qemu_real_host_page_size = qemu_getpagesize(); |
83fb7adf FB |
235 | if (qemu_host_page_size == 0) |
236 | qemu_host_page_size = qemu_real_host_page_size; | |
237 | if (qemu_host_page_size < TARGET_PAGE_SIZE) | |
238 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
239 | qemu_host_page_bits = 0; | |
240 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) | |
241 | qemu_host_page_bits++; | |
242 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
108c49b8 FB |
243 | l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *)); |
244 | memset(l1_phys_map, 0, L1_SIZE * sizeof(void *)); | |
50a9569b AZ |
245 | |
246 | #if !defined(_WIN32) && defined(CONFIG_USER_ONLY) | |
247 | { | |
248 | long long startaddr, endaddr; | |
249 | FILE *f; | |
250 | int n; | |
251 | ||
c8a706fe | 252 | mmap_lock(); |
0776590d | 253 | last_brk = (unsigned long)sbrk(0); |
50a9569b AZ |
254 | f = fopen("/proc/self/maps", "r"); |
255 | if (f) { | |
256 | do { | |
257 | n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr); | |
258 | if (n == 2) { | |
e0b8d65a BS |
259 | startaddr = MIN(startaddr, |
260 | (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1); | |
261 | endaddr = MIN(endaddr, | |
262 | (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1); | |
b5fc909e | 263 | page_set_flags(startaddr & TARGET_PAGE_MASK, |
50a9569b AZ |
264 | TARGET_PAGE_ALIGN(endaddr), |
265 | PAGE_RESERVED); | |
266 | } | |
267 | } while (!feof(f)); | |
268 | fclose(f); | |
269 | } | |
c8a706fe | 270 | mmap_unlock(); |
50a9569b AZ |
271 | } |
272 | #endif | |
54936004 FB |
273 | } |
274 | ||
434929bf | 275 | static inline PageDesc **page_l1_map(target_ulong index) |
54936004 | 276 | { |
17e2377a PB |
277 | #if TARGET_LONG_BITS > 32 |
278 | /* Host memory outside guest VM. For 32-bit targets we have already | |
279 | excluded high addresses. */ | |
d8173e0f | 280 | if (index > ((target_ulong)L2_SIZE * L1_SIZE)) |
17e2377a PB |
281 | return NULL; |
282 | #endif | |
434929bf AL |
283 | return &l1_map[index >> L2_BITS]; |
284 | } | |
285 | ||
286 | static inline PageDesc *page_find_alloc(target_ulong index) | |
287 | { | |
288 | PageDesc **lp, *p; | |
289 | lp = page_l1_map(index); | |
290 | if (!lp) | |
291 | return NULL; | |
292 | ||
54936004 FB |
293 | p = *lp; |
294 | if (!p) { | |
295 | /* allocate if not found */ | |
17e2377a PB |
296 | #if defined(CONFIG_USER_ONLY) |
297 | unsigned long addr; | |
298 | size_t len = sizeof(PageDesc) * L2_SIZE; | |
299 | /* Don't use qemu_malloc because it may recurse. */ | |
300 | p = mmap(0, len, PROT_READ | PROT_WRITE, | |
301 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); | |
54936004 | 302 | *lp = p; |
17e2377a PB |
303 | addr = h2g(p); |
304 | if (addr == (target_ulong)addr) { | |
305 | page_set_flags(addr & TARGET_PAGE_MASK, | |
306 | TARGET_PAGE_ALIGN(addr + len), | |
307 | PAGE_RESERVED); | |
308 | } | |
309 | #else | |
310 | p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE); | |
311 | *lp = p; | |
312 | #endif | |
54936004 FB |
313 | } |
314 | return p + (index & (L2_SIZE - 1)); | |
315 | } | |
316 | ||
00f82b8a | 317 | static inline PageDesc *page_find(target_ulong index) |
54936004 | 318 | { |
434929bf AL |
319 | PageDesc **lp, *p; |
320 | lp = page_l1_map(index); | |
321 | if (!lp) | |
322 | return NULL; | |
54936004 | 323 | |
434929bf | 324 | p = *lp; |
54936004 FB |
325 | if (!p) |
326 | return 0; | |
fd6ce8f6 FB |
327 | return p + (index & (L2_SIZE - 1)); |
328 | } | |
329 | ||
108c49b8 | 330 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
92e873b9 | 331 | { |
108c49b8 | 332 | void **lp, **p; |
e3f4e2a4 | 333 | PhysPageDesc *pd; |
92e873b9 | 334 | |
108c49b8 FB |
335 | p = (void **)l1_phys_map; |
336 | #if TARGET_PHYS_ADDR_SPACE_BITS > 32 | |
337 | ||
338 | #if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS) | |
339 | #error unsupported TARGET_PHYS_ADDR_SPACE_BITS | |
340 | #endif | |
341 | lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1)); | |
92e873b9 FB |
342 | p = *lp; |
343 | if (!p) { | |
344 | /* allocate if not found */ | |
108c49b8 FB |
345 | if (!alloc) |
346 | return NULL; | |
347 | p = qemu_vmalloc(sizeof(void *) * L1_SIZE); | |
348 | memset(p, 0, sizeof(void *) * L1_SIZE); | |
349 | *lp = p; | |
350 | } | |
351 | #endif | |
352 | lp = p + ((index >> L2_BITS) & (L1_SIZE - 1)); | |
e3f4e2a4 PB |
353 | pd = *lp; |
354 | if (!pd) { | |
355 | int i; | |
108c49b8 FB |
356 | /* allocate if not found */ |
357 | if (!alloc) | |
358 | return NULL; | |
e3f4e2a4 PB |
359 | pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE); |
360 | *lp = pd; | |
361 | for (i = 0; i < L2_SIZE; i++) | |
362 | pd[i].phys_offset = IO_MEM_UNASSIGNED; | |
92e873b9 | 363 | } |
e3f4e2a4 | 364 | return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1)); |
92e873b9 FB |
365 | } |
366 | ||
108c49b8 | 367 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
92e873b9 | 368 | { |
108c49b8 | 369 | return phys_page_find_alloc(index, 0); |
92e873b9 FB |
370 | } |
371 | ||
9fa3e853 | 372 | #if !defined(CONFIG_USER_ONLY) |
6a00d601 | 373 | static void tlb_protect_code(ram_addr_t ram_addr); |
5fafdf24 | 374 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 375 | target_ulong vaddr); |
c8a706fe PB |
376 | #define mmap_lock() do { } while(0) |
377 | #define mmap_unlock() do { } while(0) | |
9fa3e853 | 378 | #endif |
fd6ce8f6 | 379 | |
4369415f FB |
380 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
381 | ||
382 | #if defined(CONFIG_USER_ONLY) | |
383 | /* Currently it is not recommanded to allocate big chunks of data in | |
384 | user mode. It will change when a dedicated libc will be used */ | |
385 | #define USE_STATIC_CODE_GEN_BUFFER | |
386 | #endif | |
387 | ||
388 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
389 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]; | |
390 | #endif | |
391 | ||
8fcd3692 | 392 | static void code_gen_alloc(unsigned long tb_size) |
26a5f13b | 393 | { |
4369415f FB |
394 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
395 | code_gen_buffer = static_code_gen_buffer; | |
396 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
397 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
398 | #else | |
26a5f13b FB |
399 | code_gen_buffer_size = tb_size; |
400 | if (code_gen_buffer_size == 0) { | |
4369415f FB |
401 | #if defined(CONFIG_USER_ONLY) |
402 | /* in user mode, phys_ram_size is not meaningful */ | |
403 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
404 | #else | |
26a5f13b | 405 | /* XXX: needs ajustments */ |
174a9a1f | 406 | code_gen_buffer_size = (unsigned long)(phys_ram_size / 4); |
4369415f | 407 | #endif |
26a5f13b FB |
408 | } |
409 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) | |
410 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; | |
411 | /* The code gen buffer location may have constraints depending on | |
412 | the host cpu and OS */ | |
413 | #if defined(__linux__) | |
414 | { | |
415 | int flags; | |
141ac468 BS |
416 | void *start = NULL; |
417 | ||
26a5f13b FB |
418 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
419 | #if defined(__x86_64__) | |
420 | flags |= MAP_32BIT; | |
421 | /* Cannot map more than that */ | |
422 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
423 | code_gen_buffer_size = (800 * 1024 * 1024); | |
141ac468 BS |
424 | #elif defined(__sparc_v9__) |
425 | // Map the buffer below 2G, so we can use direct calls and branches | |
426 | flags |= MAP_FIXED; | |
427 | start = (void *) 0x60000000UL; | |
428 | if (code_gen_buffer_size > (512 * 1024 * 1024)) | |
429 | code_gen_buffer_size = (512 * 1024 * 1024); | |
26a5f13b | 430 | #endif |
141ac468 BS |
431 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
432 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
26a5f13b FB |
433 | flags, -1, 0); |
434 | if (code_gen_buffer == MAP_FAILED) { | |
435 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
436 | exit(1); | |
437 | } | |
438 | } | |
06e67a82 AL |
439 | #elif defined(__FreeBSD__) |
440 | { | |
441 | int flags; | |
442 | void *addr = NULL; | |
443 | flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
444 | #if defined(__x86_64__) | |
445 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume | |
446 | * 0x40000000 is free */ | |
447 | flags |= MAP_FIXED; | |
448 | addr = (void *)0x40000000; | |
449 | /* Cannot map more than that */ | |
450 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
451 | code_gen_buffer_size = (800 * 1024 * 1024); | |
452 | #endif | |
453 | code_gen_buffer = mmap(addr, code_gen_buffer_size, | |
454 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
455 | flags, -1, 0); | |
456 | if (code_gen_buffer == MAP_FAILED) { | |
457 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
458 | exit(1); | |
459 | } | |
460 | } | |
26a5f13b FB |
461 | #else |
462 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); | |
463 | if (!code_gen_buffer) { | |
464 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
465 | exit(1); | |
466 | } | |
467 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
468 | #endif | |
4369415f | 469 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
26a5f13b FB |
470 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
471 | code_gen_buffer_max_size = code_gen_buffer_size - | |
472 | code_gen_max_block_size(); | |
473 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; | |
474 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); | |
475 | } | |
476 | ||
477 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
478 | (in bytes) allocated to the translation buffer. Zero means default | |
479 | size. */ | |
480 | void cpu_exec_init_all(unsigned long tb_size) | |
481 | { | |
26a5f13b FB |
482 | cpu_gen_init(); |
483 | code_gen_alloc(tb_size); | |
484 | code_gen_ptr = code_gen_buffer; | |
4369415f | 485 | page_init(); |
e2eef170 | 486 | #if !defined(CONFIG_USER_ONLY) |
26a5f13b | 487 | io_mem_init(); |
e2eef170 | 488 | #endif |
26a5f13b FB |
489 | } |
490 | ||
9656f324 PB |
491 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
492 | ||
493 | #define CPU_COMMON_SAVE_VERSION 1 | |
494 | ||
495 | static void cpu_common_save(QEMUFile *f, void *opaque) | |
496 | { | |
497 | CPUState *env = opaque; | |
498 | ||
499 | qemu_put_be32s(f, &env->halted); | |
500 | qemu_put_be32s(f, &env->interrupt_request); | |
501 | } | |
502 | ||
503 | static int cpu_common_load(QEMUFile *f, void *opaque, int version_id) | |
504 | { | |
505 | CPUState *env = opaque; | |
506 | ||
507 | if (version_id != CPU_COMMON_SAVE_VERSION) | |
508 | return -EINVAL; | |
509 | ||
510 | qemu_get_be32s(f, &env->halted); | |
75f482ae | 511 | qemu_get_be32s(f, &env->interrupt_request); |
9656f324 PB |
512 | tlb_flush(env, 1); |
513 | ||
514 | return 0; | |
515 | } | |
516 | #endif | |
517 | ||
6a00d601 | 518 | void cpu_exec_init(CPUState *env) |
fd6ce8f6 | 519 | { |
6a00d601 FB |
520 | CPUState **penv; |
521 | int cpu_index; | |
522 | ||
6a00d601 FB |
523 | env->next_cpu = NULL; |
524 | penv = &first_cpu; | |
525 | cpu_index = 0; | |
526 | while (*penv != NULL) { | |
527 | penv = (CPUState **)&(*penv)->next_cpu; | |
528 | cpu_index++; | |
529 | } | |
530 | env->cpu_index = cpu_index; | |
6658ffb8 | 531 | env->nb_watchpoints = 0; |
6a00d601 | 532 | *penv = env; |
b3c7724c | 533 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
9656f324 PB |
534 | register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION, |
535 | cpu_common_save, cpu_common_load, env); | |
b3c7724c PB |
536 | register_savevm("cpu", cpu_index, CPU_SAVE_VERSION, |
537 | cpu_save, cpu_load, env); | |
538 | #endif | |
fd6ce8f6 FB |
539 | } |
540 | ||
9fa3e853 FB |
541 | static inline void invalidate_page_bitmap(PageDesc *p) |
542 | { | |
543 | if (p->code_bitmap) { | |
59817ccb | 544 | qemu_free(p->code_bitmap); |
9fa3e853 FB |
545 | p->code_bitmap = NULL; |
546 | } | |
547 | p->code_write_count = 0; | |
548 | } | |
549 | ||
fd6ce8f6 FB |
550 | /* set to NULL all the 'first_tb' fields in all PageDescs */ |
551 | static void page_flush_tb(void) | |
552 | { | |
553 | int i, j; | |
554 | PageDesc *p; | |
555 | ||
556 | for(i = 0; i < L1_SIZE; i++) { | |
557 | p = l1_map[i]; | |
558 | if (p) { | |
9fa3e853 FB |
559 | for(j = 0; j < L2_SIZE; j++) { |
560 | p->first_tb = NULL; | |
561 | invalidate_page_bitmap(p); | |
562 | p++; | |
563 | } | |
fd6ce8f6 FB |
564 | } |
565 | } | |
566 | } | |
567 | ||
568 | /* flush all the translation blocks */ | |
d4e8164f | 569 | /* XXX: tb_flush is currently not thread safe */ |
6a00d601 | 570 | void tb_flush(CPUState *env1) |
fd6ce8f6 | 571 | { |
6a00d601 | 572 | CPUState *env; |
0124311e | 573 | #if defined(DEBUG_FLUSH) |
ab3d1727 BS |
574 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
575 | (unsigned long)(code_gen_ptr - code_gen_buffer), | |
576 | nb_tbs, nb_tbs > 0 ? | |
577 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); | |
fd6ce8f6 | 578 | #endif |
26a5f13b | 579 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
a208e54a PB |
580 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
581 | ||
fd6ce8f6 | 582 | nb_tbs = 0; |
3b46e624 | 583 | |
6a00d601 FB |
584 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
585 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
586 | } | |
9fa3e853 | 587 | |
8a8a608f | 588 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
fd6ce8f6 | 589 | page_flush_tb(); |
9fa3e853 | 590 | |
fd6ce8f6 | 591 | code_gen_ptr = code_gen_buffer; |
d4e8164f FB |
592 | /* XXX: flush processor icache at this point if cache flush is |
593 | expensive */ | |
e3db7226 | 594 | tb_flush_count++; |
fd6ce8f6 FB |
595 | } |
596 | ||
597 | #ifdef DEBUG_TB_CHECK | |
598 | ||
bc98a7ef | 599 | static void tb_invalidate_check(target_ulong address) |
fd6ce8f6 FB |
600 | { |
601 | TranslationBlock *tb; | |
602 | int i; | |
603 | address &= TARGET_PAGE_MASK; | |
99773bd4 PB |
604 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
605 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
606 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
607 | address >= tb->pc + tb->size)) { | |
608 | printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n", | |
99773bd4 | 609 | address, (long)tb->pc, tb->size); |
fd6ce8f6 FB |
610 | } |
611 | } | |
612 | } | |
613 | } | |
614 | ||
615 | /* verify that all the pages have correct rights for code */ | |
616 | static void tb_page_check(void) | |
617 | { | |
618 | TranslationBlock *tb; | |
619 | int i, flags1, flags2; | |
3b46e624 | 620 | |
99773bd4 PB |
621 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
622 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
623 | flags1 = page_get_flags(tb->pc); |
624 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
625 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
626 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
99773bd4 | 627 | (long)tb->pc, tb->size, flags1, flags2); |
fd6ce8f6 FB |
628 | } |
629 | } | |
630 | } | |
631 | } | |
632 | ||
bdaf78e0 | 633 | static void tb_jmp_check(TranslationBlock *tb) |
d4e8164f FB |
634 | { |
635 | TranslationBlock *tb1; | |
636 | unsigned int n1; | |
637 | ||
638 | /* suppress any remaining jumps to this TB */ | |
639 | tb1 = tb->jmp_first; | |
640 | for(;;) { | |
641 | n1 = (long)tb1 & 3; | |
642 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
643 | if (n1 == 2) | |
644 | break; | |
645 | tb1 = tb1->jmp_next[n1]; | |
646 | } | |
647 | /* check end of list */ | |
648 | if (tb1 != tb) { | |
649 | printf("ERROR: jmp_list from 0x%08lx\n", (long)tb); | |
650 | } | |
651 | } | |
652 | ||
fd6ce8f6 FB |
653 | #endif |
654 | ||
655 | /* invalidate one TB */ | |
656 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, | |
657 | int next_offset) | |
658 | { | |
659 | TranslationBlock *tb1; | |
660 | for(;;) { | |
661 | tb1 = *ptb; | |
662 | if (tb1 == tb) { | |
663 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); | |
664 | break; | |
665 | } | |
666 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); | |
667 | } | |
668 | } | |
669 | ||
9fa3e853 FB |
670 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
671 | { | |
672 | TranslationBlock *tb1; | |
673 | unsigned int n1; | |
674 | ||
675 | for(;;) { | |
676 | tb1 = *ptb; | |
677 | n1 = (long)tb1 & 3; | |
678 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
679 | if (tb1 == tb) { | |
680 | *ptb = tb1->page_next[n1]; | |
681 | break; | |
682 | } | |
683 | ptb = &tb1->page_next[n1]; | |
684 | } | |
685 | } | |
686 | ||
d4e8164f FB |
687 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
688 | { | |
689 | TranslationBlock *tb1, **ptb; | |
690 | unsigned int n1; | |
691 | ||
692 | ptb = &tb->jmp_next[n]; | |
693 | tb1 = *ptb; | |
694 | if (tb1) { | |
695 | /* find tb(n) in circular list */ | |
696 | for(;;) { | |
697 | tb1 = *ptb; | |
698 | n1 = (long)tb1 & 3; | |
699 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
700 | if (n1 == n && tb1 == tb) | |
701 | break; | |
702 | if (n1 == 2) { | |
703 | ptb = &tb1->jmp_first; | |
704 | } else { | |
705 | ptb = &tb1->jmp_next[n1]; | |
706 | } | |
707 | } | |
708 | /* now we can suppress tb(n) from the list */ | |
709 | *ptb = tb->jmp_next[n]; | |
710 | ||
711 | tb->jmp_next[n] = NULL; | |
712 | } | |
713 | } | |
714 | ||
715 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
716 | another TB */ | |
717 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
718 | { | |
719 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); | |
720 | } | |
721 | ||
2e70f6ef | 722 | void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr) |
fd6ce8f6 | 723 | { |
6a00d601 | 724 | CPUState *env; |
8a40a180 | 725 | PageDesc *p; |
d4e8164f | 726 | unsigned int h, n1; |
00f82b8a | 727 | target_phys_addr_t phys_pc; |
8a40a180 | 728 | TranslationBlock *tb1, *tb2; |
3b46e624 | 729 | |
8a40a180 FB |
730 | /* remove the TB from the hash list */ |
731 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
732 | h = tb_phys_hash_func(phys_pc); | |
5fafdf24 | 733 | tb_remove(&tb_phys_hash[h], tb, |
8a40a180 FB |
734 | offsetof(TranslationBlock, phys_hash_next)); |
735 | ||
736 | /* remove the TB from the page list */ | |
737 | if (tb->page_addr[0] != page_addr) { | |
738 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
739 | tb_page_remove(&p->first_tb, tb); | |
740 | invalidate_page_bitmap(p); | |
741 | } | |
742 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
743 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
744 | tb_page_remove(&p->first_tb, tb); | |
745 | invalidate_page_bitmap(p); | |
746 | } | |
747 | ||
36bdbe54 | 748 | tb_invalidated_flag = 1; |
59817ccb | 749 | |
fd6ce8f6 | 750 | /* remove the TB from the hash list */ |
8a40a180 | 751 | h = tb_jmp_cache_hash_func(tb->pc); |
6a00d601 FB |
752 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
753 | if (env->tb_jmp_cache[h] == tb) | |
754 | env->tb_jmp_cache[h] = NULL; | |
755 | } | |
d4e8164f FB |
756 | |
757 | /* suppress this TB from the two jump lists */ | |
758 | tb_jmp_remove(tb, 0); | |
759 | tb_jmp_remove(tb, 1); | |
760 | ||
761 | /* suppress any remaining jumps to this TB */ | |
762 | tb1 = tb->jmp_first; | |
763 | for(;;) { | |
764 | n1 = (long)tb1 & 3; | |
765 | if (n1 == 2) | |
766 | break; | |
767 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
768 | tb2 = tb1->jmp_next[n1]; | |
769 | tb_reset_jump(tb1, n1); | |
770 | tb1->jmp_next[n1] = NULL; | |
771 | tb1 = tb2; | |
772 | } | |
773 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ | |
9fa3e853 | 774 | |
e3db7226 | 775 | tb_phys_invalidate_count++; |
9fa3e853 FB |
776 | } |
777 | ||
778 | static inline void set_bits(uint8_t *tab, int start, int len) | |
779 | { | |
780 | int end, mask, end1; | |
781 | ||
782 | end = start + len; | |
783 | tab += start >> 3; | |
784 | mask = 0xff << (start & 7); | |
785 | if ((start & ~7) == (end & ~7)) { | |
786 | if (start < end) { | |
787 | mask &= ~(0xff << (end & 7)); | |
788 | *tab |= mask; | |
789 | } | |
790 | } else { | |
791 | *tab++ |= mask; | |
792 | start = (start + 8) & ~7; | |
793 | end1 = end & ~7; | |
794 | while (start < end1) { | |
795 | *tab++ = 0xff; | |
796 | start += 8; | |
797 | } | |
798 | if (start < end) { | |
799 | mask = ~(0xff << (end & 7)); | |
800 | *tab |= mask; | |
801 | } | |
802 | } | |
803 | } | |
804 | ||
805 | static void build_page_bitmap(PageDesc *p) | |
806 | { | |
807 | int n, tb_start, tb_end; | |
808 | TranslationBlock *tb; | |
3b46e624 | 809 | |
b2a7081a | 810 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); |
9fa3e853 FB |
811 | if (!p->code_bitmap) |
812 | return; | |
9fa3e853 FB |
813 | |
814 | tb = p->first_tb; | |
815 | while (tb != NULL) { | |
816 | n = (long)tb & 3; | |
817 | tb = (TranslationBlock *)((long)tb & ~3); | |
818 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
819 | if (n == 0) { | |
820 | /* NOTE: tb_end may be after the end of the page, but | |
821 | it is not a problem */ | |
822 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
823 | tb_end = tb_start + tb->size; | |
824 | if (tb_end > TARGET_PAGE_SIZE) | |
825 | tb_end = TARGET_PAGE_SIZE; | |
826 | } else { | |
827 | tb_start = 0; | |
828 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
829 | } | |
830 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
831 | tb = tb->page_next[n]; | |
832 | } | |
833 | } | |
834 | ||
2e70f6ef PB |
835 | TranslationBlock *tb_gen_code(CPUState *env, |
836 | target_ulong pc, target_ulong cs_base, | |
837 | int flags, int cflags) | |
d720b93d FB |
838 | { |
839 | TranslationBlock *tb; | |
840 | uint8_t *tc_ptr; | |
841 | target_ulong phys_pc, phys_page2, virt_page2; | |
842 | int code_gen_size; | |
843 | ||
c27004ec FB |
844 | phys_pc = get_phys_addr_code(env, pc); |
845 | tb = tb_alloc(pc); | |
d720b93d FB |
846 | if (!tb) { |
847 | /* flush must be done */ | |
848 | tb_flush(env); | |
849 | /* cannot fail at this point */ | |
c27004ec | 850 | tb = tb_alloc(pc); |
2e70f6ef PB |
851 | /* Don't forget to invalidate previous TB info. */ |
852 | tb_invalidated_flag = 1; | |
d720b93d FB |
853 | } |
854 | tc_ptr = code_gen_ptr; | |
855 | tb->tc_ptr = tc_ptr; | |
856 | tb->cs_base = cs_base; | |
857 | tb->flags = flags; | |
858 | tb->cflags = cflags; | |
d07bde88 | 859 | cpu_gen_code(env, tb, &code_gen_size); |
d720b93d | 860 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
3b46e624 | 861 | |
d720b93d | 862 | /* check next page if needed */ |
c27004ec | 863 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
d720b93d | 864 | phys_page2 = -1; |
c27004ec | 865 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
d720b93d FB |
866 | phys_page2 = get_phys_addr_code(env, virt_page2); |
867 | } | |
868 | tb_link_phys(tb, phys_pc, phys_page2); | |
2e70f6ef | 869 | return tb; |
d720b93d | 870 | } |
3b46e624 | 871 | |
9fa3e853 FB |
872 | /* invalidate all TBs which intersect with the target physical page |
873 | starting in range [start;end[. NOTE: start and end must refer to | |
d720b93d FB |
874 | the same physical page. 'is_cpu_write_access' should be true if called |
875 | from a real cpu write access: the virtual CPU will exit the current | |
876 | TB if code is modified inside this TB. */ | |
00f82b8a | 877 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, |
d720b93d FB |
878 | int is_cpu_write_access) |
879 | { | |
880 | int n, current_tb_modified, current_tb_not_found, current_flags; | |
d720b93d | 881 | CPUState *env = cpu_single_env; |
9fa3e853 | 882 | PageDesc *p; |
ea1c1802 | 883 | TranslationBlock *tb, *tb_next, *current_tb, *saved_tb; |
9fa3e853 | 884 | target_ulong tb_start, tb_end; |
d720b93d | 885 | target_ulong current_pc, current_cs_base; |
9fa3e853 FB |
886 | |
887 | p = page_find(start >> TARGET_PAGE_BITS); | |
5fafdf24 | 888 | if (!p) |
9fa3e853 | 889 | return; |
5fafdf24 | 890 | if (!p->code_bitmap && |
d720b93d FB |
891 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
892 | is_cpu_write_access) { | |
9fa3e853 FB |
893 | /* build code bitmap */ |
894 | build_page_bitmap(p); | |
895 | } | |
896 | ||
897 | /* we remove all the TBs in the range [start, end[ */ | |
898 | /* XXX: see if in some cases it could be faster to invalidate all the code */ | |
d720b93d FB |
899 | current_tb_not_found = is_cpu_write_access; |
900 | current_tb_modified = 0; | |
901 | current_tb = NULL; /* avoid warning */ | |
902 | current_pc = 0; /* avoid warning */ | |
903 | current_cs_base = 0; /* avoid warning */ | |
904 | current_flags = 0; /* avoid warning */ | |
9fa3e853 FB |
905 | tb = p->first_tb; |
906 | while (tb != NULL) { | |
907 | n = (long)tb & 3; | |
908 | tb = (TranslationBlock *)((long)tb & ~3); | |
909 | tb_next = tb->page_next[n]; | |
910 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
911 | if (n == 0) { | |
912 | /* NOTE: tb_end may be after the end of the page, but | |
913 | it is not a problem */ | |
914 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
915 | tb_end = tb_start + tb->size; | |
916 | } else { | |
917 | tb_start = tb->page_addr[1]; | |
918 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
919 | } | |
920 | if (!(tb_end <= start || tb_start >= end)) { | |
d720b93d FB |
921 | #ifdef TARGET_HAS_PRECISE_SMC |
922 | if (current_tb_not_found) { | |
923 | current_tb_not_found = 0; | |
924 | current_tb = NULL; | |
2e70f6ef | 925 | if (env->mem_io_pc) { |
d720b93d | 926 | /* now we have a real cpu fault */ |
2e70f6ef | 927 | current_tb = tb_find_pc(env->mem_io_pc); |
d720b93d FB |
928 | } |
929 | } | |
930 | if (current_tb == tb && | |
2e70f6ef | 931 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
932 | /* If we are modifying the current TB, we must stop |
933 | its execution. We could be more precise by checking | |
934 | that the modification is after the current PC, but it | |
935 | would require a specialized function to partially | |
936 | restore the CPU state */ | |
3b46e624 | 937 | |
d720b93d | 938 | current_tb_modified = 1; |
5fafdf24 | 939 | cpu_restore_state(current_tb, env, |
2e70f6ef | 940 | env->mem_io_pc, NULL); |
d720b93d FB |
941 | #if defined(TARGET_I386) |
942 | current_flags = env->hflags; | |
943 | current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); | |
944 | current_cs_base = (target_ulong)env->segs[R_CS].base; | |
945 | current_pc = current_cs_base + env->eip; | |
946 | #else | |
947 | #error unsupported CPU | |
948 | #endif | |
949 | } | |
950 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
6f5a9f7e FB |
951 | /* we need to do that to handle the case where a signal |
952 | occurs while doing tb_phys_invalidate() */ | |
953 | saved_tb = NULL; | |
954 | if (env) { | |
955 | saved_tb = env->current_tb; | |
956 | env->current_tb = NULL; | |
957 | } | |
9fa3e853 | 958 | tb_phys_invalidate(tb, -1); |
6f5a9f7e FB |
959 | if (env) { |
960 | env->current_tb = saved_tb; | |
961 | if (env->interrupt_request && env->current_tb) | |
962 | cpu_interrupt(env, env->interrupt_request); | |
963 | } | |
9fa3e853 FB |
964 | } |
965 | tb = tb_next; | |
966 | } | |
967 | #if !defined(CONFIG_USER_ONLY) | |
968 | /* if no code remaining, no need to continue to use slow writes */ | |
969 | if (!p->first_tb) { | |
970 | invalidate_page_bitmap(p); | |
d720b93d | 971 | if (is_cpu_write_access) { |
2e70f6ef | 972 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
d720b93d FB |
973 | } |
974 | } | |
975 | #endif | |
976 | #ifdef TARGET_HAS_PRECISE_SMC | |
977 | if (current_tb_modified) { | |
978 | /* we generate a block containing just the instruction | |
979 | modifying the memory. It will ensure that it cannot modify | |
980 | itself */ | |
ea1c1802 | 981 | env->current_tb = NULL; |
2e70f6ef | 982 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d | 983 | cpu_resume_from_signal(env, NULL); |
9fa3e853 | 984 | } |
fd6ce8f6 | 985 | #endif |
9fa3e853 | 986 | } |
fd6ce8f6 | 987 | |
9fa3e853 | 988 | /* len must be <= 8 and start must be a multiple of len */ |
00f82b8a | 989 | static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len) |
9fa3e853 FB |
990 | { |
991 | PageDesc *p; | |
992 | int offset, b; | |
59817ccb | 993 | #if 0 |
a4193c8a FB |
994 | if (1) { |
995 | if (loglevel) { | |
5fafdf24 | 996 | fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
2e70f6ef | 997 | cpu_single_env->mem_io_vaddr, len, |
5fafdf24 | 998 | cpu_single_env->eip, |
a4193c8a FB |
999 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); |
1000 | } | |
59817ccb FB |
1001 | } |
1002 | #endif | |
9fa3e853 | 1003 | p = page_find(start >> TARGET_PAGE_BITS); |
5fafdf24 | 1004 | if (!p) |
9fa3e853 FB |
1005 | return; |
1006 | if (p->code_bitmap) { | |
1007 | offset = start & ~TARGET_PAGE_MASK; | |
1008 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
1009 | if (b & ((1 << len) - 1)) | |
1010 | goto do_invalidate; | |
1011 | } else { | |
1012 | do_invalidate: | |
d720b93d | 1013 | tb_invalidate_phys_page_range(start, start + len, 1); |
9fa3e853 FB |
1014 | } |
1015 | } | |
1016 | ||
9fa3e853 | 1017 | #if !defined(CONFIG_SOFTMMU) |
00f82b8a | 1018 | static void tb_invalidate_phys_page(target_phys_addr_t addr, |
d720b93d | 1019 | unsigned long pc, void *puc) |
9fa3e853 | 1020 | { |
d720b93d FB |
1021 | int n, current_flags, current_tb_modified; |
1022 | target_ulong current_pc, current_cs_base; | |
9fa3e853 | 1023 | PageDesc *p; |
d720b93d FB |
1024 | TranslationBlock *tb, *current_tb; |
1025 | #ifdef TARGET_HAS_PRECISE_SMC | |
1026 | CPUState *env = cpu_single_env; | |
1027 | #endif | |
9fa3e853 FB |
1028 | |
1029 | addr &= TARGET_PAGE_MASK; | |
1030 | p = page_find(addr >> TARGET_PAGE_BITS); | |
5fafdf24 | 1031 | if (!p) |
9fa3e853 FB |
1032 | return; |
1033 | tb = p->first_tb; | |
d720b93d FB |
1034 | current_tb_modified = 0; |
1035 | current_tb = NULL; | |
1036 | current_pc = 0; /* avoid warning */ | |
1037 | current_cs_base = 0; /* avoid warning */ | |
1038 | current_flags = 0; /* avoid warning */ | |
1039 | #ifdef TARGET_HAS_PRECISE_SMC | |
1040 | if (tb && pc != 0) { | |
1041 | current_tb = tb_find_pc(pc); | |
1042 | } | |
1043 | #endif | |
9fa3e853 FB |
1044 | while (tb != NULL) { |
1045 | n = (long)tb & 3; | |
1046 | tb = (TranslationBlock *)((long)tb & ~3); | |
d720b93d FB |
1047 | #ifdef TARGET_HAS_PRECISE_SMC |
1048 | if (current_tb == tb && | |
2e70f6ef | 1049 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1050 | /* If we are modifying the current TB, we must stop |
1051 | its execution. We could be more precise by checking | |
1052 | that the modification is after the current PC, but it | |
1053 | would require a specialized function to partially | |
1054 | restore the CPU state */ | |
3b46e624 | 1055 | |
d720b93d FB |
1056 | current_tb_modified = 1; |
1057 | cpu_restore_state(current_tb, env, pc, puc); | |
1058 | #if defined(TARGET_I386) | |
1059 | current_flags = env->hflags; | |
1060 | current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); | |
1061 | current_cs_base = (target_ulong)env->segs[R_CS].base; | |
1062 | current_pc = current_cs_base + env->eip; | |
1063 | #else | |
1064 | #error unsupported CPU | |
1065 | #endif | |
1066 | } | |
1067 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1068 | tb_phys_invalidate(tb, addr); |
1069 | tb = tb->page_next[n]; | |
1070 | } | |
fd6ce8f6 | 1071 | p->first_tb = NULL; |
d720b93d FB |
1072 | #ifdef TARGET_HAS_PRECISE_SMC |
1073 | if (current_tb_modified) { | |
1074 | /* we generate a block containing just the instruction | |
1075 | modifying the memory. It will ensure that it cannot modify | |
1076 | itself */ | |
ea1c1802 | 1077 | env->current_tb = NULL; |
2e70f6ef | 1078 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d FB |
1079 | cpu_resume_from_signal(env, puc); |
1080 | } | |
1081 | #endif | |
fd6ce8f6 | 1082 | } |
9fa3e853 | 1083 | #endif |
fd6ce8f6 FB |
1084 | |
1085 | /* add the tb in the target page and protect it if necessary */ | |
5fafdf24 | 1086 | static inline void tb_alloc_page(TranslationBlock *tb, |
53a5960a | 1087 | unsigned int n, target_ulong page_addr) |
fd6ce8f6 FB |
1088 | { |
1089 | PageDesc *p; | |
9fa3e853 FB |
1090 | TranslationBlock *last_first_tb; |
1091 | ||
1092 | tb->page_addr[n] = page_addr; | |
3a7d929e | 1093 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
1094 | tb->page_next[n] = p->first_tb; |
1095 | last_first_tb = p->first_tb; | |
1096 | p->first_tb = (TranslationBlock *)((long)tb | n); | |
1097 | invalidate_page_bitmap(p); | |
fd6ce8f6 | 1098 | |
107db443 | 1099 | #if defined(TARGET_HAS_SMC) || 1 |
d720b93d | 1100 | |
9fa3e853 | 1101 | #if defined(CONFIG_USER_ONLY) |
fd6ce8f6 | 1102 | if (p->flags & PAGE_WRITE) { |
53a5960a PB |
1103 | target_ulong addr; |
1104 | PageDesc *p2; | |
9fa3e853 FB |
1105 | int prot; |
1106 | ||
fd6ce8f6 FB |
1107 | /* force the host page as non writable (writes will have a |
1108 | page fault + mprotect overhead) */ | |
53a5960a | 1109 | page_addr &= qemu_host_page_mask; |
fd6ce8f6 | 1110 | prot = 0; |
53a5960a PB |
1111 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
1112 | addr += TARGET_PAGE_SIZE) { | |
1113 | ||
1114 | p2 = page_find (addr >> TARGET_PAGE_BITS); | |
1115 | if (!p2) | |
1116 | continue; | |
1117 | prot |= p2->flags; | |
1118 | p2->flags &= ~PAGE_WRITE; | |
1119 | page_get_flags(addr); | |
1120 | } | |
5fafdf24 | 1121 | mprotect(g2h(page_addr), qemu_host_page_size, |
fd6ce8f6 FB |
1122 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
1123 | #ifdef DEBUG_TB_INVALIDATE | |
ab3d1727 | 1124 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
53a5960a | 1125 | page_addr); |
fd6ce8f6 | 1126 | #endif |
fd6ce8f6 | 1127 | } |
9fa3e853 FB |
1128 | #else |
1129 | /* if some code is already present, then the pages are already | |
1130 | protected. So we handle the case where only the first TB is | |
1131 | allocated in a physical page */ | |
1132 | if (!last_first_tb) { | |
6a00d601 | 1133 | tlb_protect_code(page_addr); |
9fa3e853 FB |
1134 | } |
1135 | #endif | |
d720b93d FB |
1136 | |
1137 | #endif /* TARGET_HAS_SMC */ | |
fd6ce8f6 FB |
1138 | } |
1139 | ||
1140 | /* Allocate a new translation block. Flush the translation buffer if | |
1141 | too many translation blocks or too much generated code. */ | |
c27004ec | 1142 | TranslationBlock *tb_alloc(target_ulong pc) |
fd6ce8f6 FB |
1143 | { |
1144 | TranslationBlock *tb; | |
fd6ce8f6 | 1145 | |
26a5f13b FB |
1146 | if (nb_tbs >= code_gen_max_blocks || |
1147 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) | |
d4e8164f | 1148 | return NULL; |
fd6ce8f6 FB |
1149 | tb = &tbs[nb_tbs++]; |
1150 | tb->pc = pc; | |
b448f2f3 | 1151 | tb->cflags = 0; |
d4e8164f FB |
1152 | return tb; |
1153 | } | |
1154 | ||
2e70f6ef PB |
1155 | void tb_free(TranslationBlock *tb) |
1156 | { | |
bf20dc07 | 1157 | /* In practice this is mostly used for single use temporary TB |
2e70f6ef PB |
1158 | Ignore the hard cases and just back up if this TB happens to |
1159 | be the last one generated. */ | |
1160 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { | |
1161 | code_gen_ptr = tb->tc_ptr; | |
1162 | nb_tbs--; | |
1163 | } | |
1164 | } | |
1165 | ||
9fa3e853 FB |
1166 | /* add a new TB and link it to the physical page tables. phys_page2 is |
1167 | (-1) to indicate that only one page contains the TB. */ | |
5fafdf24 | 1168 | void tb_link_phys(TranslationBlock *tb, |
9fa3e853 | 1169 | target_ulong phys_pc, target_ulong phys_page2) |
d4e8164f | 1170 | { |
9fa3e853 FB |
1171 | unsigned int h; |
1172 | TranslationBlock **ptb; | |
1173 | ||
c8a706fe PB |
1174 | /* Grab the mmap lock to stop another thread invalidating this TB |
1175 | before we are done. */ | |
1176 | mmap_lock(); | |
9fa3e853 FB |
1177 | /* add in the physical hash table */ |
1178 | h = tb_phys_hash_func(phys_pc); | |
1179 | ptb = &tb_phys_hash[h]; | |
1180 | tb->phys_hash_next = *ptb; | |
1181 | *ptb = tb; | |
fd6ce8f6 FB |
1182 | |
1183 | /* add in the page list */ | |
9fa3e853 FB |
1184 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
1185 | if (phys_page2 != -1) | |
1186 | tb_alloc_page(tb, 1, phys_page2); | |
1187 | else | |
1188 | tb->page_addr[1] = -1; | |
9fa3e853 | 1189 | |
d4e8164f FB |
1190 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
1191 | tb->jmp_next[0] = NULL; | |
1192 | tb->jmp_next[1] = NULL; | |
1193 | ||
1194 | /* init original jump addresses */ | |
1195 | if (tb->tb_next_offset[0] != 0xffff) | |
1196 | tb_reset_jump(tb, 0); | |
1197 | if (tb->tb_next_offset[1] != 0xffff) | |
1198 | tb_reset_jump(tb, 1); | |
8a40a180 FB |
1199 | |
1200 | #ifdef DEBUG_TB_CHECK | |
1201 | tb_page_check(); | |
1202 | #endif | |
c8a706fe | 1203 | mmap_unlock(); |
fd6ce8f6 FB |
1204 | } |
1205 | ||
9fa3e853 FB |
1206 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1207 | tb[1].tc_ptr. Return NULL if not found */ | |
1208 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) | |
fd6ce8f6 | 1209 | { |
9fa3e853 FB |
1210 | int m_min, m_max, m; |
1211 | unsigned long v; | |
1212 | TranslationBlock *tb; | |
a513fe19 FB |
1213 | |
1214 | if (nb_tbs <= 0) | |
1215 | return NULL; | |
1216 | if (tc_ptr < (unsigned long)code_gen_buffer || | |
1217 | tc_ptr >= (unsigned long)code_gen_ptr) | |
1218 | return NULL; | |
1219 | /* binary search (cf Knuth) */ | |
1220 | m_min = 0; | |
1221 | m_max = nb_tbs - 1; | |
1222 | while (m_min <= m_max) { | |
1223 | m = (m_min + m_max) >> 1; | |
1224 | tb = &tbs[m]; | |
1225 | v = (unsigned long)tb->tc_ptr; | |
1226 | if (v == tc_ptr) | |
1227 | return tb; | |
1228 | else if (tc_ptr < v) { | |
1229 | m_max = m - 1; | |
1230 | } else { | |
1231 | m_min = m + 1; | |
1232 | } | |
5fafdf24 | 1233 | } |
a513fe19 FB |
1234 | return &tbs[m_max]; |
1235 | } | |
7501267e | 1236 | |
ea041c0e FB |
1237 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
1238 | ||
1239 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1240 | { | |
1241 | TranslationBlock *tb1, *tb_next, **ptb; | |
1242 | unsigned int n1; | |
1243 | ||
1244 | tb1 = tb->jmp_next[n]; | |
1245 | if (tb1 != NULL) { | |
1246 | /* find head of list */ | |
1247 | for(;;) { | |
1248 | n1 = (long)tb1 & 3; | |
1249 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1250 | if (n1 == 2) | |
1251 | break; | |
1252 | tb1 = tb1->jmp_next[n1]; | |
1253 | } | |
1254 | /* we are now sure now that tb jumps to tb1 */ | |
1255 | tb_next = tb1; | |
1256 | ||
1257 | /* remove tb from the jmp_first list */ | |
1258 | ptb = &tb_next->jmp_first; | |
1259 | for(;;) { | |
1260 | tb1 = *ptb; | |
1261 | n1 = (long)tb1 & 3; | |
1262 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1263 | if (n1 == n && tb1 == tb) | |
1264 | break; | |
1265 | ptb = &tb1->jmp_next[n1]; | |
1266 | } | |
1267 | *ptb = tb->jmp_next[n]; | |
1268 | tb->jmp_next[n] = NULL; | |
3b46e624 | 1269 | |
ea041c0e FB |
1270 | /* suppress the jump to next tb in generated code */ |
1271 | tb_reset_jump(tb, n); | |
1272 | ||
0124311e | 1273 | /* suppress jumps in the tb on which we could have jumped */ |
ea041c0e FB |
1274 | tb_reset_jump_recursive(tb_next); |
1275 | } | |
1276 | } | |
1277 | ||
1278 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1279 | { | |
1280 | tb_reset_jump_recursive2(tb, 0); | |
1281 | tb_reset_jump_recursive2(tb, 1); | |
1282 | } | |
1283 | ||
1fddef4b | 1284 | #if defined(TARGET_HAS_ICE) |
d720b93d FB |
1285 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
1286 | { | |
9b3c35e0 JM |
1287 | target_phys_addr_t addr; |
1288 | target_ulong pd; | |
c2f07f81 PB |
1289 | ram_addr_t ram_addr; |
1290 | PhysPageDesc *p; | |
d720b93d | 1291 | |
c2f07f81 PB |
1292 | addr = cpu_get_phys_page_debug(env, pc); |
1293 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
1294 | if (!p) { | |
1295 | pd = IO_MEM_UNASSIGNED; | |
1296 | } else { | |
1297 | pd = p->phys_offset; | |
1298 | } | |
1299 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); | |
706cd4b5 | 1300 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
d720b93d | 1301 | } |
c27004ec | 1302 | #endif |
d720b93d | 1303 | |
6658ffb8 | 1304 | /* Add a watchpoint. */ |
0f459d16 | 1305 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, int type) |
6658ffb8 PB |
1306 | { |
1307 | int i; | |
1308 | ||
1309 | for (i = 0; i < env->nb_watchpoints; i++) { | |
1310 | if (addr == env->watchpoint[i].vaddr) | |
1311 | return 0; | |
1312 | } | |
1313 | if (env->nb_watchpoints >= MAX_WATCHPOINTS) | |
1314 | return -1; | |
1315 | ||
1316 | i = env->nb_watchpoints++; | |
1317 | env->watchpoint[i].vaddr = addr; | |
0f459d16 | 1318 | env->watchpoint[i].type = type; |
6658ffb8 PB |
1319 | tlb_flush_page(env, addr); |
1320 | /* FIXME: This flush is needed because of the hack to make memory ops | |
1321 | terminate the TB. It can be removed once the proper IO trap and | |
1322 | re-execute bits are in. */ | |
1323 | tb_flush(env); | |
1324 | return i; | |
1325 | } | |
1326 | ||
1327 | /* Remove a watchpoint. */ | |
1328 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr) | |
1329 | { | |
1330 | int i; | |
1331 | ||
1332 | for (i = 0; i < env->nb_watchpoints; i++) { | |
1333 | if (addr == env->watchpoint[i].vaddr) { | |
1334 | env->nb_watchpoints--; | |
1335 | env->watchpoint[i] = env->watchpoint[env->nb_watchpoints]; | |
1336 | tlb_flush_page(env, addr); | |
1337 | return 0; | |
1338 | } | |
1339 | } | |
1340 | return -1; | |
1341 | } | |
1342 | ||
7d03f82f EI |
1343 | /* Remove all watchpoints. */ |
1344 | void cpu_watchpoint_remove_all(CPUState *env) { | |
1345 | int i; | |
1346 | ||
1347 | for (i = 0; i < env->nb_watchpoints; i++) { | |
1348 | tlb_flush_page(env, env->watchpoint[i].vaddr); | |
1349 | } | |
1350 | env->nb_watchpoints = 0; | |
1351 | } | |
1352 | ||
c33a346e FB |
1353 | /* add a breakpoint. EXCP_DEBUG is returned by the CPU loop if a |
1354 | breakpoint is reached */ | |
2e12669a | 1355 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc) |
4c3a88a2 | 1356 | { |
1fddef4b | 1357 | #if defined(TARGET_HAS_ICE) |
4c3a88a2 | 1358 | int i; |
3b46e624 | 1359 | |
4c3a88a2 FB |
1360 | for(i = 0; i < env->nb_breakpoints; i++) { |
1361 | if (env->breakpoints[i] == pc) | |
1362 | return 0; | |
1363 | } | |
1364 | ||
1365 | if (env->nb_breakpoints >= MAX_BREAKPOINTS) | |
1366 | return -1; | |
1367 | env->breakpoints[env->nb_breakpoints++] = pc; | |
3b46e624 | 1368 | |
d720b93d | 1369 | breakpoint_invalidate(env, pc); |
4c3a88a2 FB |
1370 | return 0; |
1371 | #else | |
1372 | return -1; | |
1373 | #endif | |
1374 | } | |
1375 | ||
7d03f82f EI |
1376 | /* remove all breakpoints */ |
1377 | void cpu_breakpoint_remove_all(CPUState *env) { | |
1378 | #if defined(TARGET_HAS_ICE) | |
1379 | int i; | |
1380 | for(i = 0; i < env->nb_breakpoints; i++) { | |
1381 | breakpoint_invalidate(env, env->breakpoints[i]); | |
1382 | } | |
1383 | env->nb_breakpoints = 0; | |
1384 | #endif | |
1385 | } | |
1386 | ||
4c3a88a2 | 1387 | /* remove a breakpoint */ |
2e12669a | 1388 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc) |
4c3a88a2 | 1389 | { |
1fddef4b | 1390 | #if defined(TARGET_HAS_ICE) |
4c3a88a2 FB |
1391 | int i; |
1392 | for(i = 0; i < env->nb_breakpoints; i++) { | |
1393 | if (env->breakpoints[i] == pc) | |
1394 | goto found; | |
1395 | } | |
1396 | return -1; | |
1397 | found: | |
4c3a88a2 | 1398 | env->nb_breakpoints--; |
1fddef4b FB |
1399 | if (i < env->nb_breakpoints) |
1400 | env->breakpoints[i] = env->breakpoints[env->nb_breakpoints]; | |
d720b93d FB |
1401 | |
1402 | breakpoint_invalidate(env, pc); | |
4c3a88a2 FB |
1403 | return 0; |
1404 | #else | |
1405 | return -1; | |
1406 | #endif | |
1407 | } | |
1408 | ||
c33a346e FB |
1409 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1410 | CPU loop after each instruction */ | |
1411 | void cpu_single_step(CPUState *env, int enabled) | |
1412 | { | |
1fddef4b | 1413 | #if defined(TARGET_HAS_ICE) |
c33a346e FB |
1414 | if (env->singlestep_enabled != enabled) { |
1415 | env->singlestep_enabled = enabled; | |
1416 | /* must flush all the translated code to avoid inconsistancies */ | |
9fa3e853 | 1417 | /* XXX: only flush what is necessary */ |
0124311e | 1418 | tb_flush(env); |
c33a346e FB |
1419 | } |
1420 | #endif | |
1421 | } | |
1422 | ||
34865134 FB |
1423 | /* enable or disable low levels log */ |
1424 | void cpu_set_log(int log_flags) | |
1425 | { | |
1426 | loglevel = log_flags; | |
1427 | if (loglevel && !logfile) { | |
11fcfab4 | 1428 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
34865134 FB |
1429 | if (!logfile) { |
1430 | perror(logfilename); | |
1431 | _exit(1); | |
1432 | } | |
9fa3e853 FB |
1433 | #if !defined(CONFIG_SOFTMMU) |
1434 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
1435 | { | |
b55266b5 | 1436 | static char logfile_buf[4096]; |
9fa3e853 FB |
1437 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
1438 | } | |
1439 | #else | |
34865134 | 1440 | setvbuf(logfile, NULL, _IOLBF, 0); |
9fa3e853 | 1441 | #endif |
e735b91c PB |
1442 | log_append = 1; |
1443 | } | |
1444 | if (!loglevel && logfile) { | |
1445 | fclose(logfile); | |
1446 | logfile = NULL; | |
34865134 FB |
1447 | } |
1448 | } | |
1449 | ||
1450 | void cpu_set_log_filename(const char *filename) | |
1451 | { | |
1452 | logfilename = strdup(filename); | |
e735b91c PB |
1453 | if (logfile) { |
1454 | fclose(logfile); | |
1455 | logfile = NULL; | |
1456 | } | |
1457 | cpu_set_log(loglevel); | |
34865134 | 1458 | } |
c33a346e | 1459 | |
0124311e | 1460 | /* mask must never be zero, except for A20 change call */ |
68a79315 | 1461 | void cpu_interrupt(CPUState *env, int mask) |
ea041c0e | 1462 | { |
d5975363 | 1463 | #if !defined(USE_NPTL) |
ea041c0e | 1464 | TranslationBlock *tb; |
15a51156 | 1465 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
d5975363 | 1466 | #endif |
2e70f6ef | 1467 | int old_mask; |
59817ccb | 1468 | |
2e70f6ef | 1469 | old_mask = env->interrupt_request; |
d5975363 | 1470 | /* FIXME: This is probably not threadsafe. A different thread could |
bf20dc07 | 1471 | be in the middle of a read-modify-write operation. */ |
68a79315 | 1472 | env->interrupt_request |= mask; |
d5975363 PB |
1473 | #if defined(USE_NPTL) |
1474 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the | |
1475 | problem and hope the cpu will stop of its own accord. For userspace | |
1476 | emulation this often isn't actually as bad as it sounds. Often | |
1477 | signals are used primarily to interrupt blocking syscalls. */ | |
1478 | #else | |
2e70f6ef | 1479 | if (use_icount) { |
266910c4 | 1480 | env->icount_decr.u16.high = 0xffff; |
2e70f6ef PB |
1481 | #ifndef CONFIG_USER_ONLY |
1482 | /* CPU_INTERRUPT_EXIT isn't a real interrupt. It just means | |
1483 | an async event happened and we need to process it. */ | |
1484 | if (!can_do_io(env) | |
1485 | && (mask & ~(old_mask | CPU_INTERRUPT_EXIT)) != 0) { | |
1486 | cpu_abort(env, "Raised interrupt while not in I/O function"); | |
1487 | } | |
1488 | #endif | |
1489 | } else { | |
1490 | tb = env->current_tb; | |
1491 | /* if the cpu is currently executing code, we must unlink it and | |
1492 | all the potentially executing TB */ | |
1493 | if (tb && !testandset(&interrupt_lock)) { | |
1494 | env->current_tb = NULL; | |
1495 | tb_reset_jump_recursive(tb); | |
1496 | resetlock(&interrupt_lock); | |
1497 | } | |
ea041c0e | 1498 | } |
d5975363 | 1499 | #endif |
ea041c0e FB |
1500 | } |
1501 | ||
b54ad049 FB |
1502 | void cpu_reset_interrupt(CPUState *env, int mask) |
1503 | { | |
1504 | env->interrupt_request &= ~mask; | |
1505 | } | |
1506 | ||
c7cd6a37 | 1507 | const CPULogItem cpu_log_items[] = { |
5fafdf24 | 1508 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
f193c797 FB |
1509 | "show generated host assembly code for each compiled TB" }, |
1510 | { CPU_LOG_TB_IN_ASM, "in_asm", | |
1511 | "show target assembly code for each compiled TB" }, | |
5fafdf24 | 1512 | { CPU_LOG_TB_OP, "op", |
57fec1fe | 1513 | "show micro ops for each compiled TB" }, |
f193c797 | 1514 | { CPU_LOG_TB_OP_OPT, "op_opt", |
e01a1157 BS |
1515 | "show micro ops " |
1516 | #ifdef TARGET_I386 | |
1517 | "before eflags optimization and " | |
f193c797 | 1518 | #endif |
e01a1157 | 1519 | "after liveness analysis" }, |
f193c797 FB |
1520 | { CPU_LOG_INT, "int", |
1521 | "show interrupts/exceptions in short format" }, | |
1522 | { CPU_LOG_EXEC, "exec", | |
1523 | "show trace before each executed TB (lots of logs)" }, | |
9fddaa0c | 1524 | { CPU_LOG_TB_CPU, "cpu", |
e91c8a77 | 1525 | "show CPU state before block translation" }, |
f193c797 FB |
1526 | #ifdef TARGET_I386 |
1527 | { CPU_LOG_PCALL, "pcall", | |
1528 | "show protected mode far calls/returns/exceptions" }, | |
1529 | #endif | |
8e3a9fd2 | 1530 | #ifdef DEBUG_IOPORT |
fd872598 FB |
1531 | { CPU_LOG_IOPORT, "ioport", |
1532 | "show all i/o ports accesses" }, | |
8e3a9fd2 | 1533 | #endif |
f193c797 FB |
1534 | { 0, NULL, NULL }, |
1535 | }; | |
1536 | ||
1537 | static int cmp1(const char *s1, int n, const char *s2) | |
1538 | { | |
1539 | if (strlen(s2) != n) | |
1540 | return 0; | |
1541 | return memcmp(s1, s2, n) == 0; | |
1542 | } | |
3b46e624 | 1543 | |
f193c797 FB |
1544 | /* takes a comma separated list of log masks. Return 0 if error. */ |
1545 | int cpu_str_to_log_mask(const char *str) | |
1546 | { | |
c7cd6a37 | 1547 | const CPULogItem *item; |
f193c797 FB |
1548 | int mask; |
1549 | const char *p, *p1; | |
1550 | ||
1551 | p = str; | |
1552 | mask = 0; | |
1553 | for(;;) { | |
1554 | p1 = strchr(p, ','); | |
1555 | if (!p1) | |
1556 | p1 = p + strlen(p); | |
8e3a9fd2 FB |
1557 | if(cmp1(p,p1-p,"all")) { |
1558 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1559 | mask |= item->mask; | |
1560 | } | |
1561 | } else { | |
f193c797 FB |
1562 | for(item = cpu_log_items; item->mask != 0; item++) { |
1563 | if (cmp1(p, p1 - p, item->name)) | |
1564 | goto found; | |
1565 | } | |
1566 | return 0; | |
8e3a9fd2 | 1567 | } |
f193c797 FB |
1568 | found: |
1569 | mask |= item->mask; | |
1570 | if (*p1 != ',') | |
1571 | break; | |
1572 | p = p1 + 1; | |
1573 | } | |
1574 | return mask; | |
1575 | } | |
ea041c0e | 1576 | |
7501267e FB |
1577 | void cpu_abort(CPUState *env, const char *fmt, ...) |
1578 | { | |
1579 | va_list ap; | |
493ae1f0 | 1580 | va_list ap2; |
7501267e FB |
1581 | |
1582 | va_start(ap, fmt); | |
493ae1f0 | 1583 | va_copy(ap2, ap); |
7501267e FB |
1584 | fprintf(stderr, "qemu: fatal: "); |
1585 | vfprintf(stderr, fmt, ap); | |
1586 | fprintf(stderr, "\n"); | |
1587 | #ifdef TARGET_I386 | |
7fe48483 FB |
1588 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
1589 | #else | |
1590 | cpu_dump_state(env, stderr, fprintf, 0); | |
7501267e | 1591 | #endif |
924edcae | 1592 | if (logfile) { |
f9373291 | 1593 | fprintf(logfile, "qemu: fatal: "); |
493ae1f0 | 1594 | vfprintf(logfile, fmt, ap2); |
f9373291 JM |
1595 | fprintf(logfile, "\n"); |
1596 | #ifdef TARGET_I386 | |
1597 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); | |
1598 | #else | |
1599 | cpu_dump_state(env, logfile, fprintf, 0); | |
1600 | #endif | |
924edcae AZ |
1601 | fflush(logfile); |
1602 | fclose(logfile); | |
1603 | } | |
493ae1f0 | 1604 | va_end(ap2); |
f9373291 | 1605 | va_end(ap); |
7501267e FB |
1606 | abort(); |
1607 | } | |
1608 | ||
c5be9f08 TS |
1609 | CPUState *cpu_copy(CPUState *env) |
1610 | { | |
01ba9816 | 1611 | CPUState *new_env = cpu_init(env->cpu_model_str); |
c5be9f08 TS |
1612 | /* preserve chaining and index */ |
1613 | CPUState *next_cpu = new_env->next_cpu; | |
1614 | int cpu_index = new_env->cpu_index; | |
1615 | memcpy(new_env, env, sizeof(CPUState)); | |
1616 | new_env->next_cpu = next_cpu; | |
1617 | new_env->cpu_index = cpu_index; | |
1618 | return new_env; | |
1619 | } | |
1620 | ||
0124311e FB |
1621 | #if !defined(CONFIG_USER_ONLY) |
1622 | ||
5c751e99 EI |
1623 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
1624 | { | |
1625 | unsigned int i; | |
1626 | ||
1627 | /* Discard jump cache entries for any tb which might potentially | |
1628 | overlap the flushed page. */ | |
1629 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1630 | memset (&env->tb_jmp_cache[i], 0, | |
1631 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1632 | ||
1633 | i = tb_jmp_cache_hash_page(addr); | |
1634 | memset (&env->tb_jmp_cache[i], 0, | |
1635 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1636 | } | |
1637 | ||
ee8b7021 FB |
1638 | /* NOTE: if flush_global is true, also flush global entries (not |
1639 | implemented yet) */ | |
1640 | void tlb_flush(CPUState *env, int flush_global) | |
33417e70 | 1641 | { |
33417e70 | 1642 | int i; |
0124311e | 1643 | |
9fa3e853 FB |
1644 | #if defined(DEBUG_TLB) |
1645 | printf("tlb_flush:\n"); | |
1646 | #endif | |
0124311e FB |
1647 | /* must reset current TB so that interrupts cannot modify the |
1648 | links while we are modifying them */ | |
1649 | env->current_tb = NULL; | |
1650 | ||
33417e70 | 1651 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
84b7b8e7 FB |
1652 | env->tlb_table[0][i].addr_read = -1; |
1653 | env->tlb_table[0][i].addr_write = -1; | |
1654 | env->tlb_table[0][i].addr_code = -1; | |
1655 | env->tlb_table[1][i].addr_read = -1; | |
1656 | env->tlb_table[1][i].addr_write = -1; | |
1657 | env->tlb_table[1][i].addr_code = -1; | |
6fa4cea9 JM |
1658 | #if (NB_MMU_MODES >= 3) |
1659 | env->tlb_table[2][i].addr_read = -1; | |
1660 | env->tlb_table[2][i].addr_write = -1; | |
1661 | env->tlb_table[2][i].addr_code = -1; | |
1662 | #if (NB_MMU_MODES == 4) | |
1663 | env->tlb_table[3][i].addr_read = -1; | |
1664 | env->tlb_table[3][i].addr_write = -1; | |
1665 | env->tlb_table[3][i].addr_code = -1; | |
1666 | #endif | |
1667 | #endif | |
33417e70 | 1668 | } |
9fa3e853 | 1669 | |
8a40a180 | 1670 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
9fa3e853 | 1671 | |
0a962c02 FB |
1672 | #ifdef USE_KQEMU |
1673 | if (env->kqemu_enabled) { | |
1674 | kqemu_flush(env, flush_global); | |
1675 | } | |
9fa3e853 | 1676 | #endif |
e3db7226 | 1677 | tlb_flush_count++; |
33417e70 FB |
1678 | } |
1679 | ||
274da6b2 | 1680 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
61382a50 | 1681 | { |
5fafdf24 | 1682 | if (addr == (tlb_entry->addr_read & |
84b7b8e7 | 1683 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1684 | addr == (tlb_entry->addr_write & |
84b7b8e7 | 1685 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1686 | addr == (tlb_entry->addr_code & |
84b7b8e7 FB |
1687 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
1688 | tlb_entry->addr_read = -1; | |
1689 | tlb_entry->addr_write = -1; | |
1690 | tlb_entry->addr_code = -1; | |
1691 | } | |
61382a50 FB |
1692 | } |
1693 | ||
2e12669a | 1694 | void tlb_flush_page(CPUState *env, target_ulong addr) |
33417e70 | 1695 | { |
8a40a180 | 1696 | int i; |
0124311e | 1697 | |
9fa3e853 | 1698 | #if defined(DEBUG_TLB) |
108c49b8 | 1699 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
9fa3e853 | 1700 | #endif |
0124311e FB |
1701 | /* must reset current TB so that interrupts cannot modify the |
1702 | links while we are modifying them */ | |
1703 | env->current_tb = NULL; | |
61382a50 FB |
1704 | |
1705 | addr &= TARGET_PAGE_MASK; | |
1706 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
84b7b8e7 FB |
1707 | tlb_flush_entry(&env->tlb_table[0][i], addr); |
1708 | tlb_flush_entry(&env->tlb_table[1][i], addr); | |
6fa4cea9 JM |
1709 | #if (NB_MMU_MODES >= 3) |
1710 | tlb_flush_entry(&env->tlb_table[2][i], addr); | |
1711 | #if (NB_MMU_MODES == 4) | |
1712 | tlb_flush_entry(&env->tlb_table[3][i], addr); | |
1713 | #endif | |
1714 | #endif | |
0124311e | 1715 | |
5c751e99 | 1716 | tlb_flush_jmp_cache(env, addr); |
9fa3e853 | 1717 | |
0a962c02 FB |
1718 | #ifdef USE_KQEMU |
1719 | if (env->kqemu_enabled) { | |
1720 | kqemu_flush_page(env, addr); | |
1721 | } | |
1722 | #endif | |
9fa3e853 FB |
1723 | } |
1724 | ||
9fa3e853 FB |
1725 | /* update the TLBs so that writes to code in the virtual page 'addr' |
1726 | can be detected */ | |
6a00d601 | 1727 | static void tlb_protect_code(ram_addr_t ram_addr) |
9fa3e853 | 1728 | { |
5fafdf24 | 1729 | cpu_physical_memory_reset_dirty(ram_addr, |
6a00d601 FB |
1730 | ram_addr + TARGET_PAGE_SIZE, |
1731 | CODE_DIRTY_FLAG); | |
9fa3e853 FB |
1732 | } |
1733 | ||
9fa3e853 | 1734 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
3a7d929e | 1735 | tested for self modifying code */ |
5fafdf24 | 1736 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 1737 | target_ulong vaddr) |
9fa3e853 | 1738 | { |
3a7d929e | 1739 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG; |
1ccde1cb FB |
1740 | } |
1741 | ||
5fafdf24 | 1742 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
1ccde1cb FB |
1743 | unsigned long start, unsigned long length) |
1744 | { | |
1745 | unsigned long addr; | |
84b7b8e7 FB |
1746 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
1747 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; | |
1ccde1cb | 1748 | if ((addr - start) < length) { |
0f459d16 | 1749 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
1ccde1cb FB |
1750 | } |
1751 | } | |
1752 | } | |
1753 | ||
3a7d929e | 1754 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 1755 | int dirty_flags) |
1ccde1cb FB |
1756 | { |
1757 | CPUState *env; | |
4f2ac237 | 1758 | unsigned long length, start1; |
0a962c02 FB |
1759 | int i, mask, len; |
1760 | uint8_t *p; | |
1ccde1cb FB |
1761 | |
1762 | start &= TARGET_PAGE_MASK; | |
1763 | end = TARGET_PAGE_ALIGN(end); | |
1764 | ||
1765 | length = end - start; | |
1766 | if (length == 0) | |
1767 | return; | |
0a962c02 | 1768 | len = length >> TARGET_PAGE_BITS; |
3a7d929e | 1769 | #ifdef USE_KQEMU |
6a00d601 FB |
1770 | /* XXX: should not depend on cpu context */ |
1771 | env = first_cpu; | |
3a7d929e | 1772 | if (env->kqemu_enabled) { |
f23db169 FB |
1773 | ram_addr_t addr; |
1774 | addr = start; | |
1775 | for(i = 0; i < len; i++) { | |
1776 | kqemu_set_notdirty(env, addr); | |
1777 | addr += TARGET_PAGE_SIZE; | |
1778 | } | |
3a7d929e FB |
1779 | } |
1780 | #endif | |
f23db169 FB |
1781 | mask = ~dirty_flags; |
1782 | p = phys_ram_dirty + (start >> TARGET_PAGE_BITS); | |
1783 | for(i = 0; i < len; i++) | |
1784 | p[i] &= mask; | |
1785 | ||
1ccde1cb FB |
1786 | /* we modify the TLB cache so that the dirty bit will be set again |
1787 | when accessing the range */ | |
59817ccb | 1788 | start1 = start + (unsigned long)phys_ram_base; |
6a00d601 FB |
1789 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
1790 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
84b7b8e7 | 1791 | tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length); |
6a00d601 | 1792 | for(i = 0; i < CPU_TLB_SIZE; i++) |
84b7b8e7 | 1793 | tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length); |
6fa4cea9 JM |
1794 | #if (NB_MMU_MODES >= 3) |
1795 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1796 | tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length); | |
1797 | #if (NB_MMU_MODES == 4) | |
1798 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1799 | tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length); | |
1800 | #endif | |
1801 | #endif | |
6a00d601 | 1802 | } |
1ccde1cb FB |
1803 | } |
1804 | ||
74576198 AL |
1805 | int cpu_physical_memory_set_dirty_tracking(int enable) |
1806 | { | |
1807 | in_migration = enable; | |
1808 | return 0; | |
1809 | } | |
1810 | ||
1811 | int cpu_physical_memory_get_dirty_tracking(void) | |
1812 | { | |
1813 | return in_migration; | |
1814 | } | |
1815 | ||
3a7d929e FB |
1816 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
1817 | { | |
1818 | ram_addr_t ram_addr; | |
1819 | ||
84b7b8e7 | 1820 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
5fafdf24 | 1821 | ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + |
3a7d929e FB |
1822 | tlb_entry->addend - (unsigned long)phys_ram_base; |
1823 | if (!cpu_physical_memory_is_dirty(ram_addr)) { | |
0f459d16 | 1824 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
3a7d929e FB |
1825 | } |
1826 | } | |
1827 | } | |
1828 | ||
1829 | /* update the TLB according to the current state of the dirty bits */ | |
1830 | void cpu_tlb_update_dirty(CPUState *env) | |
1831 | { | |
1832 | int i; | |
1833 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
84b7b8e7 | 1834 | tlb_update_dirty(&env->tlb_table[0][i]); |
3a7d929e | 1835 | for(i = 0; i < CPU_TLB_SIZE; i++) |
84b7b8e7 | 1836 | tlb_update_dirty(&env->tlb_table[1][i]); |
6fa4cea9 JM |
1837 | #if (NB_MMU_MODES >= 3) |
1838 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1839 | tlb_update_dirty(&env->tlb_table[2][i]); | |
1840 | #if (NB_MMU_MODES == 4) | |
1841 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1842 | tlb_update_dirty(&env->tlb_table[3][i]); | |
1843 | #endif | |
1844 | #endif | |
3a7d929e FB |
1845 | } |
1846 | ||
0f459d16 | 1847 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
1ccde1cb | 1848 | { |
0f459d16 PB |
1849 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
1850 | tlb_entry->addr_write = vaddr; | |
1ccde1cb FB |
1851 | } |
1852 | ||
0f459d16 PB |
1853 | /* update the TLB corresponding to virtual page vaddr |
1854 | so that it is no longer dirty */ | |
1855 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) | |
1ccde1cb | 1856 | { |
1ccde1cb FB |
1857 | int i; |
1858 | ||
0f459d16 | 1859 | vaddr &= TARGET_PAGE_MASK; |
1ccde1cb | 1860 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
0f459d16 PB |
1861 | tlb_set_dirty1(&env->tlb_table[0][i], vaddr); |
1862 | tlb_set_dirty1(&env->tlb_table[1][i], vaddr); | |
6fa4cea9 | 1863 | #if (NB_MMU_MODES >= 3) |
0f459d16 | 1864 | tlb_set_dirty1(&env->tlb_table[2][i], vaddr); |
6fa4cea9 | 1865 | #if (NB_MMU_MODES == 4) |
0f459d16 | 1866 | tlb_set_dirty1(&env->tlb_table[3][i], vaddr); |
6fa4cea9 JM |
1867 | #endif |
1868 | #endif | |
9fa3e853 FB |
1869 | } |
1870 | ||
59817ccb FB |
1871 | /* add a new TLB entry. At most one entry for a given virtual address |
1872 | is permitted. Return 0 if OK or 2 if the page could not be mapped | |
1873 | (can only happen in non SOFTMMU mode for I/O pages or pages | |
1874 | conflicting with the host address space). */ | |
5fafdf24 TS |
1875 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
1876 | target_phys_addr_t paddr, int prot, | |
6ebbf390 | 1877 | int mmu_idx, int is_softmmu) |
9fa3e853 | 1878 | { |
92e873b9 | 1879 | PhysPageDesc *p; |
4f2ac237 | 1880 | unsigned long pd; |
9fa3e853 | 1881 | unsigned int index; |
4f2ac237 | 1882 | target_ulong address; |
0f459d16 | 1883 | target_ulong code_address; |
108c49b8 | 1884 | target_phys_addr_t addend; |
9fa3e853 | 1885 | int ret; |
84b7b8e7 | 1886 | CPUTLBEntry *te; |
6658ffb8 | 1887 | int i; |
0f459d16 | 1888 | target_phys_addr_t iotlb; |
9fa3e853 | 1889 | |
92e873b9 | 1890 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
1891 | if (!p) { |
1892 | pd = IO_MEM_UNASSIGNED; | |
9fa3e853 FB |
1893 | } else { |
1894 | pd = p->phys_offset; | |
9fa3e853 FB |
1895 | } |
1896 | #if defined(DEBUG_TLB) | |
6ebbf390 JM |
1897 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n", |
1898 | vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd); | |
9fa3e853 FB |
1899 | #endif |
1900 | ||
1901 | ret = 0; | |
0f459d16 PB |
1902 | address = vaddr; |
1903 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { | |
1904 | /* IO memory case (romd handled later) */ | |
1905 | address |= TLB_MMIO; | |
1906 | } | |
1907 | addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK); | |
1908 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { | |
1909 | /* Normal RAM. */ | |
1910 | iotlb = pd & TARGET_PAGE_MASK; | |
1911 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) | |
1912 | iotlb |= IO_MEM_NOTDIRTY; | |
1913 | else | |
1914 | iotlb |= IO_MEM_ROM; | |
1915 | } else { | |
1916 | /* IO handlers are currently passed a phsical address. | |
1917 | It would be nice to pass an offset from the base address | |
1918 | of that region. This would avoid having to special case RAM, | |
1919 | and avoid full address decoding in every device. | |
1920 | We can't use the high bits of pd for this because | |
1921 | IO_MEM_ROMD uses these as a ram address. */ | |
1922 | iotlb = (pd & ~TARGET_PAGE_MASK) + paddr; | |
1923 | } | |
1924 | ||
1925 | code_address = address; | |
1926 | /* Make accesses to pages with watchpoints go via the | |
1927 | watchpoint trap routines. */ | |
1928 | for (i = 0; i < env->nb_watchpoints; i++) { | |
1929 | if (vaddr == (env->watchpoint[i].vaddr & TARGET_PAGE_MASK)) { | |
1930 | iotlb = io_mem_watch + paddr; | |
1931 | /* TODO: The memory case can be optimized by not trapping | |
1932 | reads of pages with a write breakpoint. */ | |
1933 | address |= TLB_MMIO; | |
6658ffb8 | 1934 | } |
0f459d16 | 1935 | } |
d79acba4 | 1936 | |
0f459d16 PB |
1937 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
1938 | env->iotlb[mmu_idx][index] = iotlb - vaddr; | |
1939 | te = &env->tlb_table[mmu_idx][index]; | |
1940 | te->addend = addend - vaddr; | |
1941 | if (prot & PAGE_READ) { | |
1942 | te->addr_read = address; | |
1943 | } else { | |
1944 | te->addr_read = -1; | |
1945 | } | |
5c751e99 | 1946 | |
0f459d16 PB |
1947 | if (prot & PAGE_EXEC) { |
1948 | te->addr_code = code_address; | |
1949 | } else { | |
1950 | te->addr_code = -1; | |
1951 | } | |
1952 | if (prot & PAGE_WRITE) { | |
1953 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || | |
1954 | (pd & IO_MEM_ROMD)) { | |
1955 | /* Write access calls the I/O callback. */ | |
1956 | te->addr_write = address | TLB_MMIO; | |
1957 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && | |
1958 | !cpu_physical_memory_is_dirty(pd)) { | |
1959 | te->addr_write = address | TLB_NOTDIRTY; | |
9fa3e853 | 1960 | } else { |
0f459d16 | 1961 | te->addr_write = address; |
9fa3e853 | 1962 | } |
0f459d16 PB |
1963 | } else { |
1964 | te->addr_write = -1; | |
9fa3e853 | 1965 | } |
9fa3e853 FB |
1966 | return ret; |
1967 | } | |
1968 | ||
0124311e FB |
1969 | #else |
1970 | ||
ee8b7021 | 1971 | void tlb_flush(CPUState *env, int flush_global) |
0124311e FB |
1972 | { |
1973 | } | |
1974 | ||
2e12669a | 1975 | void tlb_flush_page(CPUState *env, target_ulong addr) |
0124311e FB |
1976 | { |
1977 | } | |
1978 | ||
5fafdf24 TS |
1979 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
1980 | target_phys_addr_t paddr, int prot, | |
6ebbf390 | 1981 | int mmu_idx, int is_softmmu) |
9fa3e853 FB |
1982 | { |
1983 | return 0; | |
1984 | } | |
0124311e | 1985 | |
9fa3e853 FB |
1986 | /* dump memory mappings */ |
1987 | void page_dump(FILE *f) | |
33417e70 | 1988 | { |
9fa3e853 FB |
1989 | unsigned long start, end; |
1990 | int i, j, prot, prot1; | |
1991 | PageDesc *p; | |
33417e70 | 1992 | |
9fa3e853 FB |
1993 | fprintf(f, "%-8s %-8s %-8s %s\n", |
1994 | "start", "end", "size", "prot"); | |
1995 | start = -1; | |
1996 | end = -1; | |
1997 | prot = 0; | |
1998 | for(i = 0; i <= L1_SIZE; i++) { | |
1999 | if (i < L1_SIZE) | |
2000 | p = l1_map[i]; | |
2001 | else | |
2002 | p = NULL; | |
2003 | for(j = 0;j < L2_SIZE; j++) { | |
2004 | if (!p) | |
2005 | prot1 = 0; | |
2006 | else | |
2007 | prot1 = p[j].flags; | |
2008 | if (prot1 != prot) { | |
2009 | end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS); | |
2010 | if (start != -1) { | |
2011 | fprintf(f, "%08lx-%08lx %08lx %c%c%c\n", | |
5fafdf24 | 2012 | start, end, end - start, |
9fa3e853 FB |
2013 | prot & PAGE_READ ? 'r' : '-', |
2014 | prot & PAGE_WRITE ? 'w' : '-', | |
2015 | prot & PAGE_EXEC ? 'x' : '-'); | |
2016 | } | |
2017 | if (prot1 != 0) | |
2018 | start = end; | |
2019 | else | |
2020 | start = -1; | |
2021 | prot = prot1; | |
2022 | } | |
2023 | if (!p) | |
2024 | break; | |
2025 | } | |
33417e70 | 2026 | } |
33417e70 FB |
2027 | } |
2028 | ||
53a5960a | 2029 | int page_get_flags(target_ulong address) |
33417e70 | 2030 | { |
9fa3e853 FB |
2031 | PageDesc *p; |
2032 | ||
2033 | p = page_find(address >> TARGET_PAGE_BITS); | |
33417e70 | 2034 | if (!p) |
9fa3e853 FB |
2035 | return 0; |
2036 | return p->flags; | |
2037 | } | |
2038 | ||
2039 | /* modify the flags of a page and invalidate the code if | |
2040 | necessary. The flag PAGE_WRITE_ORG is positionned automatically | |
2041 | depending on PAGE_WRITE */ | |
53a5960a | 2042 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
9fa3e853 FB |
2043 | { |
2044 | PageDesc *p; | |
53a5960a | 2045 | target_ulong addr; |
9fa3e853 | 2046 | |
c8a706fe | 2047 | /* mmap_lock should already be held. */ |
9fa3e853 FB |
2048 | start = start & TARGET_PAGE_MASK; |
2049 | end = TARGET_PAGE_ALIGN(end); | |
2050 | if (flags & PAGE_WRITE) | |
2051 | flags |= PAGE_WRITE_ORG; | |
9fa3e853 FB |
2052 | for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) { |
2053 | p = page_find_alloc(addr >> TARGET_PAGE_BITS); | |
17e2377a PB |
2054 | /* We may be called for host regions that are outside guest |
2055 | address space. */ | |
2056 | if (!p) | |
2057 | return; | |
9fa3e853 FB |
2058 | /* if the write protection is set, then we invalidate the code |
2059 | inside */ | |
5fafdf24 | 2060 | if (!(p->flags & PAGE_WRITE) && |
9fa3e853 FB |
2061 | (flags & PAGE_WRITE) && |
2062 | p->first_tb) { | |
d720b93d | 2063 | tb_invalidate_phys_page(addr, 0, NULL); |
9fa3e853 FB |
2064 | } |
2065 | p->flags = flags; | |
2066 | } | |
33417e70 FB |
2067 | } |
2068 | ||
3d97b40b TS |
2069 | int page_check_range(target_ulong start, target_ulong len, int flags) |
2070 | { | |
2071 | PageDesc *p; | |
2072 | target_ulong end; | |
2073 | target_ulong addr; | |
2074 | ||
55f280c9 AZ |
2075 | if (start + len < start) |
2076 | /* we've wrapped around */ | |
2077 | return -1; | |
2078 | ||
3d97b40b TS |
2079 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
2080 | start = start & TARGET_PAGE_MASK; | |
2081 | ||
3d97b40b TS |
2082 | for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) { |
2083 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2084 | if( !p ) | |
2085 | return -1; | |
2086 | if( !(p->flags & PAGE_VALID) ) | |
2087 | return -1; | |
2088 | ||
dae3270c | 2089 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
3d97b40b | 2090 | return -1; |
dae3270c FB |
2091 | if (flags & PAGE_WRITE) { |
2092 | if (!(p->flags & PAGE_WRITE_ORG)) | |
2093 | return -1; | |
2094 | /* unprotect the page if it was put read-only because it | |
2095 | contains translated code */ | |
2096 | if (!(p->flags & PAGE_WRITE)) { | |
2097 | if (!page_unprotect(addr, 0, NULL)) | |
2098 | return -1; | |
2099 | } | |
2100 | return 0; | |
2101 | } | |
3d97b40b TS |
2102 | } |
2103 | return 0; | |
2104 | } | |
2105 | ||
9fa3e853 FB |
2106 | /* called from signal handler: invalidate the code and unprotect the |
2107 | page. Return TRUE if the fault was succesfully handled. */ | |
53a5960a | 2108 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
9fa3e853 FB |
2109 | { |
2110 | unsigned int page_index, prot, pindex; | |
2111 | PageDesc *p, *p1; | |
53a5960a | 2112 | target_ulong host_start, host_end, addr; |
9fa3e853 | 2113 | |
c8a706fe PB |
2114 | /* Technically this isn't safe inside a signal handler. However we |
2115 | know this only ever happens in a synchronous SEGV handler, so in | |
2116 | practice it seems to be ok. */ | |
2117 | mmap_lock(); | |
2118 | ||
83fb7adf | 2119 | host_start = address & qemu_host_page_mask; |
9fa3e853 FB |
2120 | page_index = host_start >> TARGET_PAGE_BITS; |
2121 | p1 = page_find(page_index); | |
c8a706fe PB |
2122 | if (!p1) { |
2123 | mmap_unlock(); | |
9fa3e853 | 2124 | return 0; |
c8a706fe | 2125 | } |
83fb7adf | 2126 | host_end = host_start + qemu_host_page_size; |
9fa3e853 FB |
2127 | p = p1; |
2128 | prot = 0; | |
2129 | for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) { | |
2130 | prot |= p->flags; | |
2131 | p++; | |
2132 | } | |
2133 | /* if the page was really writable, then we change its | |
2134 | protection back to writable */ | |
2135 | if (prot & PAGE_WRITE_ORG) { | |
2136 | pindex = (address - host_start) >> TARGET_PAGE_BITS; | |
2137 | if (!(p1[pindex].flags & PAGE_WRITE)) { | |
5fafdf24 | 2138 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
9fa3e853 FB |
2139 | (prot & PAGE_BITS) | PAGE_WRITE); |
2140 | p1[pindex].flags |= PAGE_WRITE; | |
2141 | /* and since the content will be modified, we must invalidate | |
2142 | the corresponding translated code. */ | |
d720b93d | 2143 | tb_invalidate_phys_page(address, pc, puc); |
9fa3e853 FB |
2144 | #ifdef DEBUG_TB_CHECK |
2145 | tb_invalidate_check(address); | |
2146 | #endif | |
c8a706fe | 2147 | mmap_unlock(); |
9fa3e853 FB |
2148 | return 1; |
2149 | } | |
2150 | } | |
c8a706fe | 2151 | mmap_unlock(); |
9fa3e853 FB |
2152 | return 0; |
2153 | } | |
2154 | ||
6a00d601 FB |
2155 | static inline void tlb_set_dirty(CPUState *env, |
2156 | unsigned long addr, target_ulong vaddr) | |
1ccde1cb FB |
2157 | { |
2158 | } | |
9fa3e853 FB |
2159 | #endif /* defined(CONFIG_USER_ONLY) */ |
2160 | ||
e2eef170 | 2161 | #if !defined(CONFIG_USER_ONLY) |
db7b5426 | 2162 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
00f82b8a AJ |
2163 | ram_addr_t memory); |
2164 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, | |
2165 | ram_addr_t orig_memory); | |
db7b5426 BS |
2166 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
2167 | need_subpage) \ | |
2168 | do { \ | |
2169 | if (addr > start_addr) \ | |
2170 | start_addr2 = 0; \ | |
2171 | else { \ | |
2172 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ | |
2173 | if (start_addr2 > 0) \ | |
2174 | need_subpage = 1; \ | |
2175 | } \ | |
2176 | \ | |
49e9fba2 | 2177 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
db7b5426 BS |
2178 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
2179 | else { \ | |
2180 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ | |
2181 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ | |
2182 | need_subpage = 1; \ | |
2183 | } \ | |
2184 | } while (0) | |
2185 | ||
33417e70 FB |
2186 | /* register physical memory. 'size' must be a multiple of the target |
2187 | page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an | |
2188 | io memory page */ | |
5fafdf24 | 2189 | void cpu_register_physical_memory(target_phys_addr_t start_addr, |
00f82b8a AJ |
2190 | ram_addr_t size, |
2191 | ram_addr_t phys_offset) | |
33417e70 | 2192 | { |
108c49b8 | 2193 | target_phys_addr_t addr, end_addr; |
92e873b9 | 2194 | PhysPageDesc *p; |
9d42037b | 2195 | CPUState *env; |
00f82b8a | 2196 | ram_addr_t orig_size = size; |
db7b5426 | 2197 | void *subpage; |
33417e70 | 2198 | |
da260249 FB |
2199 | #ifdef USE_KQEMU |
2200 | /* XXX: should not depend on cpu context */ | |
2201 | env = first_cpu; | |
2202 | if (env->kqemu_enabled) { | |
2203 | kqemu_set_phys_mem(start_addr, size, phys_offset); | |
2204 | } | |
2205 | #endif | |
7ba1e619 AL |
2206 | if (kvm_enabled()) |
2207 | kvm_set_phys_mem(start_addr, size, phys_offset); | |
2208 | ||
5fd386f6 | 2209 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
49e9fba2 BS |
2210 | end_addr = start_addr + (target_phys_addr_t)size; |
2211 | for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) { | |
db7b5426 BS |
2212 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
2213 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { | |
00f82b8a | 2214 | ram_addr_t orig_memory = p->phys_offset; |
db7b5426 BS |
2215 | target_phys_addr_t start_addr2, end_addr2; |
2216 | int need_subpage = 0; | |
2217 | ||
2218 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, | |
2219 | need_subpage); | |
4254fab8 | 2220 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
db7b5426 BS |
2221 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
2222 | subpage = subpage_init((addr & TARGET_PAGE_MASK), | |
2223 | &p->phys_offset, orig_memory); | |
2224 | } else { | |
2225 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) | |
2226 | >> IO_MEM_SHIFT]; | |
2227 | } | |
2228 | subpage_register(subpage, start_addr2, end_addr2, phys_offset); | |
2229 | } else { | |
2230 | p->phys_offset = phys_offset; | |
2231 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2232 | (phys_offset & IO_MEM_ROMD)) | |
2233 | phys_offset += TARGET_PAGE_SIZE; | |
2234 | } | |
2235 | } else { | |
2236 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2237 | p->phys_offset = phys_offset; | |
2238 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2239 | (phys_offset & IO_MEM_ROMD)) | |
2240 | phys_offset += TARGET_PAGE_SIZE; | |
2241 | else { | |
2242 | target_phys_addr_t start_addr2, end_addr2; | |
2243 | int need_subpage = 0; | |
2244 | ||
2245 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, | |
2246 | end_addr2, need_subpage); | |
2247 | ||
4254fab8 | 2248 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
db7b5426 BS |
2249 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
2250 | &p->phys_offset, IO_MEM_UNASSIGNED); | |
2251 | subpage_register(subpage, start_addr2, end_addr2, | |
2252 | phys_offset); | |
2253 | } | |
2254 | } | |
2255 | } | |
33417e70 | 2256 | } |
3b46e624 | 2257 | |
9d42037b FB |
2258 | /* since each CPU stores ram addresses in its TLB cache, we must |
2259 | reset the modified entries */ | |
2260 | /* XXX: slow ! */ | |
2261 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
2262 | tlb_flush(env, 1); | |
2263 | } | |
33417e70 FB |
2264 | } |
2265 | ||
ba863458 | 2266 | /* XXX: temporary until new memory mapping API */ |
00f82b8a | 2267 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
ba863458 FB |
2268 | { |
2269 | PhysPageDesc *p; | |
2270 | ||
2271 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2272 | if (!p) | |
2273 | return IO_MEM_UNASSIGNED; | |
2274 | return p->phys_offset; | |
2275 | } | |
2276 | ||
e9a1ab19 | 2277 | /* XXX: better than nothing */ |
00f82b8a | 2278 | ram_addr_t qemu_ram_alloc(ram_addr_t size) |
e9a1ab19 FB |
2279 | { |
2280 | ram_addr_t addr; | |
7fb4fdcf | 2281 | if ((phys_ram_alloc_offset + size) > phys_ram_size) { |
012a7045 | 2282 | fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n", |
ed441467 | 2283 | (uint64_t)size, (uint64_t)phys_ram_size); |
e9a1ab19 FB |
2284 | abort(); |
2285 | } | |
2286 | addr = phys_ram_alloc_offset; | |
2287 | phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size); | |
2288 | return addr; | |
2289 | } | |
2290 | ||
2291 | void qemu_ram_free(ram_addr_t addr) | |
2292 | { | |
2293 | } | |
2294 | ||
a4193c8a | 2295 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
33417e70 | 2296 | { |
67d3b957 | 2297 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2298 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
b4f0a316 | 2299 | #endif |
e18231a3 BS |
2300 | #if defined(TARGET_SPARC) || defined(TARGET_CRIS) |
2301 | do_unassigned_access(addr, 0, 0, 0, 1); | |
2302 | #endif | |
2303 | return 0; | |
2304 | } | |
2305 | ||
2306 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) | |
2307 | { | |
2308 | #ifdef DEBUG_UNASSIGNED | |
2309 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2310 | #endif | |
2311 | #if defined(TARGET_SPARC) || defined(TARGET_CRIS) | |
2312 | do_unassigned_access(addr, 0, 0, 0, 2); | |
2313 | #endif | |
2314 | return 0; | |
2315 | } | |
2316 | ||
2317 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) | |
2318 | { | |
2319 | #ifdef DEBUG_UNASSIGNED | |
2320 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2321 | #endif | |
2322 | #if defined(TARGET_SPARC) || defined(TARGET_CRIS) | |
2323 | do_unassigned_access(addr, 0, 0, 0, 4); | |
67d3b957 | 2324 | #endif |
33417e70 FB |
2325 | return 0; |
2326 | } | |
2327 | ||
a4193c8a | 2328 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
33417e70 | 2329 | { |
67d3b957 | 2330 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2331 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
67d3b957 | 2332 | #endif |
e18231a3 BS |
2333 | #if defined(TARGET_SPARC) || defined(TARGET_CRIS) |
2334 | do_unassigned_access(addr, 1, 0, 0, 1); | |
2335 | #endif | |
2336 | } | |
2337 | ||
2338 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) | |
2339 | { | |
2340 | #ifdef DEBUG_UNASSIGNED | |
2341 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
2342 | #endif | |
2343 | #if defined(TARGET_SPARC) || defined(TARGET_CRIS) | |
2344 | do_unassigned_access(addr, 1, 0, 0, 2); | |
2345 | #endif | |
2346 | } | |
2347 | ||
2348 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
2349 | { | |
2350 | #ifdef DEBUG_UNASSIGNED | |
2351 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
2352 | #endif | |
2353 | #if defined(TARGET_SPARC) || defined(TARGET_CRIS) | |
2354 | do_unassigned_access(addr, 1, 0, 0, 4); | |
b4f0a316 | 2355 | #endif |
33417e70 FB |
2356 | } |
2357 | ||
2358 | static CPUReadMemoryFunc *unassigned_mem_read[3] = { | |
2359 | unassigned_mem_readb, | |
e18231a3 BS |
2360 | unassigned_mem_readw, |
2361 | unassigned_mem_readl, | |
33417e70 FB |
2362 | }; |
2363 | ||
2364 | static CPUWriteMemoryFunc *unassigned_mem_write[3] = { | |
2365 | unassigned_mem_writeb, | |
e18231a3 BS |
2366 | unassigned_mem_writew, |
2367 | unassigned_mem_writel, | |
33417e70 FB |
2368 | }; |
2369 | ||
0f459d16 PB |
2370 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
2371 | uint32_t val) | |
9fa3e853 | 2372 | { |
3a7d929e | 2373 | int dirty_flags; |
3a7d929e FB |
2374 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2375 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2376 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2377 | tb_invalidate_phys_page_fast(ram_addr, 1); |
2378 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2379 | #endif |
3a7d929e | 2380 | } |
0f459d16 | 2381 | stb_p(phys_ram_base + ram_addr, val); |
f32fc648 FB |
2382 | #ifdef USE_KQEMU |
2383 | if (cpu_single_env->kqemu_enabled && | |
2384 | (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) | |
2385 | kqemu_modify_page(cpu_single_env, ram_addr); | |
2386 | #endif | |
f23db169 FB |
2387 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2388 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2389 | /* we remove the notdirty callback only if the code has been | |
2390 | flushed */ | |
2391 | if (dirty_flags == 0xff) | |
2e70f6ef | 2392 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2393 | } |
2394 | ||
0f459d16 PB |
2395 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
2396 | uint32_t val) | |
9fa3e853 | 2397 | { |
3a7d929e | 2398 | int dirty_flags; |
3a7d929e FB |
2399 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2400 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2401 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2402 | tb_invalidate_phys_page_fast(ram_addr, 2); |
2403 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2404 | #endif |
3a7d929e | 2405 | } |
0f459d16 | 2406 | stw_p(phys_ram_base + ram_addr, val); |
f32fc648 FB |
2407 | #ifdef USE_KQEMU |
2408 | if (cpu_single_env->kqemu_enabled && | |
2409 | (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) | |
2410 | kqemu_modify_page(cpu_single_env, ram_addr); | |
2411 | #endif | |
f23db169 FB |
2412 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2413 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2414 | /* we remove the notdirty callback only if the code has been | |
2415 | flushed */ | |
2416 | if (dirty_flags == 0xff) | |
2e70f6ef | 2417 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2418 | } |
2419 | ||
0f459d16 PB |
2420 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
2421 | uint32_t val) | |
9fa3e853 | 2422 | { |
3a7d929e | 2423 | int dirty_flags; |
3a7d929e FB |
2424 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2425 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2426 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2427 | tb_invalidate_phys_page_fast(ram_addr, 4); |
2428 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2429 | #endif |
3a7d929e | 2430 | } |
0f459d16 | 2431 | stl_p(phys_ram_base + ram_addr, val); |
f32fc648 FB |
2432 | #ifdef USE_KQEMU |
2433 | if (cpu_single_env->kqemu_enabled && | |
2434 | (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) | |
2435 | kqemu_modify_page(cpu_single_env, ram_addr); | |
2436 | #endif | |
f23db169 FB |
2437 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2438 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2439 | /* we remove the notdirty callback only if the code has been | |
2440 | flushed */ | |
2441 | if (dirty_flags == 0xff) | |
2e70f6ef | 2442 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2443 | } |
2444 | ||
3a7d929e | 2445 | static CPUReadMemoryFunc *error_mem_read[3] = { |
9fa3e853 FB |
2446 | NULL, /* never used */ |
2447 | NULL, /* never used */ | |
2448 | NULL, /* never used */ | |
2449 | }; | |
2450 | ||
1ccde1cb FB |
2451 | static CPUWriteMemoryFunc *notdirty_mem_write[3] = { |
2452 | notdirty_mem_writeb, | |
2453 | notdirty_mem_writew, | |
2454 | notdirty_mem_writel, | |
2455 | }; | |
2456 | ||
0f459d16 PB |
2457 | /* Generate a debug exception if a watchpoint has been hit. */ |
2458 | static void check_watchpoint(int offset, int flags) | |
2459 | { | |
2460 | CPUState *env = cpu_single_env; | |
2461 | target_ulong vaddr; | |
2462 | int i; | |
2463 | ||
2e70f6ef | 2464 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
0f459d16 PB |
2465 | for (i = 0; i < env->nb_watchpoints; i++) { |
2466 | if (vaddr == env->watchpoint[i].vaddr | |
2467 | && (env->watchpoint[i].type & flags)) { | |
2468 | env->watchpoint_hit = i + 1; | |
2469 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); | |
2470 | break; | |
2471 | } | |
2472 | } | |
2473 | } | |
2474 | ||
6658ffb8 PB |
2475 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
2476 | so these check for a hit then pass through to the normal out-of-line | |
2477 | phys routines. */ | |
2478 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) | |
2479 | { | |
0f459d16 | 2480 | check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_READ); |
6658ffb8 PB |
2481 | return ldub_phys(addr); |
2482 | } | |
2483 | ||
2484 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) | |
2485 | { | |
0f459d16 | 2486 | check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_READ); |
6658ffb8 PB |
2487 | return lduw_phys(addr); |
2488 | } | |
2489 | ||
2490 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) | |
2491 | { | |
0f459d16 | 2492 | check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_READ); |
6658ffb8 PB |
2493 | return ldl_phys(addr); |
2494 | } | |
2495 | ||
6658ffb8 PB |
2496 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
2497 | uint32_t val) | |
2498 | { | |
0f459d16 | 2499 | check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_WRITE); |
6658ffb8 PB |
2500 | stb_phys(addr, val); |
2501 | } | |
2502 | ||
2503 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, | |
2504 | uint32_t val) | |
2505 | { | |
0f459d16 | 2506 | check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_WRITE); |
6658ffb8 PB |
2507 | stw_phys(addr, val); |
2508 | } | |
2509 | ||
2510 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, | |
2511 | uint32_t val) | |
2512 | { | |
0f459d16 | 2513 | check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_WRITE); |
6658ffb8 PB |
2514 | stl_phys(addr, val); |
2515 | } | |
2516 | ||
2517 | static CPUReadMemoryFunc *watch_mem_read[3] = { | |
2518 | watch_mem_readb, | |
2519 | watch_mem_readw, | |
2520 | watch_mem_readl, | |
2521 | }; | |
2522 | ||
2523 | static CPUWriteMemoryFunc *watch_mem_write[3] = { | |
2524 | watch_mem_writeb, | |
2525 | watch_mem_writew, | |
2526 | watch_mem_writel, | |
2527 | }; | |
6658ffb8 | 2528 | |
db7b5426 BS |
2529 | static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr, |
2530 | unsigned int len) | |
2531 | { | |
db7b5426 BS |
2532 | uint32_t ret; |
2533 | unsigned int idx; | |
2534 | ||
2535 | idx = SUBPAGE_IDX(addr - mmio->base); | |
2536 | #if defined(DEBUG_SUBPAGE) | |
2537 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, | |
2538 | mmio, len, addr, idx); | |
2539 | #endif | |
3ee89922 | 2540 | ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr); |
db7b5426 BS |
2541 | |
2542 | return ret; | |
2543 | } | |
2544 | ||
2545 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, | |
2546 | uint32_t value, unsigned int len) | |
2547 | { | |
db7b5426 BS |
2548 | unsigned int idx; |
2549 | ||
2550 | idx = SUBPAGE_IDX(addr - mmio->base); | |
2551 | #if defined(DEBUG_SUBPAGE) | |
2552 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__, | |
2553 | mmio, len, addr, idx, value); | |
2554 | #endif | |
3ee89922 | 2555 | (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value); |
db7b5426 BS |
2556 | } |
2557 | ||
2558 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) | |
2559 | { | |
2560 | #if defined(DEBUG_SUBPAGE) | |
2561 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2562 | #endif | |
2563 | ||
2564 | return subpage_readlen(opaque, addr, 0); | |
2565 | } | |
2566 | ||
2567 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, | |
2568 | uint32_t value) | |
2569 | { | |
2570 | #if defined(DEBUG_SUBPAGE) | |
2571 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2572 | #endif | |
2573 | subpage_writelen(opaque, addr, value, 0); | |
2574 | } | |
2575 | ||
2576 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) | |
2577 | { | |
2578 | #if defined(DEBUG_SUBPAGE) | |
2579 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2580 | #endif | |
2581 | ||
2582 | return subpage_readlen(opaque, addr, 1); | |
2583 | } | |
2584 | ||
2585 | static void subpage_writew (void *opaque, target_phys_addr_t addr, | |
2586 | uint32_t value) | |
2587 | { | |
2588 | #if defined(DEBUG_SUBPAGE) | |
2589 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2590 | #endif | |
2591 | subpage_writelen(opaque, addr, value, 1); | |
2592 | } | |
2593 | ||
2594 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) | |
2595 | { | |
2596 | #if defined(DEBUG_SUBPAGE) | |
2597 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2598 | #endif | |
2599 | ||
2600 | return subpage_readlen(opaque, addr, 2); | |
2601 | } | |
2602 | ||
2603 | static void subpage_writel (void *opaque, | |
2604 | target_phys_addr_t addr, uint32_t value) | |
2605 | { | |
2606 | #if defined(DEBUG_SUBPAGE) | |
2607 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2608 | #endif | |
2609 | subpage_writelen(opaque, addr, value, 2); | |
2610 | } | |
2611 | ||
2612 | static CPUReadMemoryFunc *subpage_read[] = { | |
2613 | &subpage_readb, | |
2614 | &subpage_readw, | |
2615 | &subpage_readl, | |
2616 | }; | |
2617 | ||
2618 | static CPUWriteMemoryFunc *subpage_write[] = { | |
2619 | &subpage_writeb, | |
2620 | &subpage_writew, | |
2621 | &subpage_writel, | |
2622 | }; | |
2623 | ||
2624 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, | |
00f82b8a | 2625 | ram_addr_t memory) |
db7b5426 BS |
2626 | { |
2627 | int idx, eidx; | |
4254fab8 | 2628 | unsigned int i; |
db7b5426 BS |
2629 | |
2630 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2631 | return -1; | |
2632 | idx = SUBPAGE_IDX(start); | |
2633 | eidx = SUBPAGE_IDX(end); | |
2634 | #if defined(DEBUG_SUBPAGE) | |
2635 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__, | |
2636 | mmio, start, end, idx, eidx, memory); | |
2637 | #endif | |
2638 | memory >>= IO_MEM_SHIFT; | |
2639 | for (; idx <= eidx; idx++) { | |
4254fab8 | 2640 | for (i = 0; i < 4; i++) { |
3ee89922 BS |
2641 | if (io_mem_read[memory][i]) { |
2642 | mmio->mem_read[idx][i] = &io_mem_read[memory][i]; | |
2643 | mmio->opaque[idx][0][i] = io_mem_opaque[memory]; | |
2644 | } | |
2645 | if (io_mem_write[memory][i]) { | |
2646 | mmio->mem_write[idx][i] = &io_mem_write[memory][i]; | |
2647 | mmio->opaque[idx][1][i] = io_mem_opaque[memory]; | |
2648 | } | |
4254fab8 | 2649 | } |
db7b5426 BS |
2650 | } |
2651 | ||
2652 | return 0; | |
2653 | } | |
2654 | ||
00f82b8a AJ |
2655 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
2656 | ram_addr_t orig_memory) | |
db7b5426 BS |
2657 | { |
2658 | subpage_t *mmio; | |
2659 | int subpage_memory; | |
2660 | ||
2661 | mmio = qemu_mallocz(sizeof(subpage_t)); | |
2662 | if (mmio != NULL) { | |
2663 | mmio->base = base; | |
2664 | subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio); | |
2665 | #if defined(DEBUG_SUBPAGE) | |
2666 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, | |
2667 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
2668 | #endif | |
2669 | *phys = subpage_memory | IO_MEM_SUBPAGE; | |
2670 | subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory); | |
2671 | } | |
2672 | ||
2673 | return mmio; | |
2674 | } | |
2675 | ||
33417e70 FB |
2676 | static void io_mem_init(void) |
2677 | { | |
3a7d929e | 2678 | cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL); |
a4193c8a | 2679 | cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL); |
3a7d929e | 2680 | cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL); |
1ccde1cb FB |
2681 | io_mem_nb = 5; |
2682 | ||
0f459d16 | 2683 | io_mem_watch = cpu_register_io_memory(0, watch_mem_read, |
6658ffb8 | 2684 | watch_mem_write, NULL); |
1ccde1cb | 2685 | /* alloc dirty bits array */ |
0a962c02 | 2686 | phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS); |
3a7d929e | 2687 | memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS); |
33417e70 FB |
2688 | } |
2689 | ||
2690 | /* mem_read and mem_write are arrays of functions containing the | |
2691 | function to access byte (index 0), word (index 1) and dword (index | |
3ee89922 BS |
2692 | 2). Functions can be omitted with a NULL function pointer. The |
2693 | registered functions may be modified dynamically later. | |
2694 | If io_index is non zero, the corresponding io zone is | |
4254fab8 BS |
2695 | modified. If it is zero, a new io zone is allocated. The return |
2696 | value can be used with cpu_register_physical_memory(). (-1) is | |
2697 | returned if error. */ | |
33417e70 FB |
2698 | int cpu_register_io_memory(int io_index, |
2699 | CPUReadMemoryFunc **mem_read, | |
a4193c8a FB |
2700 | CPUWriteMemoryFunc **mem_write, |
2701 | void *opaque) | |
33417e70 | 2702 | { |
4254fab8 | 2703 | int i, subwidth = 0; |
33417e70 FB |
2704 | |
2705 | if (io_index <= 0) { | |
b5ff1b31 | 2706 | if (io_mem_nb >= IO_MEM_NB_ENTRIES) |
33417e70 FB |
2707 | return -1; |
2708 | io_index = io_mem_nb++; | |
2709 | } else { | |
2710 | if (io_index >= IO_MEM_NB_ENTRIES) | |
2711 | return -1; | |
2712 | } | |
b5ff1b31 | 2713 | |
33417e70 | 2714 | for(i = 0;i < 3; i++) { |
4254fab8 BS |
2715 | if (!mem_read[i] || !mem_write[i]) |
2716 | subwidth = IO_MEM_SUBWIDTH; | |
33417e70 FB |
2717 | io_mem_read[io_index][i] = mem_read[i]; |
2718 | io_mem_write[io_index][i] = mem_write[i]; | |
2719 | } | |
a4193c8a | 2720 | io_mem_opaque[io_index] = opaque; |
4254fab8 | 2721 | return (io_index << IO_MEM_SHIFT) | subwidth; |
33417e70 | 2722 | } |
61382a50 | 2723 | |
8926b517 FB |
2724 | CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index) |
2725 | { | |
2726 | return io_mem_write[io_index >> IO_MEM_SHIFT]; | |
2727 | } | |
2728 | ||
2729 | CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index) | |
2730 | { | |
2731 | return io_mem_read[io_index >> IO_MEM_SHIFT]; | |
2732 | } | |
2733 | ||
e2eef170 PB |
2734 | #endif /* !defined(CONFIG_USER_ONLY) */ |
2735 | ||
13eb76e0 FB |
2736 | /* physical memory access (slow version, mainly for debug) */ |
2737 | #if defined(CONFIG_USER_ONLY) | |
5fafdf24 | 2738 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
2739 | int len, int is_write) |
2740 | { | |
2741 | int l, flags; | |
2742 | target_ulong page; | |
53a5960a | 2743 | void * p; |
13eb76e0 FB |
2744 | |
2745 | while (len > 0) { | |
2746 | page = addr & TARGET_PAGE_MASK; | |
2747 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2748 | if (l > len) | |
2749 | l = len; | |
2750 | flags = page_get_flags(page); | |
2751 | if (!(flags & PAGE_VALID)) | |
2752 | return; | |
2753 | if (is_write) { | |
2754 | if (!(flags & PAGE_WRITE)) | |
2755 | return; | |
579a97f7 | 2756 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 2757 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
579a97f7 FB |
2758 | /* FIXME - should this return an error rather than just fail? */ |
2759 | return; | |
72fb7daa AJ |
2760 | memcpy(p, buf, l); |
2761 | unlock_user(p, addr, l); | |
13eb76e0 FB |
2762 | } else { |
2763 | if (!(flags & PAGE_READ)) | |
2764 | return; | |
579a97f7 | 2765 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 2766 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
579a97f7 FB |
2767 | /* FIXME - should this return an error rather than just fail? */ |
2768 | return; | |
72fb7daa | 2769 | memcpy(buf, p, l); |
5b257578 | 2770 | unlock_user(p, addr, 0); |
13eb76e0 FB |
2771 | } |
2772 | len -= l; | |
2773 | buf += l; | |
2774 | addr += l; | |
2775 | } | |
2776 | } | |
8df1cd07 | 2777 | |
13eb76e0 | 2778 | #else |
5fafdf24 | 2779 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
2780 | int len, int is_write) |
2781 | { | |
2782 | int l, io_index; | |
2783 | uint8_t *ptr; | |
2784 | uint32_t val; | |
2e12669a FB |
2785 | target_phys_addr_t page; |
2786 | unsigned long pd; | |
92e873b9 | 2787 | PhysPageDesc *p; |
3b46e624 | 2788 | |
13eb76e0 FB |
2789 | while (len > 0) { |
2790 | page = addr & TARGET_PAGE_MASK; | |
2791 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2792 | if (l > len) | |
2793 | l = len; | |
92e873b9 | 2794 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
13eb76e0 FB |
2795 | if (!p) { |
2796 | pd = IO_MEM_UNASSIGNED; | |
2797 | } else { | |
2798 | pd = p->phys_offset; | |
2799 | } | |
3b46e624 | 2800 | |
13eb76e0 | 2801 | if (is_write) { |
3a7d929e | 2802 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
13eb76e0 | 2803 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
6a00d601 FB |
2804 | /* XXX: could force cpu_single_env to NULL to avoid |
2805 | potential bugs */ | |
13eb76e0 | 2806 | if (l >= 4 && ((addr & 3) == 0)) { |
1c213d19 | 2807 | /* 32 bit write access */ |
c27004ec | 2808 | val = ldl_p(buf); |
a4193c8a | 2809 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
13eb76e0 FB |
2810 | l = 4; |
2811 | } else if (l >= 2 && ((addr & 1) == 0)) { | |
1c213d19 | 2812 | /* 16 bit write access */ |
c27004ec | 2813 | val = lduw_p(buf); |
a4193c8a | 2814 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val); |
13eb76e0 FB |
2815 | l = 2; |
2816 | } else { | |
1c213d19 | 2817 | /* 8 bit write access */ |
c27004ec | 2818 | val = ldub_p(buf); |
a4193c8a | 2819 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val); |
13eb76e0 FB |
2820 | l = 1; |
2821 | } | |
2822 | } else { | |
b448f2f3 FB |
2823 | unsigned long addr1; |
2824 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
13eb76e0 | 2825 | /* RAM case */ |
b448f2f3 | 2826 | ptr = phys_ram_base + addr1; |
13eb76e0 | 2827 | memcpy(ptr, buf, l); |
3a7d929e FB |
2828 | if (!cpu_physical_memory_is_dirty(addr1)) { |
2829 | /* invalidate code */ | |
2830 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
2831 | /* set dirty bit */ | |
5fafdf24 | 2832 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
f23db169 | 2833 | (0xff & ~CODE_DIRTY_FLAG); |
3a7d929e | 2834 | } |
13eb76e0 FB |
2835 | } |
2836 | } else { | |
5fafdf24 | 2837 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 2838 | !(pd & IO_MEM_ROMD)) { |
13eb76e0 FB |
2839 | /* I/O case */ |
2840 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
2841 | if (l >= 4 && ((addr & 3) == 0)) { | |
2842 | /* 32 bit read access */ | |
a4193c8a | 2843 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
c27004ec | 2844 | stl_p(buf, val); |
13eb76e0 FB |
2845 | l = 4; |
2846 | } else if (l >= 2 && ((addr & 1) == 0)) { | |
2847 | /* 16 bit read access */ | |
a4193c8a | 2848 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr); |
c27004ec | 2849 | stw_p(buf, val); |
13eb76e0 FB |
2850 | l = 2; |
2851 | } else { | |
1c213d19 | 2852 | /* 8 bit read access */ |
a4193c8a | 2853 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr); |
c27004ec | 2854 | stb_p(buf, val); |
13eb76e0 FB |
2855 | l = 1; |
2856 | } | |
2857 | } else { | |
2858 | /* RAM case */ | |
5fafdf24 | 2859 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
13eb76e0 FB |
2860 | (addr & ~TARGET_PAGE_MASK); |
2861 | memcpy(buf, ptr, l); | |
2862 | } | |
2863 | } | |
2864 | len -= l; | |
2865 | buf += l; | |
2866 | addr += l; | |
2867 | } | |
2868 | } | |
8df1cd07 | 2869 | |
d0ecd2aa | 2870 | /* used for ROM loading : can write in RAM and ROM */ |
5fafdf24 | 2871 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
d0ecd2aa FB |
2872 | const uint8_t *buf, int len) |
2873 | { | |
2874 | int l; | |
2875 | uint8_t *ptr; | |
2876 | target_phys_addr_t page; | |
2877 | unsigned long pd; | |
2878 | PhysPageDesc *p; | |
3b46e624 | 2879 | |
d0ecd2aa FB |
2880 | while (len > 0) { |
2881 | page = addr & TARGET_PAGE_MASK; | |
2882 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2883 | if (l > len) | |
2884 | l = len; | |
2885 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
2886 | if (!p) { | |
2887 | pd = IO_MEM_UNASSIGNED; | |
2888 | } else { | |
2889 | pd = p->phys_offset; | |
2890 | } | |
3b46e624 | 2891 | |
d0ecd2aa | 2892 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
2a4188a3 FB |
2893 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
2894 | !(pd & IO_MEM_ROMD)) { | |
d0ecd2aa FB |
2895 | /* do nothing */ |
2896 | } else { | |
2897 | unsigned long addr1; | |
2898 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
2899 | /* ROM/RAM case */ | |
2900 | ptr = phys_ram_base + addr1; | |
2901 | memcpy(ptr, buf, l); | |
2902 | } | |
2903 | len -= l; | |
2904 | buf += l; | |
2905 | addr += l; | |
2906 | } | |
2907 | } | |
2908 | ||
2909 | ||
8df1cd07 FB |
2910 | /* warning: addr must be aligned */ |
2911 | uint32_t ldl_phys(target_phys_addr_t addr) | |
2912 | { | |
2913 | int io_index; | |
2914 | uint8_t *ptr; | |
2915 | uint32_t val; | |
2916 | unsigned long pd; | |
2917 | PhysPageDesc *p; | |
2918 | ||
2919 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2920 | if (!p) { | |
2921 | pd = IO_MEM_UNASSIGNED; | |
2922 | } else { | |
2923 | pd = p->phys_offset; | |
2924 | } | |
3b46e624 | 2925 | |
5fafdf24 | 2926 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 2927 | !(pd & IO_MEM_ROMD)) { |
8df1cd07 FB |
2928 | /* I/O case */ |
2929 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
2930 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
2931 | } else { | |
2932 | /* RAM case */ | |
5fafdf24 | 2933 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
8df1cd07 FB |
2934 | (addr & ~TARGET_PAGE_MASK); |
2935 | val = ldl_p(ptr); | |
2936 | } | |
2937 | return val; | |
2938 | } | |
2939 | ||
84b7b8e7 FB |
2940 | /* warning: addr must be aligned */ |
2941 | uint64_t ldq_phys(target_phys_addr_t addr) | |
2942 | { | |
2943 | int io_index; | |
2944 | uint8_t *ptr; | |
2945 | uint64_t val; | |
2946 | unsigned long pd; | |
2947 | PhysPageDesc *p; | |
2948 | ||
2949 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2950 | if (!p) { | |
2951 | pd = IO_MEM_UNASSIGNED; | |
2952 | } else { | |
2953 | pd = p->phys_offset; | |
2954 | } | |
3b46e624 | 2955 | |
2a4188a3 FB |
2956 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2957 | !(pd & IO_MEM_ROMD)) { | |
84b7b8e7 FB |
2958 | /* I/O case */ |
2959 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
2960 | #ifdef TARGET_WORDS_BIGENDIAN | |
2961 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; | |
2962 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); | |
2963 | #else | |
2964 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
2965 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; | |
2966 | #endif | |
2967 | } else { | |
2968 | /* RAM case */ | |
5fafdf24 | 2969 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
84b7b8e7 FB |
2970 | (addr & ~TARGET_PAGE_MASK); |
2971 | val = ldq_p(ptr); | |
2972 | } | |
2973 | return val; | |
2974 | } | |
2975 | ||
aab33094 FB |
2976 | /* XXX: optimize */ |
2977 | uint32_t ldub_phys(target_phys_addr_t addr) | |
2978 | { | |
2979 | uint8_t val; | |
2980 | cpu_physical_memory_read(addr, &val, 1); | |
2981 | return val; | |
2982 | } | |
2983 | ||
2984 | /* XXX: optimize */ | |
2985 | uint32_t lduw_phys(target_phys_addr_t addr) | |
2986 | { | |
2987 | uint16_t val; | |
2988 | cpu_physical_memory_read(addr, (uint8_t *)&val, 2); | |
2989 | return tswap16(val); | |
2990 | } | |
2991 | ||
8df1cd07 FB |
2992 | /* warning: addr must be aligned. The ram page is not masked as dirty |
2993 | and the code inside is not invalidated. It is useful if the dirty | |
2994 | bits are used to track modified PTEs */ | |
2995 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) | |
2996 | { | |
2997 | int io_index; | |
2998 | uint8_t *ptr; | |
2999 | unsigned long pd; | |
3000 | PhysPageDesc *p; | |
3001 | ||
3002 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3003 | if (!p) { | |
3004 | pd = IO_MEM_UNASSIGNED; | |
3005 | } else { | |
3006 | pd = p->phys_offset; | |
3007 | } | |
3b46e624 | 3008 | |
3a7d929e | 3009 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 FB |
3010 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
3011 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
3012 | } else { | |
74576198 AL |
3013 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
3014 | ptr = phys_ram_base + addr1; | |
8df1cd07 | 3015 | stl_p(ptr, val); |
74576198 AL |
3016 | |
3017 | if (unlikely(in_migration)) { | |
3018 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3019 | /* invalidate code */ | |
3020 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3021 | /* set dirty bit */ | |
3022 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= | |
3023 | (0xff & ~CODE_DIRTY_FLAG); | |
3024 | } | |
3025 | } | |
8df1cd07 FB |
3026 | } |
3027 | } | |
3028 | ||
bc98a7ef JM |
3029 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
3030 | { | |
3031 | int io_index; | |
3032 | uint8_t *ptr; | |
3033 | unsigned long pd; | |
3034 | PhysPageDesc *p; | |
3035 | ||
3036 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3037 | if (!p) { | |
3038 | pd = IO_MEM_UNASSIGNED; | |
3039 | } else { | |
3040 | pd = p->phys_offset; | |
3041 | } | |
3b46e624 | 3042 | |
bc98a7ef JM |
3043 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
3044 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
3045 | #ifdef TARGET_WORDS_BIGENDIAN | |
3046 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); | |
3047 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); | |
3048 | #else | |
3049 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
3050 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); | |
3051 | #endif | |
3052 | } else { | |
5fafdf24 | 3053 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
bc98a7ef JM |
3054 | (addr & ~TARGET_PAGE_MASK); |
3055 | stq_p(ptr, val); | |
3056 | } | |
3057 | } | |
3058 | ||
8df1cd07 | 3059 | /* warning: addr must be aligned */ |
8df1cd07 FB |
3060 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
3061 | { | |
3062 | int io_index; | |
3063 | uint8_t *ptr; | |
3064 | unsigned long pd; | |
3065 | PhysPageDesc *p; | |
3066 | ||
3067 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3068 | if (!p) { | |
3069 | pd = IO_MEM_UNASSIGNED; | |
3070 | } else { | |
3071 | pd = p->phys_offset; | |
3072 | } | |
3b46e624 | 3073 | |
3a7d929e | 3074 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 FB |
3075 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
3076 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
3077 | } else { | |
3078 | unsigned long addr1; | |
3079 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3080 | /* RAM case */ | |
3081 | ptr = phys_ram_base + addr1; | |
3082 | stl_p(ptr, val); | |
3a7d929e FB |
3083 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3084 | /* invalidate code */ | |
3085 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3086 | /* set dirty bit */ | |
f23db169 FB |
3087 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
3088 | (0xff & ~CODE_DIRTY_FLAG); | |
3a7d929e | 3089 | } |
8df1cd07 FB |
3090 | } |
3091 | } | |
3092 | ||
aab33094 FB |
3093 | /* XXX: optimize */ |
3094 | void stb_phys(target_phys_addr_t addr, uint32_t val) | |
3095 | { | |
3096 | uint8_t v = val; | |
3097 | cpu_physical_memory_write(addr, &v, 1); | |
3098 | } | |
3099 | ||
3100 | /* XXX: optimize */ | |
3101 | void stw_phys(target_phys_addr_t addr, uint32_t val) | |
3102 | { | |
3103 | uint16_t v = tswap16(val); | |
3104 | cpu_physical_memory_write(addr, (const uint8_t *)&v, 2); | |
3105 | } | |
3106 | ||
3107 | /* XXX: optimize */ | |
3108 | void stq_phys(target_phys_addr_t addr, uint64_t val) | |
3109 | { | |
3110 | val = tswap64(val); | |
3111 | cpu_physical_memory_write(addr, (const uint8_t *)&val, 8); | |
3112 | } | |
3113 | ||
13eb76e0 FB |
3114 | #endif |
3115 | ||
3116 | /* virtual memory access for debug */ | |
5fafdf24 | 3117 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
b448f2f3 | 3118 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
3119 | { |
3120 | int l; | |
9b3c35e0 JM |
3121 | target_phys_addr_t phys_addr; |
3122 | target_ulong page; | |
13eb76e0 FB |
3123 | |
3124 | while (len > 0) { | |
3125 | page = addr & TARGET_PAGE_MASK; | |
3126 | phys_addr = cpu_get_phys_page_debug(env, page); | |
3127 | /* if no physical page mapped, return an error */ | |
3128 | if (phys_addr == -1) | |
3129 | return -1; | |
3130 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3131 | if (l > len) | |
3132 | l = len; | |
5fafdf24 | 3133 | cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK), |
b448f2f3 | 3134 | buf, l, is_write); |
13eb76e0 FB |
3135 | len -= l; |
3136 | buf += l; | |
3137 | addr += l; | |
3138 | } | |
3139 | return 0; | |
3140 | } | |
3141 | ||
2e70f6ef PB |
3142 | /* in deterministic execution mode, instructions doing device I/Os |
3143 | must be at the end of the TB */ | |
3144 | void cpu_io_recompile(CPUState *env, void *retaddr) | |
3145 | { | |
3146 | TranslationBlock *tb; | |
3147 | uint32_t n, cflags; | |
3148 | target_ulong pc, cs_base; | |
3149 | uint64_t flags; | |
3150 | ||
3151 | tb = tb_find_pc((unsigned long)retaddr); | |
3152 | if (!tb) { | |
3153 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", | |
3154 | retaddr); | |
3155 | } | |
3156 | n = env->icount_decr.u16.low + tb->icount; | |
3157 | cpu_restore_state(tb, env, (unsigned long)retaddr, NULL); | |
3158 | /* Calculate how many instructions had been executed before the fault | |
bf20dc07 | 3159 | occurred. */ |
2e70f6ef PB |
3160 | n = n - env->icount_decr.u16.low; |
3161 | /* Generate a new TB ending on the I/O insn. */ | |
3162 | n++; | |
3163 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
3164 | they were already the first instruction in the TB. If this is not | |
bf20dc07 | 3165 | the first instruction in a TB then re-execute the preceding |
2e70f6ef PB |
3166 | branch. */ |
3167 | #if defined(TARGET_MIPS) | |
3168 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
3169 | env->active_tc.PC -= 4; | |
3170 | env->icount_decr.u16.low++; | |
3171 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
3172 | } | |
3173 | #elif defined(TARGET_SH4) | |
3174 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
3175 | && n > 1) { | |
3176 | env->pc -= 2; | |
3177 | env->icount_decr.u16.low++; | |
3178 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
3179 | } | |
3180 | #endif | |
3181 | /* This should never happen. */ | |
3182 | if (n > CF_COUNT_MASK) | |
3183 | cpu_abort(env, "TB too big during recompile"); | |
3184 | ||
3185 | cflags = n | CF_LAST_IO; | |
3186 | pc = tb->pc; | |
3187 | cs_base = tb->cs_base; | |
3188 | flags = tb->flags; | |
3189 | tb_phys_invalidate(tb, -1); | |
3190 | /* FIXME: In theory this could raise an exception. In practice | |
3191 | we have already translated the block once so it's probably ok. */ | |
3192 | tb_gen_code(env, pc, cs_base, flags, cflags); | |
bf20dc07 | 3193 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
2e70f6ef PB |
3194 | the first in the TB) then we end up generating a whole new TB and |
3195 | repeating the fault, which is horribly inefficient. | |
3196 | Better would be to execute just this insn uncached, or generate a | |
3197 | second new TB. */ | |
3198 | cpu_resume_from_signal(env, NULL); | |
3199 | } | |
3200 | ||
e3db7226 FB |
3201 | void dump_exec_info(FILE *f, |
3202 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
3203 | { | |
3204 | int i, target_code_size, max_target_code_size; | |
3205 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
3206 | TranslationBlock *tb; | |
3b46e624 | 3207 | |
e3db7226 FB |
3208 | target_code_size = 0; |
3209 | max_target_code_size = 0; | |
3210 | cross_page = 0; | |
3211 | direct_jmp_count = 0; | |
3212 | direct_jmp2_count = 0; | |
3213 | for(i = 0; i < nb_tbs; i++) { | |
3214 | tb = &tbs[i]; | |
3215 | target_code_size += tb->size; | |
3216 | if (tb->size > max_target_code_size) | |
3217 | max_target_code_size = tb->size; | |
3218 | if (tb->page_addr[1] != -1) | |
3219 | cross_page++; | |
3220 | if (tb->tb_next_offset[0] != 0xffff) { | |
3221 | direct_jmp_count++; | |
3222 | if (tb->tb_next_offset[1] != 0xffff) { | |
3223 | direct_jmp2_count++; | |
3224 | } | |
3225 | } | |
3226 | } | |
3227 | /* XXX: avoid using doubles ? */ | |
57fec1fe | 3228 | cpu_fprintf(f, "Translation buffer state:\n"); |
26a5f13b FB |
3229 | cpu_fprintf(f, "gen code size %ld/%ld\n", |
3230 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); | |
3231 | cpu_fprintf(f, "TB count %d/%d\n", | |
3232 | nb_tbs, code_gen_max_blocks); | |
5fafdf24 | 3233 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
e3db7226 FB |
3234 | nb_tbs ? target_code_size / nb_tbs : 0, |
3235 | max_target_code_size); | |
5fafdf24 | 3236 | cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n", |
e3db7226 FB |
3237 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
3238 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); | |
5fafdf24 TS |
3239 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
3240 | cross_page, | |
e3db7226 FB |
3241 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
3242 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
5fafdf24 | 3243 | direct_jmp_count, |
e3db7226 FB |
3244 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
3245 | direct_jmp2_count, | |
3246 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
57fec1fe | 3247 | cpu_fprintf(f, "\nStatistics:\n"); |
e3db7226 FB |
3248 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
3249 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
3250 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
b67d9a52 | 3251 | tcg_dump_info(f, cpu_fprintf); |
e3db7226 FB |
3252 | } |
3253 | ||
5fafdf24 | 3254 | #if !defined(CONFIG_USER_ONLY) |
61382a50 FB |
3255 | |
3256 | #define MMUSUFFIX _cmmu | |
3257 | #define GETPC() NULL | |
3258 | #define env cpu_single_env | |
b769d8fe | 3259 | #define SOFTMMU_CODE_ACCESS |
61382a50 FB |
3260 | |
3261 | #define SHIFT 0 | |
3262 | #include "softmmu_template.h" | |
3263 | ||
3264 | #define SHIFT 1 | |
3265 | #include "softmmu_template.h" | |
3266 | ||
3267 | #define SHIFT 2 | |
3268 | #include "softmmu_template.h" | |
3269 | ||
3270 | #define SHIFT 3 | |
3271 | #include "softmmu_template.h" | |
3272 | ||
3273 | #undef env | |
3274 | ||
3275 | #endif |