[mirror_qemu.git] / hw / arm / armv7m.c

/*
 * ARMV7M System emulation.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/arm/armv7m.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/loader.h"
#include "hw/qdev-properties.h"
#include "elf.h"
#include "sysemu/qtest.h"
#include "sysemu/reset.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "exec/address-spaces.h"
#include "target/arm/idau.h"

/* Bitbanded IO.  Each word corresponds to a single bit.  */

/* Get the byte address of the real memory for a bitband access.  */
static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
{
    return s->base | (offset & 0x1ffffff) >> 5;
}

static MemTxResult bitband_read(void *opaque, hwaddr offset,
                                uint64_t *data, unsigned size, MemTxAttrs attrs)
{
    BitBandState *s = opaque;
    uint8_t buf[4];
    MemTxResult res;
    int bitpos, bit;
    hwaddr addr;

    assert(size <= 4);

    /* Find address in underlying memory and round down to multiple of size */
    addr = bitband_addr(s, offset) & (-size);
    res = address_space_read(&s->source_as, addr, attrs, buf, size);
    if (res) {
        return res;
    }
    /* Bit position in the N bytes read... */
    bitpos = (offset >> 2) & ((size * 8) - 1);
    /* ...converted to byte in buffer and bit in byte */
    bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
    *data = bit;
    return MEMTX_OK;
}

static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
                                 unsigned size, MemTxAttrs attrs)
{
    BitBandState *s = opaque;
    uint8_t buf[4];
    MemTxResult res;
    int bitpos, bit;
    hwaddr addr;

    assert(size <= 4);

    /* Find address in underlying memory and round down to multiple of size */
    addr = bitband_addr(s, offset) & (-size);
    res = address_space_read(&s->source_as, addr, attrs, buf, size);
    if (res) {
        return res;
    }
    /* Bit position in the N bytes read... */
    bitpos = (offset >> 2) & ((size * 8) - 1);
    /* ...converted to byte in buffer and bit in byte */
    bit = 1 << (bitpos & 7);
    if (value & 1) {
        buf[bitpos >> 3] |= bit;
    } else {
        buf[bitpos >> 3] &= ~bit;
    }
    return address_space_write(&s->source_as, addr, attrs, buf, size);
}

static const MemoryRegionOps bitband_ops = {
    .read_with_attrs = bitband_read,
    .write_with_attrs = bitband_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .impl.min_access_size = 1,
    .impl.max_access_size = 4,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
};

static void bitband_init(Object *obj)
{
    BitBandState *s = BITBAND(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);

    memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
                          "bitband", 0x02000000);
    sysbus_init_mmio(dev, &s->iomem);
}

static void bitband_realize(DeviceState *dev, Error **errp)
{
    BitBandState *s = BITBAND(dev);

    if (!s->source_memory) {
        error_setg(errp, "source-memory property not set");
        return;
    }

    address_space_init(&s->source_as, s->source_memory, "bitband-source");
}

/* Board init.  */

static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
    0x20000000, 0x40000000
};

static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
    0x22000000, 0x42000000
};

static void armv7m_instance_init(Object *obj)
{
    ARMv7MState *s = ARMV7M(obj);
    int i;

    /* Can't init the cpu here, we don't yet know which model to use */

    memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);

    sysbus_init_child_obj(obj, "nvnic", &s->nvic, sizeof(s->nvic), TYPE_NVIC);
    object_property_add_alias(obj, "num-irq",
                              OBJECT(&s->nvic), "num-irq");

    for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
        sysbus_init_child_obj(obj, "bitband[*]", &s->bitband[i],
                              sizeof(s->bitband[i]), TYPE_BITBAND);
    }
}

static void armv7m_realize(DeviceState *dev, Error **errp)
{
    ARMv7MState *s = ARMV7M(dev);
    SysBusDevice *sbd;
    Error *err = NULL;
    int i;

    if (!s->board_memory) {
        error_setg(errp, "memory property was not set");
        return;
    }

    memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);

    s->cpu = ARM_CPU(object_new_with_props(s->cpu_type, OBJECT(s), "cpu",
                                           &err, NULL));
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }

    object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
                             &error_abort);
    if (object_property_find(OBJECT(s->cpu), "idau", NULL)) {
        object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }
    }
    if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) {
        object_property_set_uint(OBJECT(s->cpu), s->init_svtor,
                                 "init-svtor", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }
    }
    if (object_property_find(OBJECT(s->cpu), "start-powered-off", NULL)) {
        object_property_set_bool(OBJECT(s->cpu), s->start_powered_off,
                                 "start-powered-off", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }
    }
    if (object_property_find(OBJECT(s->cpu), "vfp", NULL)) {
        object_property_set_bool(OBJECT(s->cpu), s->vfp,
                                 "vfp", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }
    }
    if (object_property_find(OBJECT(s->cpu), "dsp", NULL)) {
        object_property_set_bool(OBJECT(s->cpu), s->dsp,
                                 "dsp", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }
    }

    /*
     * Tell the CPU where the NVIC is; it will fail realize if it doesn't
     * have one. Similarly, tell the NVIC where its CPU is.
     */
    s->cpu->env.nvic = &s->nvic;
    s->nvic.cpu = s->cpu;

    object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }

    /* Note that we must realize the NVIC after the CPU */
    object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }

    /* Alias the NVIC's input and output GPIOs as our own so the board
     * code can wire them up. (We do this in realize because the
     * NVIC doesn't create the input GPIO array until realize.)
     */
    qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
    qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
    qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");

    /* Wire the NVIC up to the CPU */
    sbd = SYS_BUS_DEVICE(&s->nvic);
    sysbus_connect_irq(sbd, 0,
                       qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));

    memory_region_add_subregion(&s->container, 0xe000e000,
                                sysbus_mmio_get_region(sbd, 0));

    if (s->enable_bitband) {
        for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
            Object *obj = OBJECT(&s->bitband[i]);
            SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);

            object_property_set_int(obj, bitband_input_addr[i], "base", &err);
            if (err != NULL) {
                error_propagate(errp, err);
                return;
            }
            object_property_set_link(obj, OBJECT(s->board_memory),
                                     "source-memory", &error_abort);
            object_property_set_bool(obj, true, "realized", &err);
            if (err != NULL) {
                error_propagate(errp, err);
                return;
            }

            memory_region_add_subregion(&s->container, bitband_output_addr[i],
                                        sysbus_mmio_get_region(sbd, 0));
        }
    }
}

static Property armv7m_properties[] = {
    DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
    DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
                     MemoryRegion *),
    DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
    DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
    DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false),
    DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off,
                     false),
    DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
    DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
    DEFINE_PROP_END_OF_LIST(),
};

static void armv7m_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = armv7m_realize;
    device_class_set_props(dc, armv7m_properties);
}

static const TypeInfo armv7m_info = {
    .name = TYPE_ARMV7M,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(ARMv7MState),
    .instance_init = armv7m_instance_init,
    .class_init = armv7m_class_init,
};

static void armv7m_reset(void *opaque)
{
    ARMCPU *cpu = opaque;

    cpu_reset(CPU(cpu));
}

void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
{
    int image_size;
    uint64_t entry;
    uint64_t lowaddr;
    int big_endian;
    AddressSpace *as;
    int asidx;
    CPUState *cs = CPU(cpu);

#ifdef TARGET_WORDS_BIGENDIAN
    big_endian = 1;
#else
    big_endian = 0;
#endif

    if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
        asidx = ARMASIdx_S;
    } else {
        asidx = ARMASIdx_NS;
    }
    as = cpu_get_address_space(cs, asidx);

    if (kernel_filename) {
        image_size = load_elf_as(kernel_filename, NULL, NULL, NULL,
                                 &entry, &lowaddr, NULL,
                                 NULL, big_endian, EM_ARM, 1, 0, as);
        if (image_size < 0) {
            image_size = load_image_targphys_as(kernel_filename, 0,
                                                mem_size, as);
            lowaddr = 0;
        }
        if (image_size < 0) {
            error_report("Could not load kernel '%s'", kernel_filename);
            exit(1);
        }
    }

    /* CPU objects (unlike devices) are not automatically reset on system
     * reset, so we must always register a handler to do so. Unlike
     * A-profile CPUs, we don't need to do anything special in the
     * handler to arrange that it starts correctly.
     * This is arguably the wrong place to do this, but it matches the
     * way A-profile does it. Note that this means that every M profile
     * board must call this function!
     */
    qemu_register_reset(armv7m_reset, cpu);
}

static Property bitband_properties[] = {
    DEFINE_PROP_UINT32("base", BitBandState, base, 0),
    DEFINE_PROP_LINK("source-memory", BitBandState, source_memory,
                     TYPE_MEMORY_REGION, MemoryRegion *),
    DEFINE_PROP_END_OF_LIST(),
};

static void bitband_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = bitband_realize;
    device_class_set_props(dc, bitband_properties);
}

static const TypeInfo bitband_info = {
    .name          = TYPE_BITBAND,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(BitBandState),
    .instance_init = bitband_init,
    .class_init    = bitband_class_init,
};

static void armv7m_register_types(void)
{
    type_register_static(&bitband_info);
    type_register_static(&armv7m_info);
}

type_init(armv7m_register_types)
Commit	Line	Data
9ee6e8bb PB	1	/*
	2	* ARMV7M System emulation.
	3	*
	4	* Copyright (c) 2006-2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
2167f7bc	7	* This code is licensed under the GPL.
9ee6e8bb PB	8	*/
9ee6e8bb PB	9
12b16722	10	#include "qemu/osdep.h"
56b7c66f	11	#include "hw/arm/armv7m.h"
da34e65c	12	#include "qapi/error.h"
4771d756	13	#include "cpu.h"
83c9f4ca	14	#include "hw/sysbus.h"
12ec8bd5	15	#include "hw/arm/boot.h"
83c9f4ca	16	#include "hw/loader.h"
a27bd6c7	17	#include "hw/qdev-properties.h"
ca20cf32	18	#include "elf.h"
5633b90a	19	#include "sysemu/qtest.h"
71e8a915	20	#include "sysemu/reset.h"
5633b90a	21	#include "qemu/error-report.h"
0b8fa32f	22	#include "qemu/module.h"
618119c2	23	#include "exec/address-spaces.h"
c60c1b0d	24	#include "target/arm/idau.h"
9ee6e8bb PB	25
	26	/* Bitbanded IO. Each word corresponds to a single bit. */
	27
2167f7bc	28	/* Get the byte address of the real memory for a bitband access. */
f68d881c	29	static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
9ee6e8bb	30	{
f68d881c	31	return s->base \| (offset & 0x1ffffff) >> 5;
9ee6e8bb PB	32	}
9ee6e8bb PB	33
f68d881c PM	34	static MemTxResult bitband_read(void *opaque, hwaddr offset,
f68d881c PM	35	uint64_t *data, unsigned size, MemTxAttrs attrs)
9ee6e8bb	36	{
f68d881c PM	37	BitBandState *s = opaque;
	38	uint8_t buf[4];
	39	MemTxResult res;
	40	int bitpos, bit;
	41	hwaddr addr;
	42
	43	assert(size <= 4);
	44
	45	/* Find address in underlying memory and round down to multiple of size */
	46	addr = bitband_addr(s, offset) & (-size);
b516572f	47	res = address_space_read(&s->source_as, addr, attrs, buf, size);
f68d881c PM	48	if (res) {
	49	return res;
	50	}
	51	/* Bit position in the N bytes read... */
	52	bitpos = (offset >> 2) & ((size * 8) - 1);
	53	/* ...converted to byte in buffer and bit in byte */
	54	bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
	55	*data = bit;
	56	return MEMTX_OK;
9ee6e8bb PB	57	}
9ee6e8bb PB	58
f68d881c PM	59	static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
f68d881c PM	60	unsigned size, MemTxAttrs attrs)
9ee6e8bb	61	{
f68d881c PM	62	BitBandState *s = opaque;
	63	uint8_t buf[4];
	64	MemTxResult res;
	65	int bitpos, bit;
	66	hwaddr addr;
	67
	68	assert(size <= 4);
	69
	70	/* Find address in underlying memory and round down to multiple of size */
	71	addr = bitband_addr(s, offset) & (-size);
b516572f	72	res = address_space_read(&s->source_as, addr, attrs, buf, size);
f68d881c PM	73	if (res) {
	74	return res;
	75	}
	76	/* Bit position in the N bytes read... */
	77	bitpos = (offset >> 2) & ((size * 8) - 1);
	78	/* ...converted to byte in buffer and bit in byte */
	79	bit = 1 << (bitpos & 7);
	80	if (value & 1) {
	81	buf[bitpos >> 3] \|= bit;
	82	} else {
	83	buf[bitpos >> 3] &= ~bit;
	84	}
b516572f	85	return address_space_write(&s->source_as, addr, attrs, buf, size);
9ee6e8bb PB	86	}
9ee6e8bb PB	87
f69bf9d4	88	static const MemoryRegionOps bitband_ops = {
f68d881c PM	89	.read_with_attrs = bitband_read,
f68d881c PM	90	.write_with_attrs = bitband_write,
f69bf9d4	91	.endianness = DEVICE_NATIVE_ENDIAN,
f68d881c PM	92	.impl.min_access_size = 1,
	93	.impl.max_access_size = 4,
	94	.valid.min_access_size = 1,
	95	.valid.max_access_size = 4,
9ee6e8bb PB	96	};
9ee6e8bb PB	97
3f5ab254	98	static void bitband_init(Object *obj)
9ee6e8bb	99	{
3f5ab254 XZ	100	BitBandState *s = BITBAND(obj);
3f5ab254 XZ	101	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
9ee6e8bb	102
f68d881c	103	memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
64bde0f3	104	"bitband", 0x02000000);
750ecd44	105	sysbus_init_mmio(dev, &s->iomem);
40905a6a PB	106	}
40905a6a PB	107
f68d881c PM	108	static void bitband_realize(DeviceState dev, Error *errp)
	109	{
	110	BitBandState *s = BITBAND(dev);
	111
	112	if (!s->source_memory) {
	113	error_setg(errp, "source-memory property not set");
	114	return;
	115	}
	116
b516572f	117	address_space_init(&s->source_as, s->source_memory, "bitband-source");
f68d881c PM	118	}
f68d881c PM	119
9ee6e8bb	120	/* Board init. */
983fe826	121
56b7c66f PM	122	static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
	123	0x20000000, 0x40000000
	124	};
	125
	126	static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
	127	0x22000000, 0x42000000
	128	};
	129
	130	static void armv7m_instance_init(Object *obj)
	131	{
	132	ARMv7MState *s = ARMV7M(obj);
	133	int i;
	134
	135	/* Can't init the cpu here, we don't yet know which model to use */
	136
618119c2 PM	137	memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
618119c2 PM	138
955cbc6b	139	sysbus_init_child_obj(obj, "nvnic", &s->nvic, sizeof(s->nvic), TYPE_NVIC);
56b7c66f	140	object_property_add_alias(obj, "num-irq",
d2623129	141	OBJECT(&s->nvic), "num-irq");
56b7c66f PM	142
56b7c66f PM	143	for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
955cbc6b TH	144	sysbus_init_child_obj(obj, "bitband[*]", &s->bitband[i],
955cbc6b TH	145	sizeof(s->bitband[i]), TYPE_BITBAND);
56b7c66f PM	146	}
	147	}
	148
	149	static void armv7m_realize(DeviceState dev, Error *errp)
	150	{
	151	ARMv7MState *s = ARMV7M(dev);
98957a94	152	SysBusDevice *sbd;
56b7c66f PM	153	Error *err = NULL;
56b7c66f PM	154	int i;
56b7c66f	155
618119c2 PM	156	if (!s->board_memory) {
	157	error_setg(errp, "memory property was not set");
	158	return;
	159	}
	160
	161	memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
	162
e4c81e3a PM	163	s->cpu = ARM_CPU(object_new_with_props(s->cpu_type, OBJECT(s), "cpu",
	164	&err, NULL));
	165	if (err != NULL) {
	166	error_propagate(errp, err);
	167	return;
	168	}
56b7c66f	169
618119c2 PM	170	object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
618119c2 PM	171	&error_abort);
c60c1b0d PM	172	if (object_property_find(OBJECT(s->cpu), "idau", NULL)) {
	173	object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err);
	174	if (err != NULL) {
	175	error_propagate(errp, err);
	176	return;
	177	}
	178	}
60d75d81 PM	179	if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) {
	180	object_property_set_uint(OBJECT(s->cpu), s->init_svtor,
	181	"init-svtor", &err);
	182	if (err != NULL) {
	183	error_propagate(errp, err);
	184	return;
	185	}
	186	}
66647809 PM	187	if (object_property_find(OBJECT(s->cpu), "start-powered-off", NULL)) {
	188	object_property_set_bool(OBJECT(s->cpu), s->start_powered_off,
	189	"start-powered-off", &err);
	190	if (err != NULL) {
	191	error_propagate(errp, err);
	192	return;
	193	}
	194	}
e0cf7b81 PM	195	if (object_property_find(OBJECT(s->cpu), "vfp", NULL)) {
	196	object_property_set_bool(OBJECT(s->cpu), s->vfp,
	197	"vfp", &err);
	198	if (err != NULL) {
	199	error_propagate(errp, err);
	200	return;
	201	}
	202	}
	203	if (object_property_find(OBJECT(s->cpu), "dsp", NULL)) {
	204	object_property_set_bool(OBJECT(s->cpu), s->dsp,
	205	"dsp", &err);
	206	if (err != NULL) {
	207	error_propagate(errp, err);
	208	return;
	209	}
	210	}
95f87565	211
3693f217 PM	212	/*
	213	* Tell the CPU where the NVIC is; it will fail realize if it doesn't
	214	* have one. Similarly, tell the NVIC where its CPU is.
95f87565 PM	215	*/
95f87565 PM	216	s->cpu->env.nvic = &s->nvic;
3693f217	217	s->nvic.cpu = s->cpu;
95f87565	218
56b7c66f PM	219	object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
	220	if (err != NULL) {
	221	error_propagate(errp, err);
	222	return;
	223	}
	224
	225	/* Note that we must realize the NVIC after the CPU */
	226	object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
	227	if (err != NULL) {
	228	error_propagate(errp, err);
	229	return;
	230	}
	231
	232	/* Alias the NVIC's input and output GPIOs as our own so the board
	233	* code can wire them up. (We do this in realize because the
	234	* NVIC doesn't create the input GPIO array until realize.)
	235	*/
	236	qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
	237	qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
514b4f36	238	qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");
56b7c66f PM	239
56b7c66f PM	240	/* Wire the NVIC up to the CPU */
98957a94 PM	241	sbd = SYS_BUS_DEVICE(&s->nvic);
98957a94 PM	242	sysbus_connect_irq(sbd, 0,
56b7c66f	243	qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
56b7c66f	244
98957a94 PM	245	memory_region_add_subregion(&s->container, 0xe000e000,
	246	sysbus_mmio_get_region(sbd, 0));
	247
a1c5a062 SH	248	if (s->enable_bitband) {
	249	for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
	250	Object *obj = OBJECT(&s->bitband[i]);
	251	SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
	252
	253	object_property_set_int(obj, bitband_input_addr[i], "base", &err);
	254	if (err != NULL) {
	255	error_propagate(errp, err);
	256	return;
	257	}
	258	object_property_set_link(obj, OBJECT(s->board_memory),
	259	"source-memory", &error_abort);
	260	object_property_set_bool(obj, true, "realized", &err);
	261	if (err != NULL) {
	262	error_propagate(errp, err);
	263	return;
	264	}
	265
	266	memory_region_add_subregion(&s->container, bitband_output_addr[i],
	267	sysbus_mmio_get_region(sbd, 0));
56b7c66f	268	}
56b7c66f PM	269	}
	270	}
	271
	272	static Property armv7m_properties[] = {
ba1ba5cc	273	DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
e2ff1215 FZ	274	DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
e2ff1215 FZ	275	MemoryRegion *),
c60c1b0d	276	DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
60d75d81	277	DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
a1c5a062	278	DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false),
66647809 PM	279	DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off,
66647809 PM	280	false),
e0cf7b81 PM	281	DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
e0cf7b81 PM	282	DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
56b7c66f PM	283	DEFINE_PROP_END_OF_LIST(),
	284	};
	285
	286	static void armv7m_class_init(ObjectClass klass, void data)
	287	{
	288	DeviceClass *dc = DEVICE_CLASS(klass);
	289
	290	dc->realize = armv7m_realize;
4f67d30b	291	device_class_set_props(dc, armv7m_properties);
56b7c66f PM	292	}
	293
	294	static const TypeInfo armv7m_info = {
	295	.name = TYPE_ARMV7M,
	296	.parent = TYPE_SYS_BUS_DEVICE,
	297	.instance_size = sizeof(ARMv7MState),
	298	.instance_init = armv7m_instance_init,
	299	.class_init = armv7m_class_init,
	300	};
	301
983fe826 PB	302	static void armv7m_reset(void *opaque)
983fe826 PB	303	{
31363f12 AF	304	ARMCPU *cpu = opaque;
	305
	306	cpu_reset(CPU(cpu));
983fe826 PB	307	}
983fe826 PB	308
3651c285 PM	309	void armv7m_load_kernel(ARMCPU cpu, const char kernel_filename, int mem_size)
	310	{
	311	int image_size;
	312	uint64_t entry;
	313	uint64_t lowaddr;
	314	int big_endian;
891f3bc3 PM	315	AddressSpace *as;
	316	int asidx;
	317	CPUState *cs = CPU(cpu);
9ee6e8bb	318
ca20cf32 BS	319	#ifdef TARGET_WORDS_BIGENDIAN
	320	big_endian = 1;
	321	#else
	322	big_endian = 0;
	323	#endif
	324
891f3bc3 PM	325	if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
	326	asidx = ARMASIdx_S;
	327	} else {
	328	asidx = ARMASIdx_NS;
	329	}
	330	as = cpu_get_address_space(cs, asidx);
	331
5633b90a	332	if (kernel_filename) {
4366e1db	333	image_size = load_elf_as(kernel_filename, NULL, NULL, NULL,
6cdda0ff	334	&entry, &lowaddr, NULL,
891f3bc3	335	NULL, big_endian, EM_ARM, 1, 0, as);
5633b90a	336	if (image_size < 0) {
891f3bc3 PM	337	image_size = load_image_targphys_as(kernel_filename, 0,
891f3bc3 PM	338	mem_size, as);
5633b90a AF	339	lowaddr = 0;
	340	}
	341	if (image_size < 0) {
	342	error_report("Could not load kernel '%s'", kernel_filename);
	343	exit(1);
	344	}
9ee6e8bb PB	345	}
9ee6e8bb PB	346
3651c285 PM	347	/* CPU objects (unlike devices) are not automatically reset on system
	348	* reset, so we must always register a handler to do so. Unlike
	349	* A-profile CPUs, we don't need to do anything special in the
	350	* handler to arrange that it starts correctly.
	351	* This is arguably the wrong place to do this, but it matches the
	352	* way A-profile does it. Note that this means that every M profile
	353	* board must call this function!
	354	*/
31363f12	355	qemu_register_reset(armv7m_reset, cpu);
9ee6e8bb	356	}
40905a6a	357
999e12bb AL	358	static Property bitband_properties[] = {
999e12bb AL	359	DEFINE_PROP_UINT32("base", BitBandState, base, 0),
5f486f97 FZ	360	DEFINE_PROP_LINK("source-memory", BitBandState, source_memory,
5f486f97 FZ	361	TYPE_MEMORY_REGION, MemoryRegion *),
999e12bb AL	362	DEFINE_PROP_END_OF_LIST(),
	363	};
	364
	365	static void bitband_class_init(ObjectClass klass, void data)
	366	{
39bffca2	367	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	368
f68d881c	369	dc->realize = bitband_realize;
4f67d30b	370	device_class_set_props(dc, bitband_properties);
999e12bb AL	371	}
999e12bb AL	372
8c43a6f0	373	static const TypeInfo bitband_info = {
936230a7	374	.name = TYPE_BITBAND,
39bffca2 AL	375	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	376	.instance_size = sizeof(BitBandState),
3f5ab254	377	.instance_init = bitband_init,
39bffca2	378	.class_init = bitband_class_init,
ee6847d1 GH	379	};
ee6847d1 GH	380
83f7d43a	381	static void armv7m_register_types(void)
40905a6a	382	{
39bffca2	383	type_register_static(&bitband_info);
56b7c66f	384	type_register_static(&armv7m_info);
40905a6a PB	385	}
40905a6a PB	386
83f7d43a	387	type_init(armv7m_register_types)