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Commit | Line | Data |
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43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * Jeremy Kerr <jk@ozlabs.org> | |
6 | * | |
7 | * Copyright 2016 IBM Corp. | |
8 | * | |
9 | * This code is licensed under the GPL version 2 or later. See | |
10 | * the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
da34e65c | 14 | #include "qapi/error.h" |
4771d756 | 15 | #include "cpu.h" |
43e3346e | 16 | #include "exec/address-spaces.h" |
c7c3c9f8 | 17 | #include "hw/misc/unimp.h" |
00442402 | 18 | #include "hw/arm/aspeed_soc.h" |
43e3346e | 19 | #include "hw/char/serial.h" |
03dd024f | 20 | #include "qemu/log.h" |
0b8fa32f | 21 | #include "qemu/module.h" |
ece09bee | 22 | #include "qemu/error-report.h" |
16020011 | 23 | #include "hw/i2c/aspeed_i2c.h" |
ea337c65 | 24 | #include "net/net.h" |
46517dd4 | 25 | #include "sysemu/sysemu.h" |
43e3346e | 26 | |
ff90606f | 27 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 |
d783d1fe CLG |
28 | |
29 | static const hwaddr aspeed_soc_ast2400_memmap[] = { | |
30 | [ASPEED_IOMEM] = 0x1E600000, | |
31 | [ASPEED_FMC] = 0x1E620000, | |
32 | [ASPEED_SPI1] = 0x1E630000, | |
bfdd34f1 | 33 | [ASPEED_EHCI1] = 0x1E6A1000, |
d783d1fe CLG |
34 | [ASPEED_VIC] = 0x1E6C0000, |
35 | [ASPEED_SDMC] = 0x1E6E0000, | |
36 | [ASPEED_SCU] = 0x1E6E2000, | |
118c82e7 | 37 | [ASPEED_XDMA] = 0x1E6E7000, |
514bcf6f | 38 | [ASPEED_VIDEO] = 0x1E700000, |
d783d1fe CLG |
39 | [ASPEED_ADC] = 0x1E6E9000, |
40 | [ASPEED_SRAM] = 0x1E720000, | |
2bea128c | 41 | [ASPEED_SDHCI] = 0x1E740000, |
d783d1fe CLG |
42 | [ASPEED_GPIO] = 0x1E780000, |
43 | [ASPEED_RTC] = 0x1E781000, | |
44 | [ASPEED_TIMER1] = 0x1E782000, | |
45 | [ASPEED_WDT] = 0x1E785000, | |
46 | [ASPEED_PWM] = 0x1E786000, | |
47 | [ASPEED_LPC] = 0x1E789000, | |
48 | [ASPEED_IBT] = 0x1E789140, | |
49 | [ASPEED_I2C] = 0x1E78A000, | |
50 | [ASPEED_ETH1] = 0x1E660000, | |
51 | [ASPEED_ETH2] = 0x1E680000, | |
52 | [ASPEED_UART1] = 0x1E783000, | |
53 | [ASPEED_UART5] = 0x1E784000, | |
54 | [ASPEED_VUART] = 0x1E787000, | |
55 | [ASPEED_SDRAM] = 0x40000000, | |
56 | }; | |
57 | ||
58 | static const hwaddr aspeed_soc_ast2500_memmap[] = { | |
59 | [ASPEED_IOMEM] = 0x1E600000, | |
60 | [ASPEED_FMC] = 0x1E620000, | |
61 | [ASPEED_SPI1] = 0x1E630000, | |
62 | [ASPEED_SPI2] = 0x1E631000, | |
bfdd34f1 GR |
63 | [ASPEED_EHCI1] = 0x1E6A1000, |
64 | [ASPEED_EHCI2] = 0x1E6A3000, | |
d783d1fe CLG |
65 | [ASPEED_VIC] = 0x1E6C0000, |
66 | [ASPEED_SDMC] = 0x1E6E0000, | |
67 | [ASPEED_SCU] = 0x1E6E2000, | |
118c82e7 | 68 | [ASPEED_XDMA] = 0x1E6E7000, |
d783d1fe | 69 | [ASPEED_ADC] = 0x1E6E9000, |
514bcf6f | 70 | [ASPEED_VIDEO] = 0x1E700000, |
d783d1fe | 71 | [ASPEED_SRAM] = 0x1E720000, |
2bea128c | 72 | [ASPEED_SDHCI] = 0x1E740000, |
d783d1fe CLG |
73 | [ASPEED_GPIO] = 0x1E780000, |
74 | [ASPEED_RTC] = 0x1E781000, | |
75 | [ASPEED_TIMER1] = 0x1E782000, | |
76 | [ASPEED_WDT] = 0x1E785000, | |
77 | [ASPEED_PWM] = 0x1E786000, | |
78 | [ASPEED_LPC] = 0x1E789000, | |
79 | [ASPEED_IBT] = 0x1E789140, | |
80 | [ASPEED_I2C] = 0x1E78A000, | |
81 | [ASPEED_ETH1] = 0x1E660000, | |
82 | [ASPEED_ETH2] = 0x1E680000, | |
83 | [ASPEED_UART1] = 0x1E783000, | |
84 | [ASPEED_UART5] = 0x1E784000, | |
85 | [ASPEED_VUART] = 0x1E787000, | |
86 | [ASPEED_SDRAM] = 0x80000000, | |
87 | }; | |
ff90606f | 88 | |
b456b113 CLG |
89 | static const int aspeed_soc_ast2400_irqmap[] = { |
90 | [ASPEED_UART1] = 9, | |
91 | [ASPEED_UART2] = 32, | |
92 | [ASPEED_UART3] = 33, | |
93 | [ASPEED_UART4] = 34, | |
94 | [ASPEED_UART5] = 10, | |
95 | [ASPEED_VUART] = 8, | |
96 | [ASPEED_FMC] = 19, | |
bfdd34f1 GR |
97 | [ASPEED_EHCI1] = 5, |
98 | [ASPEED_EHCI2] = 13, | |
b456b113 CLG |
99 | [ASPEED_SDMC] = 0, |
100 | [ASPEED_SCU] = 21, | |
101 | [ASPEED_ADC] = 31, | |
102 | [ASPEED_GPIO] = 20, | |
103 | [ASPEED_RTC] = 22, | |
104 | [ASPEED_TIMER1] = 16, | |
105 | [ASPEED_TIMER2] = 17, | |
106 | [ASPEED_TIMER3] = 18, | |
107 | [ASPEED_TIMER4] = 35, | |
108 | [ASPEED_TIMER5] = 36, | |
109 | [ASPEED_TIMER6] = 37, | |
110 | [ASPEED_TIMER7] = 38, | |
111 | [ASPEED_TIMER8] = 39, | |
112 | [ASPEED_WDT] = 27, | |
113 | [ASPEED_PWM] = 28, | |
114 | [ASPEED_LPC] = 8, | |
115 | [ASPEED_IBT] = 8, /* LPC */ | |
116 | [ASPEED_I2C] = 12, | |
117 | [ASPEED_ETH1] = 2, | |
118 | [ASPEED_ETH2] = 3, | |
118c82e7 | 119 | [ASPEED_XDMA] = 6, |
2bea128c | 120 | [ASPEED_SDHCI] = 26, |
b456b113 | 121 | }; |
43e3346e | 122 | |
b456b113 CLG |
123 | #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap |
124 | ||
b456b113 CLG |
125 | static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) |
126 | { | |
127 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
128 | ||
54ecafb7 | 129 | return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]); |
b456b113 CLG |
130 | } |
131 | ||
ff90606f | 132 | static void aspeed_soc_init(Object *obj) |
43e3346e | 133 | { |
ff90606f | 134 | AspeedSoCState *s = ASPEED_SOC(obj); |
b033271f | 135 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
dbcabeeb | 136 | int i; |
811a5b1d CLG |
137 | char socname[8]; |
138 | char typename[64]; | |
139 | ||
54ecafb7 | 140 | if (sscanf(sc->name, "%7s", socname) != 1) { |
811a5b1d CLG |
141 | g_assert_not_reached(); |
142 | } | |
43e3346e | 143 | |
54ecafb7 | 144 | for (i = 0; i < sc->num_cpus; i++) { |
9fc7fc4d | 145 | object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); |
ece09bee | 146 | } |
43e3346e | 147 | |
9a937f6c | 148 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); |
db873cc5 | 149 | object_initialize_child(obj, "scu", &s->scu, typename); |
334973bb | 150 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
54ecafb7 | 151 | sc->silicon_rev); |
334973bb | 152 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), |
d2623129 | 153 | "hw-strap1"); |
334973bb | 154 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
d2623129 | 155 | "hw-strap2"); |
b6e70d1d | 156 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
d2623129 | 157 | "hw-prot-key"); |
7c1c69bc | 158 | |
db873cc5 | 159 | object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC); |
e2a11ca8 | 160 | |
db873cc5 | 161 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
75fb4577 | 162 | |
72d96f8e | 163 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); |
db873cc5 | 164 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
e2a11ca8 | 165 | |
f7da1aa8 | 166 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
db873cc5 | 167 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
e2a11ca8 | 168 | |
811a5b1d | 169 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); |
db873cc5 | 170 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
d2623129 | 171 | object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); |
7c1c69bc | 172 | |
54ecafb7 | 173 | for (i = 0; i < sc->spis_num; i++) { |
811a5b1d | 174 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); |
db873cc5 | 175 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
dbcabeeb | 176 | } |
c2da8a8b | 177 | |
bfdd34f1 | 178 | for (i = 0; i < sc->ehcis_num; i++) { |
db873cc5 MA |
179 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
180 | TYPE_PLATFORM_EHCI); | |
bfdd34f1 GR |
181 | } |
182 | ||
8e00d1a9 | 183 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
db873cc5 | 184 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
c6c7cfb0 | 185 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
d2623129 | 186 | "ram-size"); |
ebe31c0a | 187 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), |
d2623129 | 188 | "max-ram-size"); |
013befe1 | 189 | |
54ecafb7 | 190 | for (i = 0; i < sc->wdts_num; i++) { |
6112bd6d | 191 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); |
db873cc5 | 192 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
f986ee1d | 193 | } |
ea337c65 | 194 | |
d300db02 | 195 | for (i = 0; i < sc->macs_num; i++) { |
db873cc5 MA |
196 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
197 | TYPE_FTGMAC100); | |
67340990 | 198 | } |
118c82e7 | 199 | |
db873cc5 | 200 | object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); |
fdcc7c06 | 201 | |
811a5b1d | 202 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); |
db873cc5 | 203 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
2bea128c | 204 | |
db873cc5 | 205 | object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI); |
2bea128c | 206 | |
5325cc34 | 207 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
0e2c24c6 | 208 | |
2bea128c EJ |
209 | /* Init sd card slot class here so that they're under the correct parent */ |
210 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
7089e0cc MA |
211 | object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], |
212 | TYPE_SYSBUS_SDHCI); | |
2bea128c | 213 | } |
43e3346e AJ |
214 | } |
215 | ||
ff90606f | 216 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) |
43e3346e AJ |
217 | { |
218 | int i; | |
ff90606f | 219 | AspeedSoCState *s = ASPEED_SOC(dev); |
dbcabeeb | 220 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
123327d1 | 221 | Error *err = NULL; |
43e3346e AJ |
222 | |
223 | /* IO space */ | |
54ecafb7 | 224 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], |
d783d1fe | 225 | ASPEED_SOC_IOMEM_SIZE); |
43e3346e | 226 | |
514bcf6f JS |
227 | /* Video engine stub */ |
228 | create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], | |
229 | 0x1000); | |
230 | ||
2d105bd6 | 231 | /* CPU */ |
b7f1a0cb | 232 | for (i = 0; i < sc->num_cpus; i++) { |
668f62ec | 233 | if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { |
ece09bee CLG |
234 | return; |
235 | } | |
2d105bd6 CLG |
236 | } |
237 | ||
74af4eec | 238 | /* SRAM */ |
a2e9989c | 239 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", |
54ecafb7 | 240 | sc->sram_size, &err); |
74af4eec CLG |
241 | if (err) { |
242 | error_propagate(errp, err); | |
243 | return; | |
244 | } | |
d783d1fe | 245 | memory_region_add_subregion(get_system_memory(), |
54ecafb7 | 246 | sc->memmap[ASPEED_SRAM], &s->sram); |
74af4eec | 247 | |
e2a11ca8 | 248 | /* SCU */ |
668f62ec | 249 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { |
e2a11ca8 CLG |
250 | return; |
251 | } | |
54ecafb7 | 252 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); |
e2a11ca8 | 253 | |
43e3346e | 254 | /* VIC */ |
668f62ec | 255 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) { |
43e3346e AJ |
256 | return; |
257 | } | |
54ecafb7 | 258 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]); |
43e3346e | 259 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, |
2d105bd6 | 260 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); |
43e3346e | 261 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, |
2d105bd6 | 262 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); |
43e3346e | 263 | |
75fb4577 | 264 | /* RTC */ |
668f62ec | 265 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
75fb4577 JS |
266 | return; |
267 | } | |
54ecafb7 | 268 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); |
75fb4577 JS |
269 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
270 | aspeed_soc_get_irq(s, ASPEED_RTC)); | |
271 | ||
43e3346e | 272 | /* Timer */ |
5325cc34 MA |
273 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
274 | &error_abort); | |
668f62ec | 275 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { |
43e3346e AJ |
276 | return; |
277 | } | |
d783d1fe | 278 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, |
54ecafb7 | 279 | sc->memmap[ASPEED_TIMER1]); |
b456b113 CLG |
280 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
281 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); | |
43e3346e AJ |
282 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
283 | } | |
284 | ||
285 | /* UART - attach an 8250 to the IO space as our UART5 */ | |
9bca0edb | 286 | if (serial_hd(0)) { |
b456b113 | 287 | qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); |
54ecafb7 | 288 | serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, |
9bca0edb | 289 | uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); |
43e3346e | 290 | } |
16020011 CLG |
291 | |
292 | /* I2C */ | |
5325cc34 | 293 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
c24d9716 | 294 | &error_abort); |
668f62ec | 295 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { |
16020011 CLG |
296 | return; |
297 | } | |
54ecafb7 | 298 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); |
16020011 | 299 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, |
b456b113 | 300 | aspeed_soc_get_irq(s, ASPEED_I2C)); |
7c1c69bc | 301 | |
26d5df95 | 302 | /* FMC, The number of CS is set at the board level */ |
5325cc34 | 303 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
c24d9716 | 304 | &error_abort); |
778a2dc5 | 305 | if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base", |
668f62ec | 306 | sc->memmap[ASPEED_SDRAM], errp)) { |
6da4433f CLG |
307 | return; |
308 | } | |
668f62ec | 309 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { |
7c1c69bc CLG |
310 | return; |
311 | } | |
54ecafb7 | 312 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); |
dcb83444 CLG |
313 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, |
314 | s->fmc.ctrl->flash_window_base); | |
0e5803df | 315 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
b456b113 | 316 | aspeed_soc_get_irq(s, ASPEED_FMC)); |
7c1c69bc CLG |
317 | |
318 | /* SPI */ | |
54ecafb7 | 319 | for (i = 0; i < sc->spis_num; i++) { |
5325cc34 | 320 | object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); |
668f62ec | 321 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
dbcabeeb CLG |
322 | return; |
323 | } | |
d783d1fe | 324 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, |
54ecafb7 | 325 | sc->memmap[ASPEED_SPI1 + i]); |
dbcabeeb CLG |
326 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, |
327 | s->spi[i].ctrl->flash_window_base); | |
7c1c69bc | 328 | } |
c2da8a8b | 329 | |
bfdd34f1 GR |
330 | /* EHCI */ |
331 | for (i = 0; i < sc->ehcis_num; i++) { | |
668f62ec | 332 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { |
bfdd34f1 GR |
333 | return; |
334 | } | |
335 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, | |
336 | sc->memmap[ASPEED_EHCI1 + i]); | |
337 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, | |
338 | aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); | |
339 | } | |
340 | ||
c2da8a8b | 341 | /* SDMC - SDRAM Memory Controller */ |
668f62ec | 342 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { |
c2da8a8b CLG |
343 | return; |
344 | } | |
54ecafb7 | 345 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); |
013befe1 CLG |
346 | |
347 | /* Watch dog */ | |
54ecafb7 | 348 | for (i = 0; i < sc->wdts_num; i++) { |
6112bd6d CLG |
349 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); |
350 | ||
5325cc34 MA |
351 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
352 | &error_abort); | |
668f62ec | 353 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { |
f986ee1d JS |
354 | return; |
355 | } | |
356 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
54ecafb7 | 357 | sc->memmap[ASPEED_WDT] + i * awc->offset); |
013befe1 | 358 | } |
ea337c65 CLG |
359 | |
360 | /* Net */ | |
d3bad7e7 | 361 | for (i = 0; i < sc->macs_num; i++) { |
5325cc34 | 362 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
2255f6b7 | 363 | &error_abort); |
668f62ec | 364 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { |
123327d1 | 365 | return; |
67340990 CLG |
366 | } |
367 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | |
54ecafb7 | 368 | sc->memmap[ASPEED_ETH1 + i]); |
67340990 CLG |
369 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
370 | aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); | |
ea337c65 | 371 | } |
118c82e7 EJ |
372 | |
373 | /* XDMA */ | |
668f62ec | 374 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { |
118c82e7 EJ |
375 | return; |
376 | } | |
377 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | |
54ecafb7 | 378 | sc->memmap[ASPEED_XDMA]); |
118c82e7 EJ |
379 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
380 | aspeed_soc_get_irq(s, ASPEED_XDMA)); | |
fdcc7c06 RG |
381 | |
382 | /* GPIO */ | |
668f62ec | 383 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
fdcc7c06 RG |
384 | return; |
385 | } | |
54ecafb7 | 386 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); |
fdcc7c06 RG |
387 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
388 | aspeed_soc_get_irq(s, ASPEED_GPIO)); | |
2bea128c EJ |
389 | |
390 | /* SDHCI */ | |
668f62ec | 391 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
2bea128c EJ |
392 | return; |
393 | } | |
394 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | |
54ecafb7 | 395 | sc->memmap[ASPEED_SDHCI]); |
2bea128c EJ |
396 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
397 | aspeed_soc_get_irq(s, ASPEED_SDHCI)); | |
43e3346e | 398 | } |
ece09bee | 399 | static Property aspeed_soc_properties[] = { |
95b56e17 CLG |
400 | DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, |
401 | MemoryRegion *), | |
ece09bee CLG |
402 | DEFINE_PROP_END_OF_LIST(), |
403 | }; | |
43e3346e | 404 | |
ff90606f | 405 | static void aspeed_soc_class_init(ObjectClass *oc, void *data) |
43e3346e AJ |
406 | { |
407 | DeviceClass *dc = DEVICE_CLASS(oc); | |
408 | ||
ff90606f | 409 | dc->realize = aspeed_soc_realize; |
469f3da4 TH |
410 | /* Reason: Uses serial_hds and nd_table in realize() directly */ |
411 | dc->user_creatable = false; | |
4f67d30b | 412 | device_class_set_props(dc, aspeed_soc_properties); |
43e3346e AJ |
413 | } |
414 | ||
ff90606f | 415 | static const TypeInfo aspeed_soc_type_info = { |
b033271f CLG |
416 | .name = TYPE_ASPEED_SOC, |
417 | .parent = TYPE_DEVICE, | |
b033271f CLG |
418 | .instance_size = sizeof(AspeedSoCState), |
419 | .class_size = sizeof(AspeedSoCClass), | |
54ecafb7 | 420 | .class_init = aspeed_soc_class_init, |
b033271f | 421 | .abstract = true, |
43e3346e AJ |
422 | }; |
423 | ||
54ecafb7 | 424 | static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) |
43e3346e | 425 | { |
54ecafb7 | 426 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); |
b033271f | 427 | |
54ecafb7 CLG |
428 | sc->name = "ast2400-a1"; |
429 | sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); | |
430 | sc->silicon_rev = AST2400_A1_SILICON_REV; | |
431 | sc->sram_size = 0x8000; | |
432 | sc->spis_num = 1; | |
bfdd34f1 | 433 | sc->ehcis_num = 1; |
54ecafb7 | 434 | sc->wdts_num = 2; |
d300db02 | 435 | sc->macs_num = 2; |
54ecafb7 CLG |
436 | sc->irqmap = aspeed_soc_ast2400_irqmap; |
437 | sc->memmap = aspeed_soc_ast2400_memmap; | |
438 | sc->num_cpus = 1; | |
439 | } | |
440 | ||
441 | static const TypeInfo aspeed_soc_ast2400_type_info = { | |
442 | .name = "ast2400-a1", | |
443 | .parent = TYPE_ASPEED_SOC, | |
444 | .instance_init = aspeed_soc_init, | |
445 | .instance_size = sizeof(AspeedSoCState), | |
446 | .class_init = aspeed_soc_ast2400_class_init, | |
447 | }; | |
448 | ||
449 | static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | |
450 | { | |
451 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | |
452 | ||
453 | sc->name = "ast2500-a1"; | |
454 | sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); | |
455 | sc->silicon_rev = AST2500_A1_SILICON_REV; | |
456 | sc->sram_size = 0x9000; | |
457 | sc->spis_num = 2; | |
bfdd34f1 | 458 | sc->ehcis_num = 2; |
54ecafb7 | 459 | sc->wdts_num = 3; |
d300db02 | 460 | sc->macs_num = 2; |
54ecafb7 CLG |
461 | sc->irqmap = aspeed_soc_ast2500_irqmap; |
462 | sc->memmap = aspeed_soc_ast2500_memmap; | |
463 | sc->num_cpus = 1; | |
43e3346e AJ |
464 | } |
465 | ||
54ecafb7 CLG |
466 | static const TypeInfo aspeed_soc_ast2500_type_info = { |
467 | .name = "ast2500-a1", | |
468 | .parent = TYPE_ASPEED_SOC, | |
469 | .instance_init = aspeed_soc_init, | |
470 | .instance_size = sizeof(AspeedSoCState), | |
471 | .class_init = aspeed_soc_ast2500_class_init, | |
472 | }; | |
473 | static void aspeed_soc_register_types(void) | |
474 | { | |
475 | type_register_static(&aspeed_soc_type_info); | |
476 | type_register_static(&aspeed_soc_ast2400_type_info); | |
477 | type_register_static(&aspeed_soc_ast2500_type_info); | |
478 | }; | |
479 | ||
ff90606f | 480 | type_init(aspeed_soc_register_types) |