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5fafdf24 1/*
16406950
PB
2 * ARM kernel loader.
3 *
9ee6e8bb 4 * Copyright (c) 2006-2007 CodeSourcery.
16406950
PB
5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the GPL.
16406950
PB
8 */
9
412beee6 10#include "config.h"
83c9f4ca 11#include "hw/hw.h"
bd2be150 12#include "hw/arm/arm.h"
9c17d615 13#include "sysemu/sysemu.h"
83c9f4ca
PB
14#include "hw/boards.h"
15#include "hw/loader.h"
ca20cf32 16#include "elf.h"
9c17d615 17#include "sysemu/device_tree.h"
1de7afc9 18#include "qemu/config-file.h"
16406950
PB
19
20#define KERNEL_ARGS_ADDR 0x100
21#define KERNEL_LOAD_ADDR 0x00010000
16406950
PB
22
23/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
24static uint32_t bootloader[] = {
25 0xe3a00000, /* mov r0, #0 */
f8414cb5
PM
26 0xe59f1004, /* ldr r1, [pc, #4] */
27 0xe59f2004, /* ldr r2, [pc, #4] */
28 0xe59ff004, /* ldr pc, [pc, #4] */
29 0, /* Board ID */
16406950
PB
30 0, /* Address of kernel args. Set by integratorcp_init. */
31 0 /* Kernel entry point. Set by integratorcp_init. */
32};
33
9d5ba9bf
ML
34/* Handling for secondary CPU boot in a multicore system.
35 * Unlike the uniprocessor/primary CPU boot, this is platform
36 * dependent. The default code here is based on the secondary
37 * CPU boot protocol used on realview/vexpress boards, with
38 * some parameterisation to increase its flexibility.
39 * QEMU platform models for which this code is not appropriate
40 * should override write_secondary_boot and secondary_cpu_reset_hook
41 * instead.
42 *
43 * This code enables the interrupt controllers for the secondary
44 * CPUs and then puts all the secondary CPUs into a loop waiting
45 * for an interprocessor interrupt and polling a configurable
46 * location for the kernel secondary CPU entry point.
47 */
bf471f79
PM
48#define DSB_INSN 0xf57ff04f
49#define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */
50
9ee6e8bb 51static uint32_t smpboot[] = {
bf471f79
PM
52 0xe59f2028, /* ldr r2, gic_cpu_if */
53 0xe59f0028, /* ldr r0, startaddr */
078758d0 54 0xe3a01001, /* mov r1, #1 */
bf471f79
PM
55 0xe5821000, /* str r1, [r2] - set GICC_CTLR.Enable */
56 0xe3a010ff, /* mov r1, #0xff */
57 0xe5821004, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */
58 DSB_INSN, /* dsb */
9ee6e8bb
PB
59 0xe320f003, /* wfi */
60 0xe5901000, /* ldr r1, [r0] */
be0f204a
PB
61 0xe1110001, /* tst r1, r1 */
62 0x0afffffb, /* beq <wfi> */
f7c70325 63 0xe12fff11, /* bx r1 */
96eacf64 64 0, /* gic_cpu_if: base address of GIC CPU interface */
078758d0 65 0 /* bootreg: Boot register address is held here */
9ee6e8bb
PB
66};
67
9543b0cd 68static void default_write_secondary(ARMCPU *cpu,
9d5ba9bf
ML
69 const struct arm_boot_info *info)
70{
71 int n;
72 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
96eacf64 73 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
9d5ba9bf 74 for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
bf471f79
PM
75 /* Replace DSB with the pre-v7 DSB if necessary. */
76 if (!arm_feature(&cpu->env, ARM_FEATURE_V7) &&
77 smpboot[n] == DSB_INSN) {
78 smpboot[n] = CP15_DSB_INSN;
79 }
9d5ba9bf
ML
80 smpboot[n] = tswap32(smpboot[n]);
81 }
82 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
83 info->smp_loader_start);
84}
85
5d309320 86static void default_reset_secondary(ARMCPU *cpu,
9d5ba9bf
ML
87 const struct arm_boot_info *info)
88{
5d309320
AF
89 CPUARMState *env = &cpu->env;
90
9d5ba9bf
ML
91 stl_phys_notdirty(info->smp_bootreg_addr, 0);
92 env->regs[15] = info->smp_loader_start;
93}
94
52b43737
PB
95#define WRITE_WORD(p, value) do { \
96 stl_phys_notdirty(p, value); \
97 p += 4; \
98} while (0)
99
761c9eb0 100static void set_kernel_args(const struct arm_boot_info *info)
16406950 101{
761c9eb0 102 int initrd_size = info->initrd_size;
a8170e5e
AK
103 hwaddr base = info->loader_start;
104 hwaddr p;
16406950 105
52b43737 106 p = base + KERNEL_ARGS_ADDR;
16406950 107 /* ATAG_CORE */
52b43737
PB
108 WRITE_WORD(p, 5);
109 WRITE_WORD(p, 0x54410001);
110 WRITE_WORD(p, 1);
111 WRITE_WORD(p, 0x1000);
112 WRITE_WORD(p, 0);
16406950 113 /* ATAG_MEM */
f93eb9ff 114 /* TODO: handle multiple chips on one ATAG list */
52b43737
PB
115 WRITE_WORD(p, 4);
116 WRITE_WORD(p, 0x54410002);
117 WRITE_WORD(p, info->ram_size);
118 WRITE_WORD(p, info->loader_start);
16406950
PB
119 if (initrd_size) {
120 /* ATAG_INITRD2 */
52b43737
PB
121 WRITE_WORD(p, 4);
122 WRITE_WORD(p, 0x54420005);
fc53b7d4 123 WRITE_WORD(p, info->initrd_start);
52b43737 124 WRITE_WORD(p, initrd_size);
16406950 125 }
f93eb9ff 126 if (info->kernel_cmdline && *info->kernel_cmdline) {
16406950
PB
127 /* ATAG_CMDLINE */
128 int cmdline_size;
129
f93eb9ff 130 cmdline_size = strlen(info->kernel_cmdline);
e1fe50dc 131 cpu_physical_memory_write(p + 8, info->kernel_cmdline,
52b43737 132 cmdline_size + 1);
16406950 133 cmdline_size = (cmdline_size >> 2) + 1;
52b43737
PB
134 WRITE_WORD(p, cmdline_size + 2);
135 WRITE_WORD(p, 0x54410009);
136 p += cmdline_size * 4;
16406950 137 }
f93eb9ff
AZ
138 if (info->atag_board) {
139 /* ATAG_BOARD */
140 int atag_board_len;
52b43737 141 uint8_t atag_board_buf[0x1000];
f93eb9ff 142
52b43737
PB
143 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
144 WRITE_WORD(p, (atag_board_len + 8) >> 2);
145 WRITE_WORD(p, 0x414f4d50);
146 cpu_physical_memory_write(p, atag_board_buf, atag_board_len);
f93eb9ff
AZ
147 p += atag_board_len;
148 }
16406950 149 /* ATAG_END */
52b43737
PB
150 WRITE_WORD(p, 0);
151 WRITE_WORD(p, 0);
16406950
PB
152}
153
761c9eb0 154static void set_kernel_args_old(const struct arm_boot_info *info)
2b8f2d41 155{
a8170e5e 156 hwaddr p;
52b43737 157 const char *s;
761c9eb0 158 int initrd_size = info->initrd_size;
a8170e5e 159 hwaddr base = info->loader_start;
2b8f2d41
AZ
160
161 /* see linux/include/asm-arm/setup.h */
52b43737 162 p = base + KERNEL_ARGS_ADDR;
2b8f2d41 163 /* page_size */
52b43737 164 WRITE_WORD(p, 4096);
2b8f2d41 165 /* nr_pages */
52b43737 166 WRITE_WORD(p, info->ram_size / 4096);
2b8f2d41 167 /* ramdisk_size */
52b43737 168 WRITE_WORD(p, 0);
2b8f2d41
AZ
169#define FLAG_READONLY 1
170#define FLAG_RDLOAD 4
171#define FLAG_RDPROMPT 8
172 /* flags */
52b43737 173 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
2b8f2d41 174 /* rootdev */
52b43737 175 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */
2b8f2d41 176 /* video_num_cols */
52b43737 177 WRITE_WORD(p, 0);
2b8f2d41 178 /* video_num_rows */
52b43737 179 WRITE_WORD(p, 0);
2b8f2d41 180 /* video_x */
52b43737 181 WRITE_WORD(p, 0);
2b8f2d41 182 /* video_y */
52b43737 183 WRITE_WORD(p, 0);
2b8f2d41 184 /* memc_control_reg */
52b43737 185 WRITE_WORD(p, 0);
2b8f2d41
AZ
186 /* unsigned char sounddefault */
187 /* unsigned char adfsdrives */
188 /* unsigned char bytes_per_char_h */
189 /* unsigned char bytes_per_char_v */
52b43737 190 WRITE_WORD(p, 0);
2b8f2d41 191 /* pages_in_bank[4] */
52b43737
PB
192 WRITE_WORD(p, 0);
193 WRITE_WORD(p, 0);
194 WRITE_WORD(p, 0);
195 WRITE_WORD(p, 0);
2b8f2d41 196 /* pages_in_vram */
52b43737 197 WRITE_WORD(p, 0);
2b8f2d41 198 /* initrd_start */
fc53b7d4
PM
199 if (initrd_size) {
200 WRITE_WORD(p, info->initrd_start);
201 } else {
52b43737 202 WRITE_WORD(p, 0);
fc53b7d4 203 }
2b8f2d41 204 /* initrd_size */
52b43737 205 WRITE_WORD(p, initrd_size);
2b8f2d41 206 /* rd_start */
52b43737 207 WRITE_WORD(p, 0);
2b8f2d41 208 /* system_rev */
52b43737 209 WRITE_WORD(p, 0);
2b8f2d41 210 /* system_serial_low */
52b43737 211 WRITE_WORD(p, 0);
2b8f2d41 212 /* system_serial_high */
52b43737 213 WRITE_WORD(p, 0);
2b8f2d41 214 /* mem_fclk_21285 */
52b43737 215 WRITE_WORD(p, 0);
2b8f2d41 216 /* zero unused fields */
52b43737
PB
217 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
218 WRITE_WORD(p, 0);
219 }
220 s = info->kernel_cmdline;
221 if (s) {
e1fe50dc 222 cpu_physical_memory_write(p, s, strlen(s) + 1);
52b43737
PB
223 } else {
224 WRITE_WORD(p, 0);
225 }
2b8f2d41
AZ
226}
227
a8170e5e 228static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo)
412beee6 229{
412beee6
GL
230 void *fdt = NULL;
231 char *filename;
232 int size, rc;
70976c41 233 uint32_t acells, scells;
412beee6
GL
234
235 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
236 if (!filename) {
237 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
c23045de 238 goto fail;
412beee6
GL
239 }
240
241 fdt = load_device_tree(filename, &size);
242 if (!fdt) {
243 fprintf(stderr, "Couldn't open dtb file %s\n", filename);
244 g_free(filename);
c23045de 245 goto fail;
412beee6
GL
246 }
247 g_free(filename);
248
9bfa659e
PM
249 acells = qemu_devtree_getprop_cell(fdt, "/", "#address-cells");
250 scells = qemu_devtree_getprop_cell(fdt, "/", "#size-cells");
251 if (acells == 0 || scells == 0) {
252 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
c23045de 253 goto fail;
9bfa659e
PM
254 }
255
70976c41
PM
256 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) {
257 /* This is user error so deserves a friendlier error message
258 * than the failure of setprop_sized_cells would provide
259 */
9bfa659e
PM
260 fprintf(stderr, "qemu: dtb file not compatible with "
261 "RAM size > 4GB\n");
c23045de 262 goto fail;
9bfa659e
PM
263 }
264
70976c41
PM
265 rc = qemu_devtree_setprop_sized_cells(fdt, "/memory", "reg",
266 acells, binfo->loader_start,
267 scells, binfo->ram_size);
412beee6
GL
268 if (rc < 0) {
269 fprintf(stderr, "couldn't set /memory/reg\n");
c23045de 270 goto fail;
412beee6
GL
271 }
272
5e87975c
PC
273 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) {
274 rc = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
275 binfo->kernel_cmdline);
276 if (rc < 0) {
277 fprintf(stderr, "couldn't set /chosen/bootargs\n");
c23045de 278 goto fail;
5e87975c 279 }
412beee6
GL
280 }
281
282 if (binfo->initrd_size) {
283 rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
fc53b7d4 284 binfo->initrd_start);
412beee6
GL
285 if (rc < 0) {
286 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
c23045de 287 goto fail;
412beee6
GL
288 }
289
290 rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
fc53b7d4 291 binfo->initrd_start + binfo->initrd_size);
412beee6
GL
292 if (rc < 0) {
293 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
c23045de 294 goto fail;
412beee6
GL
295 }
296 }
3b1cceb8
PM
297
298 if (binfo->modify_dtb) {
299 binfo->modify_dtb(binfo, fdt);
300 }
301
2acafb1a 302 qemu_devtree_dumpdtb(fdt, size);
412beee6
GL
303
304 cpu_physical_memory_write(addr, fdt, size);
305
c23045de
PM
306 g_free(fdt);
307
412beee6 308 return 0;
c23045de
PM
309
310fail:
311 g_free(fdt);
312 return -1;
412beee6
GL
313}
314
6ed221b6 315static void do_cpu_reset(void *opaque)
f2d74978 316{
351d5666
AF
317 ARMCPU *cpu = opaque;
318 CPUARMState *env = &cpu->env;
462a8bc6 319 const struct arm_boot_info *info = env->boot_info;
f2d74978 320
351d5666 321 cpu_reset(CPU(cpu));
f2d74978
PB
322 if (info) {
323 if (!info->is_linux) {
324 /* Jump to the entry point. */
325 env->regs[15] = info->entry & 0xfffffffe;
326 env->thumb = info->entry & 1;
327 } else {
182735ef 328 if (CPU(cpu) == first_cpu) {
6ed221b6 329 env->regs[15] = info->loader_start;
412beee6
GL
330 if (!info->dtb_filename) {
331 if (old_param) {
332 set_kernel_args_old(info);
333 } else {
334 set_kernel_args(info);
335 }
6ed221b6 336 }
f2d74978 337 } else {
5d309320 338 info->secondary_cpu_reset_hook(cpu, info);
f2d74978
PB
339 }
340 }
341 }
f2d74978
PB
342}
343
3aaa8dfa 344void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
16406950 345{
182735ef 346 CPUState *cs = CPU(cpu);
16406950
PB
347 int kernel_size;
348 int initrd_size;
349 int n;
1c7b3754
PB
350 int is_linux = 0;
351 uint64_t elf_entry;
a8170e5e 352 hwaddr entry;
ca20cf32 353 int big_endian;
16406950
PB
354
355 /* Load the kernel. */
f93eb9ff 356 if (!info->kernel_filename) {
16406950
PB
357 fprintf(stderr, "Kernel image must be specified\n");
358 exit(1);
359 }
daf90626 360
2ff3de68 361 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
412beee6 362
9d5ba9bf
ML
363 if (!info->secondary_cpu_reset_hook) {
364 info->secondary_cpu_reset_hook = default_reset_secondary;
365 }
366 if (!info->write_secondary_boot) {
367 info->write_secondary_boot = default_write_secondary;
368 }
369
f2d74978
PB
370 if (info->nb_cpus == 0)
371 info->nb_cpus = 1;
f93eb9ff 372
ca20cf32
BS
373#ifdef TARGET_WORDS_BIGENDIAN
374 big_endian = 1;
375#else
376 big_endian = 0;
377#endif
378
fc53b7d4
PM
379 /* We want to put the initrd far enough into RAM that when the
380 * kernel is uncompressed it will not clobber the initrd. However
381 * on boards without much RAM we must ensure that we still leave
382 * enough room for a decent sized initrd, and on boards with large
383 * amounts of RAM we must avoid the initrd being so far up in RAM
384 * that it is outside lowmem and inaccessible to the kernel.
385 * So for boards with less than 256MB of RAM we put the initrd
386 * halfway into RAM, and for boards with 256MB of RAM or more we put
387 * the initrd at 128MB.
388 */
389 info->initrd_start = info->loader_start +
390 MIN(info->ram_size / 2, 128 * 1024 * 1024);
391
1c7b3754 392 /* Assume that raw images are linux kernels, and ELF images are not. */
409dbce5
AJ
393 kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry,
394 NULL, NULL, big_endian, ELF_MACHINE, 1);
1c7b3754
PB
395 entry = elf_entry;
396 if (kernel_size < 0) {
5a9154e0
AL
397 kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
398 &is_linux);
1c7b3754
PB
399 }
400 if (kernel_size < 0) {
f93eb9ff 401 entry = info->loader_start + KERNEL_LOAD_ADDR;
3b760e04 402 kernel_size = load_image_targphys(info->kernel_filename, entry,
0b944384 403 info->ram_size - KERNEL_LOAD_ADDR);
1c7b3754
PB
404 is_linux = 1;
405 }
406 if (kernel_size < 0) {
f93eb9ff
AZ
407 fprintf(stderr, "qemu: could not load kernel '%s'\n",
408 info->kernel_filename);
1c7b3754
PB
409 exit(1);
410 }
f2d74978
PB
411 info->entry = entry;
412 if (is_linux) {
f93eb9ff 413 if (info->initrd_filename) {
fd76663e
SB
414 initrd_size = load_ramdisk(info->initrd_filename,
415 info->initrd_start,
416 info->ram_size -
417 info->initrd_start);
418 if (initrd_size < 0) {
419 initrd_size = load_image_targphys(info->initrd_filename,
420 info->initrd_start,
421 info->ram_size -
422 info->initrd_start);
423 }
daf90626
PB
424 if (initrd_size < 0) {
425 fprintf(stderr, "qemu: could not load initrd '%s'\n",
f93eb9ff 426 info->initrd_filename);
daf90626
PB
427 exit(1);
428 }
429 } else {
430 initrd_size = 0;
431 }
412beee6
GL
432 info->initrd_size = initrd_size;
433
f8414cb5 434 bootloader[4] = info->board_id;
412beee6
GL
435
436 /* for device tree boot, we pass the DTB directly in r2. Otherwise
437 * we point to the kernel args.
438 */
439 if (info->dtb_filename) {
98ed805c
PM
440 /* Place the DTB after the initrd in memory. Note that some
441 * kernels will trash anything in the 4K page the initrd
442 * ends in, so make sure the DTB isn't caught up in that.
443 */
444 hwaddr dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size,
445 4096);
412beee6
GL
446 if (load_dtb(dtb_start, info)) {
447 exit(1);
448 }
449 bootloader[5] = dtb_start;
450 } else {
451 bootloader[5] = info->loader_start + KERNEL_ARGS_ADDR;
3871481c
PM
452 if (info->ram_size >= (1ULL << 32)) {
453 fprintf(stderr, "qemu: RAM size must be less than 4GB to boot"
454 " Linux kernel using ATAGS (try passing a device tree"
455 " using -dtb)\n");
456 exit(1);
457 }
412beee6 458 }
1c7b3754 459 bootloader[6] = entry;
52b43737 460 for (n = 0; n < sizeof(bootloader) / 4; n++) {
f2d74978 461 bootloader[n] = tswap32(bootloader[n]);
52b43737 462 }
f2d74978
PB
463 rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader),
464 info->loader_start);
52b43737 465 if (info->nb_cpus > 1) {
9543b0cd 466 info->write_secondary_boot(cpu, info);
52b43737 467 }
16406950 468 }
f2d74978 469 info->is_linux = is_linux;
6ed221b6 470
bdc44640 471 for (; cs; cs = CPU_NEXT(cs)) {
182735ef
AF
472 cpu = ARM_CPU(cs);
473 cpu->env.boot_info = info;
351d5666 474 qemu_register_reset(do_cpu_reset, cpu);
6ed221b6 475 }
16406950 476}