[mirror_qemu.git] / hw / arm / fsl-imx25.c

/*
 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
 *
 * i.MX25 SOC emulation.
 *
 * Based on hw/arm/xlnx-zynqmp.c
 *
 * Copyright (C) 2015 Xilinx Inc
 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/arm/fsl-imx25.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
#include "hw/qdev-properties.h"
#include "chardev/char.h"

#define IMX25_ESDHC_CAPABILITIES     0x07e20000

static void fsl_imx25_init(Object *obj)
{
    FslIMX25State *s = FSL_IMX25(obj);
    int i;

    object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
                            ARM_CPU_TYPE_NAME("arm926"),
                            &error_abort, NULL);

    sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
                          TYPE_IMX_AVIC);

    sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);

    for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
        sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
                              TYPE_IMX_SERIAL);
    }

    for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
        sysbus_init_child_obj(obj, "gpt[*]", &s->gpt[i], sizeof(s->gpt[i]),
                              TYPE_IMX25_GPT);
    }

    for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
        sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
                              TYPE_IMX_EPIT);
    }

    sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC);

    sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc),
                          TYPE_IMX_RNGC);

    for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
        sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
                              TYPE_IMX_I2C);
    }

    for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
        sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
                              TYPE_IMX_GPIO);
    }

    for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
        sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
                              TYPE_IMX_USDHC);
    }

    for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
        sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]),
                              TYPE_CHIPIDEA);
    }

}

static void fsl_imx25_realize(DeviceState *dev, Error **errp)
{
    FslIMX25State *s = FSL_IMX25(dev);
    uint8_t i;
    Error *err = NULL;

    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));

    object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);

    /* Initialize all UARTs */
    for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } serial_table[FSL_IMX25_NUM_UARTS] = {
            { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
            { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
            { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
            { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
            { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
        };

        qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));

        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            serial_table[i].irq));
    }

    /* Initialize all GPT timers */
    for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } gpt_table[FSL_IMX25_NUM_GPTS] = {
            { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
            { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
            { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
            { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
        };

        s->gpt[i].ccm = IMX_CCM(&s->ccm);

        object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            gpt_table[i].irq));
    }

    /* Initialize all EPIT timers */
    for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } epit_table[FSL_IMX25_NUM_EPITS] = {
            { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
            { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
        };

        s->epit[i].ccm = IMX_CCM(&s->ccm);

        object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            epit_table[i].irq));
    }

    qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);

    object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
                       qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));

    object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0,
                       qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ));

    /* Initialize all I2C */
    for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } i2c_table[FSL_IMX25_NUM_I2CS] = {
            { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
            { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
            { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
        };

        object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            i2c_table[i].irq));
    }

    /* Initialize all GPIOs */
    for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } gpio_table[FSL_IMX25_NUM_GPIOS] = {
            { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
            { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
            { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
            { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
        };

        object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
        /* Connect GPIO IRQ to PIC */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            gpio_table[i].irq));
    }

    /* Initialize all SDHC */
    for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } esdhc_table[FSL_IMX25_NUM_ESDHCS] = {
            { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
            { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
        };

        object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version",
                                 &err);
        object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
                                 "capareg", &err);
        object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            esdhc_table[i].irq));
    }

    /* USB */
    for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } usb_table[FSL_IMX25_NUM_USBS] = {
            { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ },
            { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
        };

        object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
                                 &error_abort);
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            usb_table[i].irq));
    }

    /* initialize 2 x 16 KB ROM */
    memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
                           FSL_IMX25_ROM0_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
                                &s->rom[0]);
    memory_region_init_rom(&s->rom[1], OBJECT(dev), "imx25.rom1",
                           FSL_IMX25_ROM1_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
                                &s->rom[1]);

    /* initialize internal RAM (128 KB) */
    memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
                           &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
                                &s->iram);

    /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
    memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx25.iram_alias",
                             &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
                                &s->iram_alias);
}

static void fsl_imx25_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = fsl_imx25_realize;
    dc->desc = "i.MX25 SOC";
    /*
     * Reason: uses serial_hds in realize and the imx25 board does not
     * support multiple CPUs
     */
    dc->user_creatable = false;
}

static const TypeInfo fsl_imx25_type_info = {
    .name = TYPE_FSL_IMX25,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(FslIMX25State),
    .instance_init = fsl_imx25_init,
    .class_init = fsl_imx25_class_init,
};

static void fsl_imx25_register_types(void)
{
    type_register_static(&fsl_imx25_type_info);
}

type_init(fsl_imx25_register_types)
Commit	Line	Data
ee708c99 JCD	1	/*
	2	* Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
	3	*
	4	* i.MX25 SOC emulation.
	5	*
	6	* Based on hw/arm/xlnx-zynqmp.c
	7	*
	8	* Copyright (C) 2015 Xilinx Inc
	9	* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful, but WITHOUT
	17	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	18	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	19	* for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License along
	22	* with this program; if not, see <http://www.gnu.org/licenses/>.
	23	*/
	24
12b16722	25	#include "qemu/osdep.h"
da34e65c	26	#include "qapi/error.h"
4771d756	27	#include "cpu.h"
ee708c99 JCD	28	#include "hw/arm/fsl-imx25.h"
	29	#include "sysemu/sysemu.h"
	30	#include "exec/address-spaces.h"
a27bd6c7	31	#include "hw/qdev-properties.h"
8228e353	32	#include "chardev/char.h"
ee708c99	33
bfae1772 GR	34	#define IMX25_ESDHC_CAPABILITIES 0x07e20000
bfae1772 GR	35
ee708c99 JCD	36	static void fsl_imx25_init(Object *obj)
	37	{
	38	FslIMX25State *s = FSL_IMX25(obj);
	39	int i;
	40
eaa9a878 PMD	41	object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
	42	ARM_CPU_TYPE_NAME("arm926"),
	43	&error_abort, NULL);
ee708c99	44
51dd12ac TH	45	sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
51dd12ac TH	46	TYPE_IMX_AVIC);
ee708c99	47
51dd12ac	48	sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);
ee708c99 JCD	49
ee708c99 JCD	50	for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
51dd12ac TH	51	sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
51dd12ac TH	52	TYPE_IMX_SERIAL);
ee708c99 JCD	53	}
	54
	55	for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
51dd12ac TH	56	sysbus_init_child_obj(obj, "gpt[*]", &s->gpt[i], sizeof(s->gpt[i]),
51dd12ac TH	57	TYPE_IMX25_GPT);
ee708c99 JCD	58	}
	59
	60	for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
51dd12ac TH	61	sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
51dd12ac TH	62	TYPE_IMX_EPIT);
ee708c99 JCD	63	}
ee708c99 JCD	64
51dd12ac	65	sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC);
ee708c99	66
f0396549 MK	67	sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc),
	68	TYPE_IMX_RNGC);
	69
ee708c99	70	for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
51dd12ac TH	71	sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
51dd12ac TH	72	TYPE_IMX_I2C);
ee708c99	73	}
6abc7158 JCD	74
6abc7158 JCD	75	for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
51dd12ac TH	76	sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
51dd12ac TH	77	TYPE_IMX_GPIO);
6abc7158	78	}
bfae1772 GR	79
	80	for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
	81	sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
	82	TYPE_IMX_USDHC);
	83	}
67f52ebe GR	84
	85	for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
	86	sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]),
	87	TYPE_CHIPIDEA);
	88	}
	89
ee708c99 JCD	90	}
	91
	92	static void fsl_imx25_realize(DeviceState dev, Error *errp)
	93	{
	94	FslIMX25State *s = FSL_IMX25(dev);
	95	uint8_t i;
	96	Error *err = NULL;
	97
	98	object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
	99	if (err) {
	100	error_propagate(errp, err);
	101	return;
	102	}
	103
	104	object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
	105	if (err) {
	106	error_propagate(errp, err);
	107	return;
	108	}
	109	sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
	110	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
	111	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
	112	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
	113	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
	114
	115	object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
	116	if (err) {
	117	error_propagate(errp, err);
	118	return;
	119	}
	120	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
	121
	122	/* Initialize all UARTs */
	123	for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
	124	static const struct {
	125	hwaddr addr;
	126	unsigned int irq;
	127	} serial_table[FSL_IMX25_NUM_UARTS] = {
	128	{ FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
	129	{ FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
	130	{ FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
	131	{ FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
	132	{ FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
	133	};
	134
fc38a112	135	qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
ee708c99 JCD	136
	137	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
	138	if (err) {
	139	error_propagate(errp, err);
	140	return;
	141	}
	142	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
	143	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	144	qdev_get_gpio_in(DEVICE(&s->avic),
	145	serial_table[i].irq));
	146	}
	147
	148	/* Initialize all GPT timers */
	149	for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
	150	static const struct {
	151	hwaddr addr;
	152	unsigned int irq;
	153	} gpt_table[FSL_IMX25_NUM_GPTS] = {
	154	{ FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
	155	{ FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
	156	{ FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
	157	{ FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
	158	};
	159
cb54d868	160	s->gpt[i].ccm = IMX_CCM(&s->ccm);
ee708c99 JCD	161
	162	object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
	163	if (err) {
	164	error_propagate(errp, err);
	165	return;
	166	}
	167	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
	168	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
	169	qdev_get_gpio_in(DEVICE(&s->avic),
	170	gpt_table[i].irq));
	171	}
	172
	173	/* Initialize all EPIT timers */
	174	for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
	175	static const struct {
	176	hwaddr addr;
	177	unsigned int irq;
	178	} epit_table[FSL_IMX25_NUM_EPITS] = {
	179	{ FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
	180	{ FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
	181	};
	182
cb54d868	183	s->epit[i].ccm = IMX_CCM(&s->ccm);
ee708c99 JCD	184
	185	object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
	186	if (err) {
	187	error_propagate(errp, err);
	188	return;
	189	}
	190	sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
	191	sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
	192	qdev_get_gpio_in(DEVICE(&s->avic),
	193	epit_table[i].irq));
	194	}
	195
	196	qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
a699b410	197
ee708c99 JCD	198	object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
	199	if (err) {
	200	error_propagate(errp, err);
	201	return;
	202	}
	203	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
	204	sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
	205	qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
	206
f0396549 MK	207	object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err);
	208	if (err) {
	209	error_propagate(errp, err);
	210	return;
	211	}
	212	sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR);
	213	sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0,
	214	qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ));
ee708c99 JCD	215
	216	/* Initialize all I2C */
	217	for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
	218	static const struct {
	219	hwaddr addr;
	220	unsigned int irq;
	221	} i2c_table[FSL_IMX25_NUM_I2CS] = {
	222	{ FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
	223	{ FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
	224	{ FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
	225	};
	226
	227	object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
	228	if (err) {
	229	error_propagate(errp, err);
	230	return;
	231	}
	232	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
	233	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
	234	qdev_get_gpio_in(DEVICE(&s->avic),
	235	i2c_table[i].irq));
	236	}
	237
6abc7158 JCD	238	/* Initialize all GPIOs */
	239	for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
	240	static const struct {
	241	hwaddr addr;
	242	unsigned int irq;
	243	} gpio_table[FSL_IMX25_NUM_GPIOS] = {
	244	{ FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
	245	{ FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
	246	{ FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
	247	{ FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
	248	};
	249
	250	object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
	251	if (err) {
	252	error_propagate(errp, err);
	253	return;
	254	}
	255	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
	256	/* Connect GPIO IRQ to PIC */
	257	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
	258	qdev_get_gpio_in(DEVICE(&s->avic),
	259	gpio_table[i].irq));
	260	}
	261
bfae1772 GR	262	/* Initialize all SDHC */
	263	for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
	264	static const struct {
	265	hwaddr addr;
	266	unsigned int irq;
	267	} esdhc_table[FSL_IMX25_NUM_ESDHCS] = {
	268	{ FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
	269	{ FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
	270	};
	271
	272	object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version",
	273	&err);
	274	object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
	275	"capareg", &err);
	276	object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
	277	if (err) {
	278	error_propagate(errp, err);
	279	return;
	280	}
	281	sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
	282	sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
	283	qdev_get_gpio_in(DEVICE(&s->avic),
	284	esdhc_table[i].irq));
	285	}
	286
67f52ebe GR	287	/* USB */
	288	for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
	289	static const struct {
	290	hwaddr addr;
	291	unsigned int irq;
	292	} usb_table[FSL_IMX25_NUM_USBS] = {
	293	{ FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ },
	294	{ FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
	295	};
	296
	297	object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
	298	&error_abort);
	299	sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
	300	sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
	301	qdev_get_gpio_in(DEVICE(&s->avic),
	302	usb_table[i].irq));
	303	}
	304
ee708c99	305	/* initialize 2 x 16 KB ROM */
32b9523a PMD	306	memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
32b9523a PMD	307	FSL_IMX25_ROM0_SIZE, &err);
ee708c99 JCD	308	if (err) {
	309	error_propagate(errp, err);
	310	return;
	311	}
	312	memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
	313	&s->rom[0]);
32b9523a PMD	314	memory_region_init_rom(&s->rom[1], OBJECT(dev), "imx25.rom1",
32b9523a PMD	315	FSL_IMX25_ROM1_SIZE, &err);
ee708c99 JCD	316	if (err) {
	317	error_propagate(errp, err);
	318	return;
	319	}
	320	memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
	321	&s->rom[1]);
	322
	323	/* initialize internal RAM (128 KB) */
98a99ce0	324	memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
ee708c99 JCD	325	&err);
	326	if (err) {
	327	error_propagate(errp, err);
	328	return;
	329	}
	330	memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
	331	&s->iram);
ee708c99 JCD	332
ee708c99 JCD	333	/* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
32b9523a	334	memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx25.iram_alias",
ee708c99 JCD	335	&s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
	336	memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
	337	&s->iram_alias);
	338	}
	339
	340	static void fsl_imx25_class_init(ObjectClass oc, void data)
	341	{
	342	DeviceClass *dc = DEVICE_CLASS(oc);
	343
	344	dc->realize = fsl_imx25_realize;
eccfa35e	345	dc->desc = "i.MX25 SOC";
5e0c7044 TH	346	/*
	347	* Reason: uses serial_hds in realize and the imx25 board does not
	348	* support multiple CPUs
	349	*/
	350	dc->user_creatable = false;
ee708c99 JCD	351	}
	352
	353	static const TypeInfo fsl_imx25_type_info = {
	354	.name = TYPE_FSL_IMX25,
	355	.parent = TYPE_DEVICE,
	356	.instance_size = sizeof(FslIMX25State),
	357	.instance_init = fsl_imx25_init,
	358	.class_init = fsl_imx25_class_init,
	359	};
	360
	361	static void fsl_imx25_register_types(void)
	362	{
	363	type_register_static(&fsl_imx25_type_info);
	364	}
	365
	366	type_init(fsl_imx25_register_types)