[mirror_qemu.git] / hw / arm / nrf51_soc.c

/*
 * Nordic Semiconductor nRF51 SoC
 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
 *
 * Copyright 2018 Joel Stanley <joel@jms.id.au>
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/boot.h"
#include "hw/sysbus.h"
#include "hw/misc/unimp.h"
#include "exec/address-spaces.h"
#include "qemu/log.h"

#include "hw/arm/nrf51.h"
#include "hw/arm/nrf51_soc.h"

/*
 * The size and base is for the NRF51822 part. If other parts
 * are supported in the future, add a sub-class of NRF51SoC for
 * the specific variants
 */
#define NRF51822_FLASH_PAGES    256
#define NRF51822_SRAM_PAGES     16
#define NRF51822_FLASH_SIZE     (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE)
#define NRF51822_SRAM_SIZE      (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE)

#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)

/* HCLK (the main CPU clock) on this SoC is always 16MHz */
#define HCLK_FRQ 16000000

static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
{
    qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
                  __func__, addr, size);
    return 1;
}

static void clock_write(void *opaque, hwaddr addr, uint64_t data,
                        unsigned int size)
{
    qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
                  __func__, addr, data, size);
}

static const MemoryRegionOps clock_ops = {
    .read = clock_read,
    .write = clock_write
};


static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
{
    NRF51State *s = NRF51_SOC(dev_soc);
    MemoryRegion *mr;
    Error *err = NULL;
    uint8_t i = 0;
    hwaddr base_addr = 0;

    if (!s->board_memory) {
        error_setg(errp, "memory property was not set");
        return;
    }

    system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ;

    object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
                             &error_abort);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
        return;
    }

    memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);

    memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
                           &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);

    /* UART */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
        return;
    }
    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
    memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu),
                       BASE_TO_IRQ(NRF51_UART_BASE)));

    /* RNG */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) {
        return;
    }

    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
    memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu),
                       BASE_TO_IRQ(NRF51_RNG_BASE)));

    /* UICR, FICR, NVMC, FLASH */
    if (!object_property_set_uint(OBJECT(&s->nvm), "flash-size",
                                  s->flash_size, errp)) {
        return;
    }

    if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), errp)) {
        return;
    }

    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
    memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
    memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
    memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
    memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);

    /* GPIO */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
        return;
    }

    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
    memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);

    /* Pass all GPIOs to the SOC layer so they are available to the board */
    qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);

    /* TIMER */
    for (i = 0; i < NRF51_NUM_TIMERS; i++) {
        if (!object_property_set_uint(OBJECT(&s->timer[i]), "id", i, errp)) {
            return;
        }
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {
            return;
        }

        base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->cpu),
                                            BASE_TO_IRQ(base_addr)));
    }

    /* STUB Peripherals */
    memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
                          "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
    memory_region_add_subregion_overlap(&s->container,
                                        NRF51_IOMEM_BASE, &s->clock, -1);

    create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE,
                                NRF51_IOMEM_SIZE);
    create_unimplemented_device("nrf51_soc.private",
                                NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE);
}

static void nrf51_soc_init(Object *obj)
{
    uint8_t i = 0;

    NRF51State *s = NRF51_SOC(obj);

    memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);

    object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
    qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
                         ARM_CPU_TYPE_NAME("cortex-m0"));
    qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);

    object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
    object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");

    object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG);

    object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM);

    object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO);

    for (i = 0; i < NRF51_NUM_TIMERS; i++) {
        object_initialize_child(obj, "timer[*]", &s->timer[i],
                                TYPE_NRF51_TIMER);

    }
}

static Property nrf51_soc_properties[] = {
    DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
                     MemoryRegion *),
    DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
    DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
                       NRF51822_FLASH_SIZE),
    DEFINE_PROP_END_OF_LIST(),
};

static void nrf51_soc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = nrf51_soc_realize;
    device_class_set_props(dc, nrf51_soc_properties);
}

static const TypeInfo nrf51_soc_info = {
    .name          = TYPE_NRF51_SOC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(NRF51State),
    .instance_init = nrf51_soc_init,
    .class_init    = nrf51_soc_class_init,
};

static void nrf51_soc_types(void)
{
    type_register_static(&nrf51_soc_info);
}
type_init(nrf51_soc_types)
Commit	Line	Data
673b2d42 JS	1	/*
	2	* Nordic Semiconductor nRF51 SoC
	3	* http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
	4	*
	5	* Copyright 2018 Joel Stanley <joel@jms.id.au>
	6	*
	7	* This code is licensed under the GPL version 2 or later. See
	8	* the COPYING file in the top-level directory.
	9	*/
	10
	11	#include "qemu/osdep.h"
	12	#include "qapi/error.h"
12ec8bd5	13	#include "hw/arm/boot.h"
673b2d42	14	#include "hw/sysbus.h"
673b2d42 JS	15	#include "hw/misc/unimp.h"
673b2d42 JS	16	#include "exec/address-spaces.h"
673b2d42	17	#include "qemu/log.h"
673b2d42	18
659b85e4	19	#include "hw/arm/nrf51.h"
673b2d42 JS	20	#include "hw/arm/nrf51_soc.h"
673b2d42 JS	21
673b2d42 JS	22	/*
	23	* The size and base is for the NRF51822 part. If other parts
	24	* are supported in the future, add a sub-class of NRF51SoC for
	25	* the specific variants
	26	*/
4d744b25 SG	27	#define NRF51822_FLASH_PAGES 256
	28	#define NRF51822_SRAM_PAGES 16
	29	#define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE)
	30	#define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE)
673b2d42	31
b0014913 JS	32	#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
b0014913 JS	33
ce4f70e8 PM	34	/* HCLK (the main CPU clock) on this SoC is always 16MHz */
	35	#define HCLK_FRQ 16000000
	36
b39dced6 SG	37	static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
	38	{
	39	qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
	40	__func__, addr, size);
	41	return 1;
	42	}
	43
	44	static void clock_write(void *opaque, hwaddr addr, uint64_t data,
	45	unsigned int size)
	46	{
	47	qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
	48	__func__, addr, data, size);
	49	}
	50
	51	static const MemoryRegionOps clock_ops = {
	52	.read = clock_read,
	53	.write = clock_write
	54	};
	55
	56
673b2d42 JS	57	static void nrf51_soc_realize(DeviceState dev_soc, Error *errp)
	58	{
	59	NRF51State *s = NRF51_SOC(dev_soc);
b0014913	60	MemoryRegion *mr;
673b2d42	61	Error *err = NULL;
60facd90 SG	62	uint8_t i = 0;
60facd90 SG	63	hwaddr base_addr = 0;
673b2d42 JS	64
	65	if (!s->board_memory) {
	66	error_setg(errp, "memory property was not set");
	67	return;
	68	}
	69
ce4f70e8 PM	70	system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ;
ce4f70e8 PM	71
5325cc34	72	object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
c24d9716	73	&error_abort);
668f62ec	74	if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
673b2d42 JS	75	return;
	76	}
	77
	78	memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
	79
287a7f6e	80	memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
287a7f6e	81	&err);
673b2d42 JS	82	if (err) {
	83	error_propagate(errp, err);
	84	return;
	85	}
659b85e4	86	memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);
673b2d42	87
b0014913	88	/* UART */
668f62ec	89	if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
b0014913 JS	90	return;
	91	}
	92	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
659b85e4	93	memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
b0014913 JS	94	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
b0014913 JS	95	qdev_get_gpio_in(DEVICE(&s->cpu),
659b85e4	96	BASE_TO_IRQ(NRF51_UART_BASE)));
b0014913	97
f30890de	98	/* RNG */
668f62ec	99	if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) {
f30890de SG	100	return;
	101	}
	102
	103	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
	104	memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
	105	sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
	106	qdev_get_gpio_in(DEVICE(&s->cpu),
	107	BASE_TO_IRQ(NRF51_RNG_BASE)));
	108
4d744b25	109	/* UICR, FICR, NVMC, FLASH */
778a2dc5	110	if (!object_property_set_uint(OBJECT(&s->nvm), "flash-size",
668f62ec	111	s->flash_size, errp)) {
4d744b25 SG	112	return;
	113	}
	114
668f62ec	115	if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), errp)) {
4d744b25 SG	116	return;
	117	}
	118
	119	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
	120	memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
	121	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
	122	memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
	123	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
	124	memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
	125	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
	126	memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);
	127
bb42c4cb	128	/* GPIO */
668f62ec	129	if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
bb42c4cb SG	130	return;
	131	}
	132
	133	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
	134	memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);
	135
	136	/* Pass all GPIOs to the SOC layer so they are available to the board */
	137	qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);
	138
60facd90 SG	139	/* TIMER */
60facd90 SG	140	for (i = 0; i < NRF51_NUM_TIMERS; i++) {
668f62ec	141	if (!object_property_set_uint(OBJECT(&s->timer[i]), "id", i, errp)) {
27d6dea3 PMD	142	return;
27d6dea3 PMD	143	}
668f62ec	144	if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {
60facd90 SG	145	return;
	146	}
	147
54595a57	148	base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
60facd90 SG	149
	150	sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
	151	sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
	152	qdev_get_gpio_in(DEVICE(&s->cpu),
	153	BASE_TO_IRQ(base_addr)));
	154	}
	155
b39dced6	156	/* STUB Peripherals */
32b9523a	157	memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
54595a57	158	"nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
b39dced6 SG	159	memory_region_add_subregion_overlap(&s->container,
	160	NRF51_IOMEM_BASE, &s->clock, -1);
	161
659b85e4 SG	162	create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE,
659b85e4 SG	163	NRF51_IOMEM_SIZE);
673b2d42	164	create_unimplemented_device("nrf51_soc.private",
659b85e4	165	NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE);
673b2d42 JS	166	}
	167
	168	static void nrf51_soc_init(Object *obj)
	169	{
60facd90 SG	170	uint8_t i = 0;
60facd90 SG	171
673b2d42 JS	172	NRF51State *s = NRF51_SOC(obj);
	173
	174	memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
	175
db873cc5	176	object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
673b2d42 JS	177	qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
	178	ARM_CPU_TYPE_NAME("cortex-m0"));
	179	qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
b0014913	180
db873cc5	181	object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
d2623129	182	object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
f30890de	183
db873cc5	184	object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG);
bb42c4cb	185
db873cc5	186	object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM);
4d744b25	187
db873cc5	188	object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO);
60facd90 SG	189
60facd90 SG	190	for (i = 0; i < NRF51_NUM_TIMERS; i++) {
db873cc5 MA	191	object_initialize_child(obj, "timer[*]", &s->timer[i],
db873cc5 MA	192	TYPE_NRF51_TIMER);
60facd90 SG	193
60facd90 SG	194	}
673b2d42 JS	195	}
	196
	197	static Property nrf51_soc_properties[] = {
	198	DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
	199	MemoryRegion *),
	200	DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
	201	DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
	202	NRF51822_FLASH_SIZE),
	203	DEFINE_PROP_END_OF_LIST(),
	204	};
	205
	206	static void nrf51_soc_class_init(ObjectClass klass, void data)
	207	{
	208	DeviceClass *dc = DEVICE_CLASS(klass);
	209
	210	dc->realize = nrf51_soc_realize;
4f67d30b	211	device_class_set_props(dc, nrf51_soc_properties);
673b2d42 JS	212	}
	213
	214	static const TypeInfo nrf51_soc_info = {
	215	.name = TYPE_NRF51_SOC,
	216	.parent = TYPE_SYS_BUS_DEVICE,
	217	.instance_size = sizeof(NRF51State),
	218	.instance_init = nrf51_soc_init,
	219	.class_init = nrf51_soc_class_init,
	220	};
	221
	222	static void nrf51_soc_types(void)
	223	{
	224	type_register_static(&nrf51_soc_info);
	225	}
	226	type_init(nrf51_soc_types)