]>
Commit | Line | Data |
---|---|---|
64580903 HZ |
1 | /* |
2 | * ARM SBSA Reference Platform emulation | |
3 | * | |
4 | * Copyright (c) 2018 Linaro Limited | |
5 | * Written by Hongbo Zhang <hongbo.zhang@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
e9fdf453 | 21 | #include "qemu-common.h" |
64580903 HZ |
22 | #include "qapi/error.h" |
23 | #include "qemu/error-report.h" | |
24 | #include "qemu/units.h" | |
e9fdf453 | 25 | #include "sysemu/device_tree.h" |
64580903 HZ |
26 | #include "sysemu/numa.h" |
27 | #include "sysemu/sysemu.h" | |
28 | #include "exec/address-spaces.h" | |
29 | #include "exec/hwaddr.h" | |
30 | #include "kvm_arm.h" | |
31 | #include "hw/arm/boot.h" | |
e9fdf453 | 32 | #include "hw/block/flash.h" |
64580903 | 33 | #include "hw/boards.h" |
e9fdf453 HZ |
34 | #include "hw/ide/internal.h" |
35 | #include "hw/ide/ahci_internal.h" | |
64580903 | 36 | #include "hw/intc/arm_gicv3_common.h" |
e9fdf453 HZ |
37 | #include "hw/loader.h" |
38 | #include "hw/pci-host/gpex.h" | |
39 | #include "hw/usb.h" | |
40 | #include "net/net.h" | |
64580903 HZ |
41 | |
42 | #define RAMLIMIT_GB 8192 | |
43 | #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) | |
44 | ||
e9fdf453 HZ |
45 | #define NUM_IRQS 256 |
46 | #define NUM_SMMU_IRQS 4 | |
47 | #define NUM_SATA_PORTS 6 | |
48 | ||
49 | #define VIRTUAL_PMU_IRQ 7 | |
50 | #define ARCH_GIC_MAINT_IRQ 9 | |
51 | #define ARCH_TIMER_VIRT_IRQ 11 | |
52 | #define ARCH_TIMER_S_EL1_IRQ 13 | |
53 | #define ARCH_TIMER_NS_EL1_IRQ 14 | |
54 | #define ARCH_TIMER_NS_EL2_IRQ 10 | |
55 | ||
64580903 HZ |
56 | enum { |
57 | SBSA_FLASH, | |
58 | SBSA_MEM, | |
59 | SBSA_CPUPERIPHS, | |
60 | SBSA_GIC_DIST, | |
61 | SBSA_GIC_REDIST, | |
62 | SBSA_SMMU, | |
63 | SBSA_UART, | |
64 | SBSA_RTC, | |
65 | SBSA_PCIE, | |
66 | SBSA_PCIE_MMIO, | |
67 | SBSA_PCIE_MMIO_HIGH, | |
68 | SBSA_PCIE_PIO, | |
69 | SBSA_PCIE_ECAM, | |
70 | SBSA_GPIO, | |
71 | SBSA_SECURE_UART, | |
72 | SBSA_SECURE_UART_MM, | |
73 | SBSA_SECURE_MEM, | |
74 | SBSA_AHCI, | |
75 | SBSA_EHCI, | |
76 | }; | |
77 | ||
78 | typedef struct MemMapEntry { | |
79 | hwaddr base; | |
80 | hwaddr size; | |
81 | } MemMapEntry; | |
82 | ||
83 | typedef struct { | |
84 | MachineState parent; | |
85 | struct arm_boot_info bootinfo; | |
86 | int smp_cpus; | |
87 | void *fdt; | |
88 | int fdt_size; | |
89 | int psci_conduit; | |
e9fdf453 | 90 | PFlashCFI01 *flash[2]; |
64580903 HZ |
91 | } SBSAMachineState; |
92 | ||
93 | #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") | |
94 | #define SBSA_MACHINE(obj) \ | |
95 | OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE) | |
96 | ||
97 | static const MemMapEntry sbsa_ref_memmap[] = { | |
98 | /* 512M boot ROM */ | |
99 | [SBSA_FLASH] = { 0, 0x20000000 }, | |
100 | /* 512M secure memory */ | |
101 | [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, | |
102 | /* Space reserved for CPU peripheral devices */ | |
103 | [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, | |
104 | [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, | |
105 | [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, | |
106 | [SBSA_UART] = { 0x60000000, 0x00001000 }, | |
107 | [SBSA_RTC] = { 0x60010000, 0x00001000 }, | |
108 | [SBSA_GPIO] = { 0x60020000, 0x00001000 }, | |
109 | [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, | |
110 | [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, | |
111 | [SBSA_SMMU] = { 0x60050000, 0x00020000 }, | |
112 | /* Space here reserved for more SMMUs */ | |
113 | [SBSA_AHCI] = { 0x60100000, 0x00010000 }, | |
114 | [SBSA_EHCI] = { 0x60110000, 0x00010000 }, | |
115 | /* Space here reserved for other devices */ | |
116 | [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, | |
117 | /* 32-bit address PCIE MMIO space */ | |
118 | [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, | |
119 | /* 256M PCIE ECAM space */ | |
120 | [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, | |
121 | /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ | |
122 | [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, | |
123 | [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, | |
124 | }; | |
125 | ||
e9fdf453 HZ |
126 | static const int sbsa_ref_irqmap[] = { |
127 | [SBSA_UART] = 1, | |
128 | [SBSA_RTC] = 2, | |
129 | [SBSA_PCIE] = 3, /* ... to 6 */ | |
130 | [SBSA_GPIO] = 7, | |
131 | [SBSA_SECURE_UART] = 8, | |
132 | [SBSA_SECURE_UART_MM] = 9, | |
133 | [SBSA_AHCI] = 10, | |
134 | [SBSA_EHCI] = 11, | |
135 | }; | |
136 | ||
137 | /* | |
138 | * Firmware on this machine only uses ACPI table to load OS, these limited | |
139 | * device tree nodes are just to let firmware know the info which varies from | |
140 | * command line parameters, so it is not necessary to be fully compatible | |
141 | * with the kernel CPU and NUMA binding rules. | |
142 | */ | |
143 | static void create_fdt(SBSAMachineState *sms) | |
144 | { | |
145 | void *fdt = create_device_tree(&sms->fdt_size); | |
146 | const MachineState *ms = MACHINE(sms); | |
147 | int cpu; | |
148 | ||
149 | if (!fdt) { | |
150 | error_report("create_device_tree() failed"); | |
151 | exit(1); | |
152 | } | |
153 | ||
154 | sms->fdt = fdt; | |
155 | ||
156 | qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); | |
157 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
158 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
159 | ||
160 | if (have_numa_distance) { | |
161 | int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); | |
162 | uint32_t *matrix = g_malloc0(size); | |
163 | int idx, i, j; | |
164 | ||
165 | for (i = 0; i < nb_numa_nodes; i++) { | |
166 | for (j = 0; j < nb_numa_nodes; j++) { | |
167 | idx = (i * nb_numa_nodes + j) * 3; | |
168 | matrix[idx + 0] = cpu_to_be32(i); | |
169 | matrix[idx + 1] = cpu_to_be32(j); | |
170 | matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); | |
171 | } | |
172 | } | |
173 | ||
174 | qemu_fdt_add_subnode(fdt, "/distance-map"); | |
175 | qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", | |
176 | matrix, size); | |
177 | g_free(matrix); | |
178 | } | |
179 | ||
180 | qemu_fdt_add_subnode(sms->fdt, "/cpus"); | |
181 | ||
182 | for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { | |
183 | char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); | |
184 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | |
185 | CPUState *cs = CPU(armcpu); | |
186 | ||
187 | qemu_fdt_add_subnode(sms->fdt, nodename); | |
188 | ||
189 | if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { | |
190 | qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", | |
191 | ms->possible_cpus->cpus[cs->cpu_index].props.node_id); | |
192 | } | |
193 | ||
194 | g_free(nodename); | |
195 | } | |
196 | } | |
197 | ||
198 | #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) | |
199 | ||
200 | static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, | |
201 | const char *name, | |
202 | const char *alias_prop_name) | |
203 | { | |
204 | /* | |
205 | * Create a single flash device. We use the same parameters as | |
206 | * the flash devices on the Versatile Express board. | |
207 | */ | |
208 | DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); | |
209 | ||
210 | qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); | |
211 | qdev_prop_set_uint8(dev, "width", 4); | |
212 | qdev_prop_set_uint8(dev, "device-width", 2); | |
213 | qdev_prop_set_bit(dev, "big-endian", false); | |
214 | qdev_prop_set_uint16(dev, "id0", 0x89); | |
215 | qdev_prop_set_uint16(dev, "id1", 0x18); | |
216 | qdev_prop_set_uint16(dev, "id2", 0x00); | |
217 | qdev_prop_set_uint16(dev, "id3", 0x00); | |
218 | qdev_prop_set_string(dev, "name", name); | |
219 | object_property_add_child(OBJECT(sms), name, OBJECT(dev), | |
220 | &error_abort); | |
221 | object_property_add_alias(OBJECT(sms), alias_prop_name, | |
222 | OBJECT(dev), "drive", &error_abort); | |
223 | return PFLASH_CFI01(dev); | |
224 | } | |
225 | ||
226 | static void sbsa_flash_create(SBSAMachineState *sms) | |
227 | { | |
228 | sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); | |
229 | sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); | |
230 | } | |
231 | ||
232 | static void sbsa_flash_map1(PFlashCFI01 *flash, | |
233 | hwaddr base, hwaddr size, | |
234 | MemoryRegion *sysmem) | |
235 | { | |
236 | DeviceState *dev = DEVICE(flash); | |
237 | ||
238 | assert(size % SBSA_FLASH_SECTOR_SIZE == 0); | |
239 | assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); | |
240 | qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); | |
241 | qdev_init_nofail(dev); | |
242 | ||
243 | memory_region_add_subregion(sysmem, base, | |
244 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), | |
245 | 0)); | |
246 | } | |
247 | ||
248 | static void sbsa_flash_map(SBSAMachineState *sms, | |
249 | MemoryRegion *sysmem, | |
250 | MemoryRegion *secure_sysmem) | |
251 | { | |
252 | /* | |
253 | * Map two flash devices to fill the SBSA_FLASH space in the memmap. | |
254 | * sysmem is the system memory space. secure_sysmem is the secure view | |
255 | * of the system, and the first flash device should be made visible only | |
256 | * there. The second flash device is visible to both secure and nonsecure. | |
e9fdf453 HZ |
257 | */ |
258 | hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; | |
259 | hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; | |
260 | ||
261 | sbsa_flash_map1(sms->flash[0], flashbase, flashsize, | |
262 | secure_sysmem); | |
263 | sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, | |
264 | sysmem); | |
265 | } | |
266 | ||
267 | static bool sbsa_firmware_init(SBSAMachineState *sms, | |
268 | MemoryRegion *sysmem, | |
269 | MemoryRegion *secure_sysmem) | |
270 | { | |
271 | int i; | |
272 | BlockBackend *pflash_blk0; | |
273 | ||
274 | /* Map legacy -drive if=pflash to machine properties */ | |
275 | for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { | |
276 | pflash_cfi01_legacy_drive(sms->flash[i], | |
277 | drive_get(IF_PFLASH, 0, i)); | |
278 | } | |
279 | ||
280 | sbsa_flash_map(sms, sysmem, secure_sysmem); | |
281 | ||
282 | pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); | |
283 | ||
284 | if (bios_name) { | |
285 | char *fname; | |
286 | MemoryRegion *mr; | |
287 | int image_size; | |
288 | ||
289 | if (pflash_blk0) { | |
290 | error_report("The contents of the first flash device may be " | |
291 | "specified with -bios or with -drive if=pflash... " | |
292 | "but you cannot use both options at once"); | |
293 | exit(1); | |
294 | } | |
295 | ||
296 | /* Fall back to -bios */ | |
297 | ||
298 | fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
299 | if (!fname) { | |
300 | error_report("Could not find ROM image '%s'", bios_name); | |
301 | exit(1); | |
302 | } | |
303 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); | |
304 | image_size = load_image_mr(fname, mr); | |
305 | g_free(fname); | |
306 | if (image_size < 0) { | |
307 | error_report("Could not load ROM image '%s'", bios_name); | |
308 | exit(1); | |
309 | } | |
310 | } | |
311 | ||
312 | return pflash_blk0 || bios_name; | |
313 | } | |
314 | ||
315 | static void create_secure_ram(SBSAMachineState *sms, | |
316 | MemoryRegion *secure_sysmem) | |
317 | { | |
318 | MemoryRegion *secram = g_new(MemoryRegion, 1); | |
319 | hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; | |
320 | hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; | |
321 | ||
322 | memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, | |
323 | &error_fatal); | |
324 | memory_region_add_subregion(secure_sysmem, base, secram); | |
325 | } | |
326 | ||
327 | static void create_gic(SBSAMachineState *sms, qemu_irq *pic) | |
328 | { | |
cc7d44c2 | 329 | unsigned int smp_cpus = MACHINE(sms)->smp.cpus; |
e9fdf453 HZ |
330 | DeviceState *gicdev; |
331 | SysBusDevice *gicbusdev; | |
332 | const char *gictype; | |
333 | uint32_t redist0_capacity, redist0_count; | |
334 | int i; | |
335 | ||
336 | gictype = gicv3_class_name(); | |
337 | ||
338 | gicdev = qdev_create(NULL, gictype); | |
339 | qdev_prop_set_uint32(gicdev, "revision", 3); | |
340 | qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); | |
341 | /* | |
342 | * Note that the num-irq property counts both internal and external | |
343 | * interrupts; there are always 32 of the former (mandated by GIC spec). | |
344 | */ | |
345 | qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); | |
346 | qdev_prop_set_bit(gicdev, "has-security-extensions", true); | |
347 | ||
348 | redist0_capacity = | |
349 | sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; | |
350 | redist0_count = MIN(smp_cpus, redist0_capacity); | |
351 | ||
352 | qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); | |
353 | qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); | |
354 | ||
355 | qdev_init_nofail(gicdev); | |
356 | gicbusdev = SYS_BUS_DEVICE(gicdev); | |
357 | sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); | |
358 | sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); | |
359 | ||
360 | /* | |
361 | * Wire the outputs from each CPU's generic timer and the GICv3 | |
362 | * maintenance interrupt signal to the appropriate GIC PPI inputs, | |
363 | * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. | |
364 | */ | |
365 | for (i = 0; i < smp_cpus; i++) { | |
366 | DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); | |
367 | int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; | |
368 | int irq; | |
369 | /* | |
370 | * Mapping from the output timer irq lines from the CPU to the | |
371 | * GIC PPI inputs used for this board. | |
372 | */ | |
373 | const int timer_irq[] = { | |
374 | [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, | |
375 | [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | |
376 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | |
377 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, | |
378 | }; | |
379 | ||
380 | for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | |
381 | qdev_connect_gpio_out(cpudev, irq, | |
382 | qdev_get_gpio_in(gicdev, | |
383 | ppibase + timer_irq[irq])); | |
384 | } | |
385 | ||
386 | qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, | |
387 | qdev_get_gpio_in(gicdev, ppibase | |
388 | + ARCH_GIC_MAINT_IRQ)); | |
389 | qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, | |
390 | qdev_get_gpio_in(gicdev, ppibase | |
391 | + VIRTUAL_PMU_IRQ)); | |
392 | ||
393 | sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); | |
394 | sysbus_connect_irq(gicbusdev, i + smp_cpus, | |
395 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | |
396 | sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, | |
397 | qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); | |
398 | sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, | |
399 | qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); | |
400 | } | |
401 | ||
402 | for (i = 0; i < NUM_IRQS; i++) { | |
403 | pic[i] = qdev_get_gpio_in(gicdev, i); | |
404 | } | |
405 | } | |
406 | ||
407 | static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart, | |
408 | MemoryRegion *mem, Chardev *chr) | |
409 | { | |
410 | hwaddr base = sbsa_ref_memmap[uart].base; | |
411 | int irq = sbsa_ref_irqmap[uart]; | |
412 | DeviceState *dev = qdev_create(NULL, "pl011"); | |
413 | SysBusDevice *s = SYS_BUS_DEVICE(dev); | |
414 | ||
415 | qdev_prop_set_chr(dev, "chardev", chr); | |
416 | qdev_init_nofail(dev); | |
417 | memory_region_add_subregion(mem, base, | |
418 | sysbus_mmio_get_region(s, 0)); | |
419 | sysbus_connect_irq(s, 0, pic[irq]); | |
420 | } | |
421 | ||
422 | static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic) | |
423 | { | |
424 | hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; | |
425 | int irq = sbsa_ref_irqmap[SBSA_RTC]; | |
426 | ||
427 | sysbus_create_simple("pl031", base, pic[irq]); | |
428 | } | |
429 | ||
430 | static DeviceState *gpio_key_dev; | |
431 | static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) | |
432 | { | |
433 | /* use gpio Pin 3 for power button event */ | |
434 | qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); | |
435 | } | |
436 | ||
437 | static Notifier sbsa_ref_powerdown_notifier = { | |
438 | .notify = sbsa_ref_powerdown_req | |
439 | }; | |
440 | ||
441 | static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic) | |
442 | { | |
443 | DeviceState *pl061_dev; | |
444 | hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; | |
445 | int irq = sbsa_ref_irqmap[SBSA_GPIO]; | |
446 | ||
447 | pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); | |
448 | ||
449 | gpio_key_dev = sysbus_create_simple("gpio-key", -1, | |
450 | qdev_get_gpio_in(pl061_dev, 3)); | |
451 | ||
452 | /* connect powerdown request */ | |
453 | qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); | |
454 | } | |
455 | ||
456 | static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic) | |
457 | { | |
458 | hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; | |
459 | int irq = sbsa_ref_irqmap[SBSA_AHCI]; | |
460 | DeviceState *dev; | |
461 | DriveInfo *hd[NUM_SATA_PORTS]; | |
462 | SysbusAHCIState *sysahci; | |
463 | AHCIState *ahci; | |
464 | int i; | |
465 | ||
466 | dev = qdev_create(NULL, "sysbus-ahci"); | |
467 | qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); | |
468 | qdev_init_nofail(dev); | |
469 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); | |
470 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); | |
471 | ||
472 | sysahci = SYSBUS_AHCI(dev); | |
473 | ahci = &sysahci->ahci; | |
474 | ide_drive_get(hd, ARRAY_SIZE(hd)); | |
475 | for (i = 0; i < ahci->ports; i++) { | |
476 | if (hd[i] == NULL) { | |
477 | continue; | |
478 | } | |
479 | ide_create_drive(&ahci->dev[i].port, 0, hd[i]); | |
480 | } | |
481 | } | |
482 | ||
483 | static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic) | |
484 | { | |
485 | hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; | |
486 | int irq = sbsa_ref_irqmap[SBSA_EHCI]; | |
487 | ||
488 | sysbus_create_simple("platform-ehci-usb", base, pic[irq]); | |
489 | } | |
490 | ||
491 | static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic, | |
492 | PCIBus *bus) | |
493 | { | |
494 | hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; | |
495 | int irq = sbsa_ref_irqmap[SBSA_SMMU]; | |
496 | DeviceState *dev; | |
497 | int i; | |
498 | ||
499 | dev = qdev_create(NULL, "arm-smmuv3"); | |
500 | ||
501 | object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", | |
502 | &error_abort); | |
503 | qdev_init_nofail(dev); | |
504 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); | |
505 | for (i = 0; i < NUM_SMMU_IRQS; i++) { | |
506 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
507 | } | |
508 | } | |
509 | ||
510 | static void create_pcie(SBSAMachineState *sms, qemu_irq *pic) | |
511 | { | |
512 | hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; | |
513 | hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; | |
514 | hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; | |
515 | hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; | |
516 | hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; | |
517 | hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; | |
518 | hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; | |
519 | int irq = sbsa_ref_irqmap[SBSA_PCIE]; | |
520 | MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; | |
521 | MemoryRegion *ecam_alias, *ecam_reg; | |
522 | DeviceState *dev; | |
523 | PCIHostState *pci; | |
524 | int i; | |
525 | ||
526 | dev = qdev_create(NULL, TYPE_GPEX_HOST); | |
527 | qdev_init_nofail(dev); | |
528 | ||
529 | /* Map ECAM space */ | |
530 | ecam_alias = g_new0(MemoryRegion, 1); | |
531 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
532 | memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", | |
533 | ecam_reg, 0, size_ecam); | |
534 | memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); | |
535 | ||
536 | /* Map the MMIO space */ | |
537 | mmio_alias = g_new0(MemoryRegion, 1); | |
538 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
539 | memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", | |
540 | mmio_reg, base_mmio, size_mmio); | |
541 | memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); | |
542 | ||
543 | /* Map the MMIO_HIGH space */ | |
544 | mmio_alias_high = g_new0(MemoryRegion, 1); | |
545 | memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", | |
546 | mmio_reg, base_mmio_high, size_mmio_high); | |
547 | memory_region_add_subregion(get_system_memory(), base_mmio_high, | |
548 | mmio_alias_high); | |
549 | ||
550 | /* Map IO port space */ | |
551 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); | |
552 | ||
553 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | |
554 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
555 | gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); | |
556 | } | |
557 | ||
558 | pci = PCI_HOST_BRIDGE(dev); | |
559 | if (pci->bus) { | |
560 | for (i = 0; i < nb_nics; i++) { | |
561 | NICInfo *nd = &nd_table[i]; | |
562 | ||
563 | if (!nd->model) { | |
564 | nd->model = g_strdup("e1000e"); | |
565 | } | |
566 | ||
567 | pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); | |
568 | } | |
569 | } | |
570 | ||
571 | pci_create_simple(pci->bus, -1, "VGA"); | |
572 | ||
573 | create_smmu(sms, pic, pci->bus); | |
574 | } | |
575 | ||
576 | static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) | |
577 | { | |
578 | const SBSAMachineState *board = container_of(binfo, SBSAMachineState, | |
579 | bootinfo); | |
580 | ||
581 | *fdt_size = board->fdt_size; | |
582 | return board->fdt; | |
583 | } | |
584 | ||
64580903 HZ |
585 | static void sbsa_ref_init(MachineState *machine) |
586 | { | |
cc7d44c2 LX |
587 | unsigned int smp_cpus = machine->smp.cpus; |
588 | unsigned int max_cpus = machine->smp.max_cpus; | |
64580903 HZ |
589 | SBSAMachineState *sms = SBSA_MACHINE(machine); |
590 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
591 | MemoryRegion *sysmem = get_system_memory(); | |
c8ead571 | 592 | MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); |
64580903 | 593 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
e9fdf453 | 594 | bool firmware_loaded; |
64580903 HZ |
595 | const CPUArchIdList *possible_cpus; |
596 | int n, sbsa_max_cpus; | |
e9fdf453 | 597 | qemu_irq pic[NUM_IRQS]; |
64580903 HZ |
598 | |
599 | if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { | |
600 | error_report("sbsa-ref: CPU type other than the built-in " | |
601 | "cortex-a57 not supported"); | |
602 | exit(1); | |
603 | } | |
604 | ||
605 | if (kvm_enabled()) { | |
606 | error_report("sbsa-ref: KVM is not supported for this machine"); | |
607 | exit(1); | |
608 | } | |
609 | ||
e9fdf453 HZ |
610 | /* |
611 | * The Secure view of the world is the same as the NonSecure, | |
612 | * but with a few extra devices. Create it as a container region | |
613 | * containing the system memory at low priority; any secure-only | |
614 | * devices go in at higher priority and take precedence. | |
615 | */ | |
e9fdf453 HZ |
616 | memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", |
617 | UINT64_MAX); | |
618 | memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); | |
619 | ||
c8ead571 | 620 | firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); |
e9fdf453 HZ |
621 | |
622 | if (machine->kernel_filename && firmware_loaded) { | |
623 | error_report("sbsa-ref: No fw_cfg device on this machine, " | |
624 | "so -kernel option is not supported when firmware loaded, " | |
625 | "please load OS from hard disk instead"); | |
626 | exit(1); | |
627 | } | |
628 | ||
64580903 HZ |
629 | /* |
630 | * This machine has EL3 enabled, external firmware should supply PSCI | |
631 | * implementation, so the QEMU's internal PSCI is disabled. | |
632 | */ | |
633 | sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; | |
634 | ||
635 | sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; | |
636 | ||
637 | if (max_cpus > sbsa_max_cpus) { | |
638 | error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " | |
639 | "supported by machine 'sbsa-ref' (%d)", | |
640 | max_cpus, sbsa_max_cpus); | |
641 | exit(1); | |
642 | } | |
643 | ||
644 | sms->smp_cpus = smp_cpus; | |
645 | ||
646 | if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { | |
647 | error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); | |
648 | exit(1); | |
649 | } | |
650 | ||
651 | possible_cpus = mc->possible_cpu_arch_ids(machine); | |
652 | for (n = 0; n < possible_cpus->len; n++) { | |
653 | Object *cpuobj; | |
654 | CPUState *cs; | |
655 | ||
656 | if (n >= smp_cpus) { | |
657 | break; | |
658 | } | |
659 | ||
660 | cpuobj = object_new(possible_cpus->cpus[n].type); | |
661 | object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, | |
662 | "mp-affinity", NULL); | |
663 | ||
664 | cs = CPU(cpuobj); | |
665 | cs->cpu_index = n; | |
666 | ||
667 | numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), | |
668 | &error_fatal); | |
669 | ||
670 | if (object_property_find(cpuobj, "reset-cbar", NULL)) { | |
671 | object_property_set_int(cpuobj, | |
672 | sbsa_ref_memmap[SBSA_CPUPERIPHS].base, | |
673 | "reset-cbar", &error_abort); | |
674 | } | |
675 | ||
676 | object_property_set_link(cpuobj, OBJECT(sysmem), "memory", | |
677 | &error_abort); | |
678 | ||
679 | object_property_set_link(cpuobj, OBJECT(secure_sysmem), | |
680 | "secure-memory", &error_abort); | |
681 | ||
682 | object_property_set_bool(cpuobj, true, "realized", &error_fatal); | |
683 | object_unref(cpuobj); | |
684 | } | |
685 | ||
686 | memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram", | |
687 | machine->ram_size); | |
688 | memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram); | |
689 | ||
e9fdf453 HZ |
690 | create_fdt(sms); |
691 | ||
692 | create_secure_ram(sms, secure_sysmem); | |
693 | ||
694 | create_gic(sms, pic); | |
695 | ||
696 | create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0)); | |
697 | create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); | |
698 | /* Second secure UART for RAS and MM from EL0 */ | |
699 | create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); | |
700 | ||
701 | create_rtc(sms, pic); | |
702 | ||
703 | create_gpio(sms, pic); | |
704 | ||
705 | create_ahci(sms, pic); | |
706 | ||
707 | create_ehci(sms, pic); | |
708 | ||
709 | create_pcie(sms, pic); | |
710 | ||
64580903 HZ |
711 | sms->bootinfo.ram_size = machine->ram_size; |
712 | sms->bootinfo.kernel_filename = machine->kernel_filename; | |
713 | sms->bootinfo.nb_cpus = smp_cpus; | |
714 | sms->bootinfo.board_id = -1; | |
715 | sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; | |
e9fdf453 HZ |
716 | sms->bootinfo.get_dtb = sbsa_ref_dtb; |
717 | sms->bootinfo.firmware_loaded = firmware_loaded; | |
64580903 HZ |
718 | arm_load_kernel(ARM_CPU(first_cpu), &sms->bootinfo); |
719 | } | |
720 | ||
721 | static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) | |
722 | { | |
723 | uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; | |
724 | return arm_cpu_mp_affinity(idx, clustersz); | |
725 | } | |
726 | ||
727 | static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) | |
728 | { | |
cc7d44c2 | 729 | unsigned int max_cpus = ms->smp.max_cpus; |
64580903 HZ |
730 | SBSAMachineState *sms = SBSA_MACHINE(ms); |
731 | int n; | |
732 | ||
733 | if (ms->possible_cpus) { | |
734 | assert(ms->possible_cpus->len == max_cpus); | |
735 | return ms->possible_cpus; | |
736 | } | |
737 | ||
738 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
739 | sizeof(CPUArchId) * max_cpus); | |
740 | ms->possible_cpus->len = max_cpus; | |
741 | for (n = 0; n < ms->possible_cpus->len; n++) { | |
742 | ms->possible_cpus->cpus[n].type = ms->cpu_type; | |
743 | ms->possible_cpus->cpus[n].arch_id = | |
744 | sbsa_ref_cpu_mp_affinity(sms, n); | |
745 | ms->possible_cpus->cpus[n].props.has_thread_id = true; | |
746 | ms->possible_cpus->cpus[n].props.thread_id = n; | |
747 | } | |
748 | return ms->possible_cpus; | |
749 | } | |
750 | ||
751 | static CpuInstanceProperties | |
752 | sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | |
753 | { | |
754 | MachineClass *mc = MACHINE_GET_CLASS(ms); | |
755 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); | |
756 | ||
757 | assert(cpu_index < possible_cpus->len); | |
758 | return possible_cpus->cpus[cpu_index].props; | |
759 | } | |
760 | ||
761 | static int64_t | |
762 | sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) | |
763 | { | |
764 | return idx % nb_numa_nodes; | |
765 | } | |
766 | ||
e9fdf453 HZ |
767 | static void sbsa_ref_instance_init(Object *obj) |
768 | { | |
769 | SBSAMachineState *sms = SBSA_MACHINE(obj); | |
770 | ||
771 | sbsa_flash_create(sms); | |
772 | } | |
773 | ||
64580903 HZ |
774 | static void sbsa_ref_class_init(ObjectClass *oc, void *data) |
775 | { | |
776 | MachineClass *mc = MACHINE_CLASS(oc); | |
777 | ||
778 | mc->init = sbsa_ref_init; | |
779 | mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; | |
780 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); | |
781 | mc->max_cpus = 512; | |
782 | mc->pci_allow_0_address = true; | |
783 | mc->minimum_page_bits = 12; | |
784 | mc->block_default_type = IF_IDE; | |
785 | mc->no_cdrom = 1; | |
786 | mc->default_ram_size = 1 * GiB; | |
787 | mc->default_cpus = 4; | |
788 | mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; | |
789 | mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; | |
790 | mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; | |
791 | } | |
792 | ||
793 | static const TypeInfo sbsa_ref_info = { | |
794 | .name = TYPE_SBSA_MACHINE, | |
795 | .parent = TYPE_MACHINE, | |
e9fdf453 | 796 | .instance_init = sbsa_ref_instance_init, |
64580903 HZ |
797 | .class_init = sbsa_ref_class_init, |
798 | .instance_size = sizeof(SBSAMachineState), | |
799 | }; | |
800 | ||
801 | static void sbsa_ref_machine_init(void) | |
802 | { | |
803 | type_register_static(&sbsa_ref_info); | |
804 | } | |
805 | ||
806 | type_init(sbsa_ref_machine_init); |