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error: Eliminate error_propagate() with Coccinelle, part 1
[mirror_qemu.git] / hw / block / fdc.c
CommitLineData
8977f3c1 1/*
890fa6be 2 * QEMU Floppy disk emulator (Intel 82078)
5fafdf24 3 *
3ccacc4a 4 * Copyright (c) 2003, 2007 Jocelyn Mayer
bcc4e41f 5 * Copyright (c) 2008 Hervé Poussineau
5fafdf24 6 *
8977f3c1
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
e80cfcfc
FB		 25/*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
f64ab228 29
80c71a24 30#include "qemu/osdep.h"
0d09e41a 31#include "hw/block/fdc.h"
da34e65c 32#include "qapi/error.h"
1de7afc9
PB		 33#include "qemu/error-report.h"
34#include "qemu/timer.h"
2055dbc1 35#include "hw/acpi/aml-build.h"
64552b6b 36#include "hw/irq.h"
0d09e41a 37#include "hw/isa/isa.h"
a27bd6c7 38#include "hw/qdev-properties.h"
83c9f4ca 39#include "hw/sysbus.h"
d6454270 40#include "migration/vmstate.h"
a92bd191 41#include "hw/block/block.h"
fa1d36df 42#include "sysemu/block-backend.h"
9c17d615
PB		 43#include "sysemu/blockdev.h"
44#include "sysemu/sysemu.h"
1de7afc9 45#include "qemu/log.h"
db725815 46#include "qemu/main-loop.h"
0b8fa32f 47#include "qemu/module.h"
1a5396d9 48#include "trace.h"
8977f3c1
FB		 49
50/********************************************************/
51/* debug Floppy devices */
8977f3c1 52
c691320f
JS		 53#define DEBUG_FLOPPY 0
54
001faf32 55#define FLOPPY_DPRINTF(fmt, ...) \
c691320f
JS		 56 do { \
57 if (DEBUG_FLOPPY) { \
58 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \
59 } \
60 } while (0)
8977f3c1 61
51e6e90e
KW		 62
63/********************************************************/
64/* qdev floppy bus */
65
66#define TYPE_FLOPPY_BUS "floppy-bus"
67#define FLOPPY_BUS(obj) OBJECT_CHECK(FloppyBus, (obj), TYPE_FLOPPY_BUS)
68
69typedef struct FDCtrl FDCtrl;
394ea2ca
KW		 70typedef struct FDrive FDrive;
71static FDrive *get_drv(FDCtrl *fdctrl, int unit);
51e6e90e
KW		 72
73typedef struct FloppyBus {
74 BusState bus;
75 FDCtrl *fdc;
76} FloppyBus;
77
78static const TypeInfo floppy_bus_info = {
79 .name = TYPE_FLOPPY_BUS,
80 .parent = TYPE_BUS,
81 .instance_size = sizeof(FloppyBus),
82};
83
84static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev)
85{
86 qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
87 bus->fdc = fdc;
88}
89
90
8977f3c1
FB		 91/********************************************************/
92/* Floppy drive emulation */
93
61a8d649
MA		 94typedef enum FDriveRate {
95 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
96 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
97 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
98 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
99} FDriveRate;
100
109c17bc
JS		 101typedef enum FDriveSize {
102 FDRIVE_SIZE_UNKNOWN,
103 FDRIVE_SIZE_350,
104 FDRIVE_SIZE_525,
105} FDriveSize;
106
61a8d649 107typedef struct FDFormat {
2da44dd0 108 FloppyDriveType drive;
61a8d649
MA		 109 uint8_t last_sect;
110 uint8_t max_track;
111 uint8_t max_head;
112 FDriveRate rate;
113} FDFormat;
114
109c17bc
JS		 115/* In many cases, the total sector size of a format is enough to uniquely
116 * identify it. However, there are some total sector collisions between
117 * formats of different physical size, and these are noted below by
118 * highlighting the total sector size for entries with collisions. */
61a8d649
MA		 119static const FDFormat fd_formats[] = {
120 /* First entry is default format */
121 /* 1.44 MB 3"1/2 floppy disks */
109c17bc
JS		 122 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */
123 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */
2da44dd0
JS		 124 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
125 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
126 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
127 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
128 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
129 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
61a8d649 130 /* 2.88 MB 3"1/2 floppy disks */
2da44dd0
JS		 131 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
132 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
133 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
134 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
135 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
61a8d649 136 /* 720 kB 3"1/2 floppy disks */
109c17bc 137 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */
2da44dd0
JS		 138 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
139 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
140 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
141 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
142 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
61a8d649 143 /* 1.2 MB 5"1/4 floppy disks */
2da44dd0 144 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
109c17bc 145 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */
2da44dd0
JS		 146 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
147 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
109c17bc 148 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */
61a8d649 149 /* 720 kB 5"1/4 floppy disks */
109c17bc 150 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */
2da44dd0 151 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
61a8d649 152 /* 360 kB 5"1/4 floppy disks */
109c17bc 153 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */
2da44dd0
JS		 154 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
155 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
156 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
61a8d649 157 /* 320 kB 5"1/4 floppy disks */
2da44dd0
JS		 158 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
159 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
61a8d649 160 /* 360 kB must match 5"1/4 better than 3"1/2... */
109c17bc 161 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */
61a8d649 162 /* end */
2da44dd0 163 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
61a8d649
MA		 164};
165
109c17bc
JS		 166static FDriveSize drive_size(FloppyDriveType drive)
167{
168 switch (drive) {
169 case FLOPPY_DRIVE_TYPE_120:
170 return FDRIVE_SIZE_525;
171 case FLOPPY_DRIVE_TYPE_144:
172 case FLOPPY_DRIVE_TYPE_288:
173 return FDRIVE_SIZE_350;
174 default:
175 return FDRIVE_SIZE_UNKNOWN;
176 }
177}
178
cefec4f5
BS		 179#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
180#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
181
8977f3c1 182/* Will always be a fixed parameter for us */
f2d81b33
BS		 183#define FD_SECTOR_LEN 512
184#define FD_SECTOR_SC 2 /* Sector size code */
185#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
8977f3c1
FB		 186
187/* Floppy disk drive emulation */
5c02c033 188typedef enum FDiskFlags {
baca51fa 189 FDISK_DBL_SIDES = 0x01,
5c02c033 190} FDiskFlags;
baca51fa 191
394ea2ca 192struct FDrive {
844f65d6 193 FDCtrl *fdctrl;
4be74634 194 BlockBackend *blk;
a17c17a2 195 BlockConf *conf;
8977f3c1 196 /* Drive status */
2da44dd0 197 FloppyDriveType drive; /* CMOS drive type */
8977f3c1 198 uint8_t perpendicular; /* 2.88 MB access mode */
8977f3c1
FB		 199 /* Position */
200 uint8_t head;
201 uint8_t track;
202 uint8_t sect;
8977f3c1 203 /* Media */
16c1e3ec 204 FloppyDriveType disk; /* Current disk type */
5c02c033 205 FDiskFlags flags;
8977f3c1
FB		 206 uint8_t last_sect; /* Nb sector per track */
207 uint8_t max_track; /* Nb of tracks */
baca51fa 208 uint16_t bps; /* Bytes per sector */
8977f3c1 209 uint8_t ro; /* Is read-only */
7d905f71 210 uint8_t media_changed; /* Is media changed */
844f65d6 211 uint8_t media_rate; /* Data rate of medium */
2e1280e8 212
d5d47efc 213 bool media_validated; /* Have we validated the media? */
394ea2ca 214};
8977f3c1 215
a73275dd
JS		 216
217static FloppyDriveType get_fallback_drive_type(FDrive *drv);
218
fd9bdbd3
JS		 219/* Hack: FD_SEEK is expected to work on empty drives. However, QEMU
220 * currently goes through some pains to keep seeks within the bounds
221 * established by last_sect and max_track. Correcting this is difficult,
222 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel.
223 *
224 * For now: allow empty drives to have large bounds so we can seek around,
225 * with the understanding that when a diskette is inserted, the bounds will
226 * properly tighten to match the geometry of that inserted medium.
227 */
228static void fd_empty_seek_hack(FDrive *drv)
229{
230 drv->last_sect = 0xFF;
231 drv->max_track = 0xFF;
232}
233
5c02c033 234static void fd_init(FDrive *drv)
8977f3c1
FB		 235{
236 /* Drive */
8977f3c1 237 drv->perpendicular = 0;
8977f3c1 238 /* Disk */
16c1e3ec 239 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
baca51fa 240 drv->last_sect = 0;
8977f3c1 241 drv->max_track = 0;
d5d47efc
JS		 242 drv->ro = true;
243 drv->media_changed = 1;
8977f3c1
FB		 244}
245
08388273
HP		 246#define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
247
7859cb98 248static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
08388273 249 uint8_t last_sect, uint8_t num_sides)
8977f3c1 250{
08388273 251 return (((track * num_sides) + head) * last_sect) + sect - 1;
8977f3c1
FB		 252}
253
254/* Returns current position, in sectors, for given drive */
5c02c033 255static int fd_sector(FDrive *drv)
8977f3c1 256{
08388273
HP		 257 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
258 NUM_SIDES(drv));
8977f3c1
FB		 259}
260
a7a5b7c0
EB		 261/* Returns current position, in bytes, for given drive */
262static int fd_offset(FDrive *drv)
263{
264 g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS);
265 return fd_sector(drv) << BDRV_SECTOR_BITS;
266}
267
77370520
BS		 268/* Seek to a new position:
269 * returns 0 if already on right track
270 * returns 1 if track changed
271 * returns 2 if track is invalid
272 * returns 3 if sector is invalid
273 * returns 4 if seek is disabled
274 */
5c02c033
BS		 275static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
276 int enable_seek)
8977f3c1
FB		 277{
278 uint32_t sector;
baca51fa
FB		 279 int ret;
280
281 if (track > drv->max_track ||
4f431960 282 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
ed5fd2cc
FB		 283 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
284 head, track, sect, 1,
285 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
286 drv->max_track, drv->last_sect);
8977f3c1
FB		 287 return 2;
288 }
289 if (sect > drv->last_sect) {
ed5fd2cc
FB		 290 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
291 head, track, sect, 1,
292 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
293 drv->max_track, drv->last_sect);
8977f3c1
FB		 294 return 3;
295 }
08388273 296 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
baca51fa 297 ret = 0;
8977f3c1
FB		 298 if (sector != fd_sector(drv)) {
299#if 0
300 if (!enable_seek) {
cced7a13
BS		 301 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
302 " (max=%d %02x %02x)\n",
303 head, track, sect, 1, drv->max_track,
304 drv->last_sect);
8977f3c1
FB		 305 return 4;
306 }
307#endif
308 drv->head = head;
6be01b1e 309 if (drv->track != track) {
abb3e55b 310 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
6be01b1e
PH		 311 drv->media_changed = 0;
312 }
4f431960 313 ret = 1;
6be01b1e 314 }
8977f3c1
FB		 315 drv->track = track;
316 drv->sect = sect;
8977f3c1
FB		 317 }
318
abb3e55b 319 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
c52acf60
PH		 320 ret = 2;
321 }
322
baca51fa 323 return ret;
8977f3c1
FB		 324}
325
326/* Set drive back to track 0 */
5c02c033 327static void fd_recalibrate(FDrive *drv)
8977f3c1
FB		 328{
329 FLOPPY_DPRINTF("recalibrate\n");
6be01b1e 330 fd_seek(drv, 0, 0, 1, 1);
8977f3c1
FB		 331}
332
d5d47efc
JS		 333/**
334 * Determine geometry based on inserted diskette.
335 * Will not operate on an empty drive.
336 *
337 * @return: 0 on success, -1 if the drive is empty.
338 */
339static int pick_geometry(FDrive *drv)
9a972233 340{
21862658 341 BlockBackend *blk = drv->blk;
9a972233
JS		 342 const FDFormat *parse;
343 uint64_t nb_sectors, size;
f31937aa
JS		 344 int i;
345 int match, size_match, type_match;
346 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO;
9a972233 347
d5d47efc 348 /* We can only pick a geometry if we have a diskette. */
abb3e55b
HR		 349 if (!drv->blk || !blk_is_inserted(drv->blk) ||
350 drv->drive == FLOPPY_DRIVE_TYPE_NONE)
351 {
d5d47efc
JS		 352 return -1;
353 }
354
f31937aa
JS		 355 /* We need to determine the likely geometry of the inserted medium.
356 * In order of preference, we look for:
357 * (1) The same drive type and number of sectors,
358 * (2) The same diskette size and number of sectors,
359 * (3) The same drive type.
360 *
361 * In all cases, matches that occur higher in the drive table will take
362 * precedence over matches that occur later in the table.
363 */
9a972233 364 blk_get_geometry(blk, &nb_sectors);
f31937aa 365 match = size_match = type_match = -1;
9a972233
JS		 366 for (i = 0; ; i++) {
367 parse = &fd_formats[i];
2da44dd0 368 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
9a972233
JS		 369 break;
370 }
f31937aa
JS		 371 size = (parse->max_head + 1) * parse->max_track * parse->last_sect;
372 if (nb_sectors == size) {
373 if (magic || parse->drive == drv->drive) {
374 /* (1) perfect match -- nb_sectors and drive type */
375 goto out;
376 } else if (drive_size(parse->drive) == drive_size(drv->drive)) {
377 /* (2) size match -- nb_sectors and physical medium size */
378 match = (match == -1) ? i : match;
379 } else {
380 /* This is suspicious -- Did the user misconfigure? */
381 size_match = (size_match == -1) ? i : size_match;
9a972233 382 }
f31937aa
JS		 383 } else if (type_match == -1) {
384 if ((parse->drive == drv->drive) ||
385 (magic && (parse->drive == get_fallback_drive_type(drv)))) {
386 /* (3) type match -- nb_sectors mismatch, but matches the type
387 * specified explicitly by the user, or matches the fallback
388 * default type when using the drive autodetect mechanism */
389 type_match = i;
9a972233
JS		 390 }
391 }
392 }
f31937aa
JS		 393
394 /* No exact match found */
9a972233 395 if (match == -1) {
f31937aa
JS		 396 if (size_match != -1) {
397 parse = &fd_formats[size_match];
398 FLOPPY_DPRINTF("User requested floppy drive type '%s', "
399 "but inserted medium appears to be a "
c691320f 400 "%"PRId64" sector '%s' type\n",
977c736f 401 FloppyDriveType_str(drv->drive),
f31937aa 402 nb_sectors,
977c736f 403 FloppyDriveType_str(parse->drive));
9a972233 404 }
329b7291 405 assert(type_match != -1 && "misconfigured fd_format");
f31937aa 406 match = type_match;
9a972233 407 }
f31937aa
JS		 408 parse = &(fd_formats[match]);
409
410 out:
21862658
JS		 411 if (parse->max_head == 0) {
412 drv->flags &= ~FDISK_DBL_SIDES;
413 } else {
414 drv->flags |= FDISK_DBL_SIDES;
415 }
416 drv->max_track = parse->max_track;
417 drv->last_sect = parse->last_sect;
d5d47efc 418 drv->disk = parse->drive;
21862658 419 drv->media_rate = parse->rate;
d5d47efc
JS		 420 return 0;
421}
422
423static void pick_drive_type(FDrive *drv)
424{
fff4687b
JS		 425 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
426 return;
427 }
428
d5d47efc
JS		 429 if (pick_geometry(drv) == 0) {
430 drv->drive = drv->disk;
431 } else {
a73275dd 432 drv->drive = get_fallback_drive_type(drv);
d5d47efc 433 }
fff4687b
JS		 434
435 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
9a972233
JS		 436}
437
8977f3c1 438/* Revalidate a disk drive after a disk change */
5c02c033 439static void fd_revalidate(FDrive *drv)
8977f3c1 440{
d5d47efc
JS		 441 int rc;
442
8977f3c1 443 FLOPPY_DPRINTF("revalidate\n");
4be74634 444 if (drv->blk != NULL) {
21862658 445 drv->ro = blk_is_read_only(drv->blk);
abb3e55b 446 if (!blk_is_inserted(drv->blk)) {
cfb08fba 447 FLOPPY_DPRINTF("No disk in drive\n");
d5d47efc 448 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
fd9bdbd3 449 fd_empty_seek_hack(drv);
d5d47efc
JS		 450 } else if (!drv->media_validated) {
451 rc = pick_geometry(drv);
452 if (rc) {
453 FLOPPY_DPRINTF("Could not validate floppy drive media");
454 } else {
455 drv->media_validated = true;
456 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
457 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
458 drv->max_track, drv->last_sect,
459 drv->ro ? "ro" : "rw");
460 }
4f431960 461 }
8977f3c1 462 } else {
cfb08fba 463 FLOPPY_DPRINTF("No drive connected\n");
baca51fa 464 drv->last_sect = 0;
4f431960
JM		 465 drv->max_track = 0;
466 drv->flags &= ~FDISK_DBL_SIDES;
d5d47efc
JS		 467 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
468 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
8977f3c1 469 }
caed8802
FB		 470}
471
39829a01 472static void fd_change_cb(void *opaque, bool load, Error **errp)
394ea2ca
KW		 473{
474 FDrive *drive = opaque;
a17c17a2
KW		 475
476 if (!load) {
477 blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort);
478 } else {
ceff3e1f
MZ		 479 if (!blkconf_apply_backend_options(drive->conf,
480 blk_is_read_only(drive->blk), false,
481 errp)) {
a17c17a2
KW		 482 return;
483 }
484 }
394ea2ca
KW		 485
486 drive->media_changed = 1;
487 drive->media_validated = false;
488 fd_revalidate(drive);
489}
490
491static const BlockDevOps fd_block_ops = {
492 .change_media_cb = fd_change_cb,
493};
494
495
496#define TYPE_FLOPPY_DRIVE "floppy"
497#define FLOPPY_DRIVE(obj) \
498 OBJECT_CHECK(FloppyDrive, (obj), TYPE_FLOPPY_DRIVE)
499
500typedef struct FloppyDrive {
a92bd191
KW		 501 DeviceState qdev;
502 uint32_t unit;
503 BlockConf conf;
504 FloppyDriveType type;
394ea2ca
KW		 505} FloppyDrive;
506
507static Property floppy_drive_properties[] = {
508 DEFINE_PROP_UINT32("unit", FloppyDrive, unit, -1),
a92bd191 509 DEFINE_BLOCK_PROPERTIES(FloppyDrive, conf),
85bbd1e7 510 DEFINE_PROP_SIGNED("drive-type", FloppyDrive, type,
a92bd191
KW		 511 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
512 FloppyDriveType),
394ea2ca
KW		 513 DEFINE_PROP_END_OF_LIST(),
514};
515
ae34fce5 516static void floppy_drive_realize(DeviceState *qdev, Error **errp)
394ea2ca
KW		 517{
518 FloppyDrive *dev = FLOPPY_DRIVE(qdev);
519 FloppyBus *bus = FLOPPY_BUS(qdev->parent_bus);
520 FDrive *drive;
0b9e918f 521 bool read_only;
a92bd191 522 int ret;
394ea2ca
KW		 523
524 if (dev->unit == -1) {
525 for (dev->unit = 0; dev->unit < MAX_FD; dev->unit++) {
526 drive = get_drv(bus->fdc, dev->unit);
527 if (!drive->blk) {
528 break;
529 }
530 }
531 }
532
533 if (dev->unit >= MAX_FD) {
ae34fce5
MZ		 534 error_setg(errp, "Can't create floppy unit %d, bus supports "
535 "only %d units", dev->unit, MAX_FD);
536 return;
394ea2ca
KW		 537 }
538
394ea2ca 539 drive = get_drv(bus->fdc, dev->unit);
394ea2ca 540 if (drive->blk) {
ae34fce5
MZ		 541 error_setg(errp, "Floppy unit %d is in use", dev->unit);
542 return;
a92bd191
KW		 543 }
544
545 if (!dev->conf.blk) {
394ea2ca 546 /* Anonymous BlockBackend for an empty drive */
d861ab3a 547 dev->conf.blk = blk_new(qemu_get_aio_context(), 0, BLK_PERM_ALL);
a92bd191
KW		 548 ret = blk_attach_dev(dev->conf.blk, qdev);
549 assert(ret == 0);
0b9e918f
KW		 550
551 /* Don't take write permissions on an empty drive to allow attaching a
552 * read-only node later */
553 read_only = true;
554 } else {
555 read_only = !blk_bs(dev->conf.blk) || blk_is_read_only(dev->conf.blk);
394ea2ca
KW		 556 }
557
c56ee92f
RK		 558 if (!blkconf_blocksizes(&dev->conf, errp)) {
559 return;
560 }
561
a92bd191
KW		 562 if (dev->conf.logical_block_size != 512 ||
563 dev->conf.physical_block_size != 512)
564 {
ae34fce5
MZ		 565 error_setg(errp, "Physical and logical block size must "
566 "be 512 for floppy");
567 return;
a92bd191
KW		 568 }
569
570 /* rerror/werror aren't supported by fdc and therefore not even registered
571 * with qdev. So set the defaults manually before they are used in
572 * blkconf_apply_backend_options(). */
573 dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO;
574 dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO;
a17c17a2 575
0b9e918f 576 if (!blkconf_apply_backend_options(&dev->conf, read_only, false, errp)) {
ae34fce5 577 return;
a17c17a2 578 }
a92bd191
KW		 579
580 /* 'enospc' is the default for -drive, 'report' is what blk_new() gives us
581 * for empty drives. */
582 if (blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC &&
583 blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_REPORT) {
ae34fce5
MZ		 584 error_setg(errp, "fdc doesn't support drive option werror");
585 return;
394ea2ca 586 }
a92bd191 587 if (blk_get_on_error(dev->conf.blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
ae34fce5
MZ		 588 error_setg(errp, "fdc doesn't support drive option rerror");
589 return;
a92bd191
KW		 590 }
591
a17c17a2 592 drive->conf = &dev->conf;
a92bd191
KW		 593 drive->blk = dev->conf.blk;
594 drive->fdctrl = bus->fdc;
595
596 fd_init(drive);
597 blk_set_dev_ops(drive->blk, &fd_block_ops, drive);
598
599 /* Keep 'type' qdev property and FDrive->drive in sync */
600 drive->drive = dev->type;
601 pick_drive_type(drive);
602 dev->type = drive->drive;
603
394ea2ca 604 fd_revalidate(drive);
394ea2ca
KW		 605}
606
607static void floppy_drive_class_init(ObjectClass *klass, void *data)
608{
609 DeviceClass *k = DEVICE_CLASS(klass);
ae34fce5 610 k->realize = floppy_drive_realize;
394ea2ca
KW		 611 set_bit(DEVICE_CATEGORY_STORAGE, k->categories);
612 k->bus_type = TYPE_FLOPPY_BUS;
4f67d30b 613 device_class_set_props(k, floppy_drive_properties);
394ea2ca
KW		 614 k->desc = "virtual floppy drive";
615}
616
617static const TypeInfo floppy_drive_info = {
618 .name = TYPE_FLOPPY_DRIVE,
619 .parent = TYPE_DEVICE,
620 .instance_size = sizeof(FloppyDrive),
621 .class_init = floppy_drive_class_init,
622};
623
8977f3c1 624/********************************************************/
4b19ec0c 625/* Intel 82078 floppy disk controller emulation */
8977f3c1 626
5c02c033 627static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
07e415f2 628static void fdctrl_to_command_phase(FDCtrl *fdctrl);
85571bc7 629static int fdctrl_transfer_handler (void *opaque, int nchan,
c227f099 630 int dma_pos, int dma_len);
d497d534 631static void fdctrl_raise_irq(FDCtrl *fdctrl);
a2df5fa3 632static FDrive *get_cur_drv(FDCtrl *fdctrl);
5c02c033
BS		 633
634static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
635static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
636static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
637static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
638static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
639static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
640static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
641static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
642static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
643static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
644static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
a758f8f4 645static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
8977f3c1 646
8977f3c1
FB		 647enum {
648 FD_DIR_WRITE = 0,
649 FD_DIR_READ = 1,
650 FD_DIR_SCANE = 2,
651 FD_DIR_SCANL = 3,
652 FD_DIR_SCANH = 4,
7ea004ed 653 FD_DIR_VERIFY = 5,
8977f3c1
FB		 654};
655
656enum {
b9b3d225
BS		 657 FD_STATE_MULTI = 0x01, /* multi track flag */
658 FD_STATE_FORMAT = 0x02, /* format flag */
8977f3c1
FB		 659};
660
9fea808a 661enum {
8c6a4d77
BS		 662 FD_REG_SRA = 0x00,
663 FD_REG_SRB = 0x01,
9fea808a
BS		 664 FD_REG_DOR = 0x02,
665 FD_REG_TDR = 0x03,
666 FD_REG_MSR = 0x04,
667 FD_REG_DSR = 0x04,
668 FD_REG_FIFO = 0x05,
669 FD_REG_DIR = 0x07,
a758f8f4 670 FD_REG_CCR = 0x07,
9fea808a
BS		 671};
672
673enum {
65cef780 674 FD_CMD_READ_TRACK = 0x02,
9fea808a
BS		 675 FD_CMD_SPECIFY = 0x03,
676 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
65cef780
BS		 677 FD_CMD_WRITE = 0x05,
678 FD_CMD_READ = 0x06,
9fea808a
BS		 679 FD_CMD_RECALIBRATE = 0x07,
680 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
65cef780
BS		 681 FD_CMD_WRITE_DELETED = 0x09,
682 FD_CMD_READ_ID = 0x0a,
683 FD_CMD_READ_DELETED = 0x0c,
684 FD_CMD_FORMAT_TRACK = 0x0d,
9fea808a
BS		 685 FD_CMD_DUMPREG = 0x0e,
686 FD_CMD_SEEK = 0x0f,
687 FD_CMD_VERSION = 0x10,
65cef780 688 FD_CMD_SCAN_EQUAL = 0x11,
9fea808a
BS		 689 FD_CMD_PERPENDICULAR_MODE = 0x12,
690 FD_CMD_CONFIGURE = 0x13,
65cef780
BS		 691 FD_CMD_LOCK = 0x14,
692 FD_CMD_VERIFY = 0x16,
9fea808a
BS		 693 FD_CMD_POWERDOWN_MODE = 0x17,
694 FD_CMD_PART_ID = 0x18,
65cef780
BS		 695 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
696 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
bb350a5e 697 FD_CMD_SAVE = 0x2e,
9fea808a 698 FD_CMD_OPTION = 0x33,
bb350a5e 699 FD_CMD_RESTORE = 0x4e,
9fea808a
BS		 700 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
701 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
9fea808a
BS		 702 FD_CMD_FORMAT_AND_WRITE = 0xcd,
703 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
704};
705
706enum {
707 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
708 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
709 FD_CONFIG_POLL = 0x10, /* Poll enabled */
710 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
711 FD_CONFIG_EIS = 0x40, /* No implied seeks */
712};
713
714enum {
2fee0088
PH		 715 FD_SR0_DS0 = 0x01,
716 FD_SR0_DS1 = 0x02,
717 FD_SR0_HEAD = 0x04,
9fea808a
BS		 718 FD_SR0_EQPMT = 0x10,
719 FD_SR0_SEEK = 0x20,
720 FD_SR0_ABNTERM = 0x40,
721 FD_SR0_INVCMD = 0x80,
722 FD_SR0_RDYCHG = 0xc0,
723};
724
77370520 725enum {
844f65d6 726 FD_SR1_MA = 0x01, /* Missing address mark */
8510854e 727 FD_SR1_NW = 0x02, /* Not writable */
77370520
BS		 728 FD_SR1_EC = 0x80, /* End of cylinder */
729};
730
731enum {
732 FD_SR2_SNS = 0x04, /* Scan not satisfied */
733 FD_SR2_SEH = 0x08, /* Scan equal hit */
734};
735
8c6a4d77
BS		 736enum {
737 FD_SRA_DIR = 0x01,
738 FD_SRA_nWP = 0x02,
739 FD_SRA_nINDX = 0x04,
740 FD_SRA_HDSEL = 0x08,
741 FD_SRA_nTRK0 = 0x10,
742 FD_SRA_STEP = 0x20,
743 FD_SRA_nDRV2 = 0x40,
744 FD_SRA_INTPEND = 0x80,
745};
746
747enum {
748 FD_SRB_MTR0 = 0x01,
749 FD_SRB_MTR1 = 0x02,
750 FD_SRB_WGATE = 0x04,
751 FD_SRB_RDATA = 0x08,
752 FD_SRB_WDATA = 0x10,
753 FD_SRB_DR0 = 0x20,
754};
755
9fea808a 756enum {
78ae820c
BS		 757#if MAX_FD == 4
758 FD_DOR_SELMASK = 0x03,
759#else
9fea808a 760 FD_DOR_SELMASK = 0x01,
78ae820c 761#endif
9fea808a
BS		 762 FD_DOR_nRESET = 0x04,
763 FD_DOR_DMAEN = 0x08,
764 FD_DOR_MOTEN0 = 0x10,
765 FD_DOR_MOTEN1 = 0x20,
766 FD_DOR_MOTEN2 = 0x40,
767 FD_DOR_MOTEN3 = 0x80,
768};
769
770enum {
78ae820c 771#if MAX_FD == 4
9fea808a 772 FD_TDR_BOOTSEL = 0x0c,
78ae820c
BS		 773#else
774 FD_TDR_BOOTSEL = 0x04,
775#endif
9fea808a
BS		 776};
777
778enum {
779 FD_DSR_DRATEMASK= 0x03,
780 FD_DSR_PWRDOWN = 0x40,
781 FD_DSR_SWRESET = 0x80,
782};
783
784enum {
785 FD_MSR_DRV0BUSY = 0x01,
786 FD_MSR_DRV1BUSY = 0x02,
787 FD_MSR_DRV2BUSY = 0x04,
788 FD_MSR_DRV3BUSY = 0x08,
789 FD_MSR_CMDBUSY = 0x10,
790 FD_MSR_NONDMA = 0x20,
791 FD_MSR_DIO = 0x40,
792 FD_MSR_RQM = 0x80,
793};
794
795enum {
796 FD_DIR_DSKCHG = 0x80,
797};
798
85d291a0
KW		 799/*
800 * See chapter 5.0 "Controller phases" of the spec:
801 *
802 * Command phase:
803 * The host writes a command and its parameters into the FIFO. The command
804 * phase is completed when all parameters for the command have been supplied,
805 * and execution phase is entered.
806 *
807 * Execution phase:
808 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
809 * contains the payload now, otherwise it's unused. When all bytes of the
810 * required data have been transferred, the state is switched to either result
811 * phase (if the command produces status bytes) or directly back into the
812 * command phase for the next command.
813 *
814 * Result phase:
815 * The host reads out the FIFO, which contains one or more result bytes now.
816 */
817enum {
818 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
819 FD_PHASE_RECONSTRUCT = 0,
820
821 FD_PHASE_COMMAND = 1,
822 FD_PHASE_EXECUTION = 2,
823 FD_PHASE_RESULT = 3,
824};
825
8977f3c1 826#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
baca51fa 827#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
8977f3c1 828
5c02c033 829struct FDCtrl {
dc6c1b37 830 MemoryRegion iomem;
d537cf6c 831 qemu_irq irq;
4b19ec0c 832 /* Controller state */
ed5fd2cc 833 QEMUTimer *result_timer;
242cca4f 834 int dma_chann;
85d291a0 835 uint8_t phase;
c8a35f1c 836 IsaDma *dma;
242cca4f
BS		 837 /* Controller's identification */
838 uint8_t version;
839 /* HW */
8c6a4d77
BS		 840 uint8_t sra;
841 uint8_t srb;
368df94d 842 uint8_t dor;
d7a6c270 843 uint8_t dor_vmstate; /* only used as temp during vmstate */
46d3233b 844 uint8_t tdr;
b9b3d225 845 uint8_t dsr;
368df94d 846 uint8_t msr;
8977f3c1 847 uint8_t cur_drv;
77370520
BS		 848 uint8_t status0;
849 uint8_t status1;
850 uint8_t status2;
8977f3c1 851 /* Command FIFO */
33f00271 852 uint8_t *fifo;
d7a6c270 853 int32_t fifo_size;
8977f3c1
FB		 854 uint32_t data_pos;
855 uint32_t data_len;
856 uint8_t data_state;
857 uint8_t data_dir;
890fa6be 858 uint8_t eot; /* last wanted sector */
8977f3c1 859 /* States kept only to be returned back */
8977f3c1
FB		 860 /* precompensation */
861 uint8_t precomp_trk;
862 uint8_t config;
863 uint8_t lock;
864 /* Power down config (also with status regB access mode */
865 uint8_t pwrd;
866 /* Floppy drives */
51e6e90e 867 FloppyBus bus;
d7a6c270 868 uint8_t num_floppies;
5c02c033 869 FDrive drives[MAX_FD];
a92bd191
KW		 870 struct {
871 BlockBackend *blk;
872 FloppyDriveType type;
873 } qdev_for_drives[MAX_FD];
f2d81b33 874 int reset_sensei;
09c6d585 875 uint32_t check_media_rate;
a73275dd 876 FloppyDriveType fallback; /* type=auto failure fallback */
242cca4f
BS		 877 /* Timers state */
878 uint8_t timer0;
879 uint8_t timer1;
e305a165 880 PortioList portio_list;
baca51fa
FB		 881};
882
a73275dd
JS		 883static FloppyDriveType get_fallback_drive_type(FDrive *drv)
884{
885 return drv->fdctrl->fallback;
886}
887
19d46d71 888#define TYPE_SYSBUS_FDC "base-sysbus-fdc"
dd3be742
HT		 889#define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
890
5c02c033 891typedef struct FDCtrlSysBus {
dd3be742
HT		 892 /*< private >*/
893 SysBusDevice parent_obj;
894 /*< public >*/
895
5c02c033
BS		 896 struct FDCtrl state;
897} FDCtrlSysBus;
8baf73ad 898
020c8e76
AF		 899#define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
900
5c02c033 901typedef struct FDCtrlISABus {
020c8e76
AF		 902 ISADevice parent_obj;
903
c9ae703d
HP		 904 uint32_t iobase;
905 uint32_t irq;
906 uint32_t dma;
5c02c033 907 struct FDCtrl state;
1ca4d09a
GN		 908 int32_t bootindexA;
909 int32_t bootindexB;
5c02c033 910} FDCtrlISABus;
8baf73ad 911
baca51fa
FB		 912static uint32_t fdctrl_read (void *opaque, uint32_t reg)
913{
5c02c033 914 FDCtrl *fdctrl = opaque;
baca51fa
FB		 915 uint32_t retval;
916
a18e67f5 917 reg &= 7;
e64d7d59 918 switch (reg) {
8c6a4d77
BS		 919 case FD_REG_SRA:
920 retval = fdctrl_read_statusA(fdctrl);
4f431960 921 break;
8c6a4d77 922 case FD_REG_SRB:
4f431960
JM		 923 retval = fdctrl_read_statusB(fdctrl);
924 break;
9fea808a 925 case FD_REG_DOR:
4f431960
JM		 926 retval = fdctrl_read_dor(fdctrl);
927 break;
9fea808a 928 case FD_REG_TDR:
baca51fa 929 retval = fdctrl_read_tape(fdctrl);
4f431960 930 break;
9fea808a 931 case FD_REG_MSR:
baca51fa 932 retval = fdctrl_read_main_status(fdctrl);
4f431960 933 break;
9fea808a 934 case FD_REG_FIFO:
baca51fa 935 retval = fdctrl_read_data(fdctrl);
4f431960 936 break;
9fea808a 937 case FD_REG_DIR:
baca51fa 938 retval = fdctrl_read_dir(fdctrl);
4f431960 939 break;
a541f297 940 default:
4f431960
JM		 941 retval = (uint32_t)(-1);
942 break;
a541f297 943 }
1a5396d9 944 trace_fdc_ioport_read(reg, retval);
baca51fa
FB		 945
946 return retval;
947}
948
949static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
950{
5c02c033 951 FDCtrl *fdctrl = opaque;
baca51fa 952
a18e67f5 953 reg &= 7;
1a5396d9 954 trace_fdc_ioport_write(reg, value);
e64d7d59 955 switch (reg) {
9fea808a 956 case FD_REG_DOR:
4f431960
JM		 957 fdctrl_write_dor(fdctrl, value);
958 break;
9fea808a 959 case FD_REG_TDR:
baca51fa 960 fdctrl_write_tape(fdctrl, value);
4f431960 961 break;
9fea808a 962 case FD_REG_DSR:
baca51fa 963 fdctrl_write_rate(fdctrl, value);
4f431960 964 break;
9fea808a 965 case FD_REG_FIFO:
baca51fa 966 fdctrl_write_data(fdctrl, value);
4f431960 967 break;
a758f8f4
HP		 968 case FD_REG_CCR:
969 fdctrl_write_ccr(fdctrl, value);
970 break;
a541f297 971 default:
4f431960 972 break;
a541f297 973 }
baca51fa
FB		 974}
975
a8170e5e 976static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
dc6c1b37 977 unsigned ize)
62a46c61 978{
5dcb6b91 979 return fdctrl_read(opaque, (uint32_t)reg);
62a46c61
FB		 980}
981
a8170e5e 982static void fdctrl_write_mem (void *opaque, hwaddr reg,
dc6c1b37 983 uint64_t value, unsigned size)
62a46c61 984{
5dcb6b91 985 fdctrl_write(opaque, (uint32_t)reg, value);
62a46c61
FB		 986}
987
dc6c1b37
AK		 988static const MemoryRegionOps fdctrl_mem_ops = {
989 .read = fdctrl_read_mem,
990 .write = fdctrl_write_mem,
991 .endianness = DEVICE_NATIVE_ENDIAN,
e80cfcfc
FB		 992};
993
dc6c1b37
AK		 994static const MemoryRegionOps fdctrl_mem_strict_ops = {
995 .read = fdctrl_read_mem,
996 .write = fdctrl_write_mem,
997 .endianness = DEVICE_NATIVE_ENDIAN,
998 .valid = {
999 .min_access_size = 1,
1000 .max_access_size = 1,
1001 },
7c560456
BS		 1002};
1003
7d905f71
JW		 1004static bool fdrive_media_changed_needed(void *opaque)
1005{
1006 FDrive *drive = opaque;
1007
abb3e55b 1008 return (drive->blk != NULL && drive->media_changed != 1);
7d905f71
JW		 1009}
1010
1011static const VMStateDescription vmstate_fdrive_media_changed = {
1012 .name = "fdrive/media_changed",
1013 .version_id = 1,
1014 .minimum_version_id = 1,
5cd8cada 1015 .needed = fdrive_media_changed_needed,
d49805ae 1016 .fields = (VMStateField[]) {
7d905f71
JW		 1017 VMSTATE_UINT8(media_changed, FDrive),
1018 VMSTATE_END_OF_LIST()
1019 }
1020};
1021
844f65d6
HP		 1022static bool fdrive_media_rate_needed(void *opaque)
1023{
1024 FDrive *drive = opaque;
1025
1026 return drive->fdctrl->check_media_rate;
1027}
1028
1029static const VMStateDescription vmstate_fdrive_media_rate = {
1030 .name = "fdrive/media_rate",
1031 .version_id = 1,
1032 .minimum_version_id = 1,
5cd8cada 1033 .needed = fdrive_media_rate_needed,
d49805ae 1034 .fields = (VMStateField[]) {
844f65d6
HP		 1035 VMSTATE_UINT8(media_rate, FDrive),
1036 VMSTATE_END_OF_LIST()
1037 }
1038};
1039
c0b92f30
PD		 1040static bool fdrive_perpendicular_needed(void *opaque)
1041{
1042 FDrive *drive = opaque;
1043
1044 return drive->perpendicular != 0;
1045}
1046
1047static const VMStateDescription vmstate_fdrive_perpendicular = {
1048 .name = "fdrive/perpendicular",
1049 .version_id = 1,
1050 .minimum_version_id = 1,
5cd8cada 1051 .needed = fdrive_perpendicular_needed,
c0b92f30
PD		 1052 .fields = (VMStateField[]) {
1053 VMSTATE_UINT8(perpendicular, FDrive),
1054 VMSTATE_END_OF_LIST()
1055 }
1056};
1057
1058static int fdrive_post_load(void *opaque, int version_id)
1059{
1060 fd_revalidate(opaque);
1061 return 0;
1062}
1063
d7a6c270
JQ		 1064static const VMStateDescription vmstate_fdrive = {
1065 .name = "fdrive",
1066 .version_id = 1,
1067 .minimum_version_id = 1,
c0b92f30 1068 .post_load = fdrive_post_load,
d49805ae 1069 .fields = (VMStateField[]) {
5c02c033
BS		 1070 VMSTATE_UINT8(head, FDrive),
1071 VMSTATE_UINT8(track, FDrive),
1072 VMSTATE_UINT8(sect, FDrive),
d7a6c270 1073 VMSTATE_END_OF_LIST()
7d905f71 1074 },
5cd8cada
JQ		 1075 .subsections = (const VMStateDescription*[]) {
1076 &vmstate_fdrive_media_changed,
1077 &vmstate_fdrive_media_rate,
1078 &vmstate_fdrive_perpendicular,
1079 NULL
d7a6c270
JQ		 1080 }
1081};
3ccacc4a 1082
85d291a0
KW		 1083/*
1084 * Reconstructs the phase from register values according to the logic that was
1085 * implemented in qemu 2.3. This is the default value that is used if the phase
1086 * subsection is not present on migration.
1087 *
1088 * Don't change this function to reflect newer qemu versions, it is part of
1089 * the migration ABI.
1090 */
1091static int reconstruct_phase(FDCtrl *fdctrl)
1092{
1093 if (fdctrl->msr & FD_MSR_NONDMA) {
1094 return FD_PHASE_EXECUTION;
1095 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
1096 /* qemu 2.3 disabled RQM only during DMA transfers */
1097 return FD_PHASE_EXECUTION;
1098 } else if (fdctrl->msr & FD_MSR_DIO) {
1099 return FD_PHASE_RESULT;
1100 } else {
1101 return FD_PHASE_COMMAND;
1102 }
1103}
1104
44b1ff31 1105static int fdc_pre_save(void *opaque)
3ccacc4a 1106{
5c02c033 1107 FDCtrl *s = opaque;
3ccacc4a 1108
d7a6c270 1109 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
44b1ff31
DDAG		 1110
1111 return 0;
3ccacc4a
BS		 1112}
1113
85d291a0
KW		 1114static int fdc_pre_load(void *opaque)
1115{
1116 FDCtrl *s = opaque;
1117 s->phase = FD_PHASE_RECONSTRUCT;
1118 return 0;
1119}
1120
e59fb374 1121static int fdc_post_load(void *opaque, int version_id)
3ccacc4a 1122{
5c02c033 1123 FDCtrl *s = opaque;
3ccacc4a 1124
d7a6c270
JQ		 1125 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
1126 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
85d291a0
KW		 1127
1128 if (s->phase == FD_PHASE_RECONSTRUCT) {
1129 s->phase = reconstruct_phase(s);
1130 }
1131
3ccacc4a
BS		 1132 return 0;
1133}
1134
c0b92f30
PD		 1135static bool fdc_reset_sensei_needed(void *opaque)
1136{
1137 FDCtrl *s = opaque;
1138
1139 return s->reset_sensei != 0;
1140}
1141
1142static const VMStateDescription vmstate_fdc_reset_sensei = {
1143 .name = "fdc/reset_sensei",
1144 .version_id = 1,
1145 .minimum_version_id = 1,
5cd8cada 1146 .needed = fdc_reset_sensei_needed,
c0b92f30
PD		 1147 .fields = (VMStateField[]) {
1148 VMSTATE_INT32(reset_sensei, FDCtrl),
1149 VMSTATE_END_OF_LIST()
1150 }
1151};
1152
1153static bool fdc_result_timer_needed(void *opaque)
1154{
1155 FDCtrl *s = opaque;
1156
1157 return timer_pending(s->result_timer);
1158}
1159
1160static const VMStateDescription vmstate_fdc_result_timer = {
1161 .name = "fdc/result_timer",
1162 .version_id = 1,
1163 .minimum_version_id = 1,
5cd8cada 1164 .needed = fdc_result_timer_needed,
c0b92f30 1165 .fields = (VMStateField[]) {
e720677e 1166 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
c0b92f30
PD		 1167 VMSTATE_END_OF_LIST()
1168 }
1169};
1170
85d291a0
KW		 1171static bool fdc_phase_needed(void *opaque)
1172{
1173 FDCtrl *fdctrl = opaque;
1174
1175 return reconstruct_phase(fdctrl) != fdctrl->phase;
1176}
1177
1178static const VMStateDescription vmstate_fdc_phase = {
1179 .name = "fdc/phase",
1180 .version_id = 1,
1181 .minimum_version_id = 1,
5cd8cada 1182 .needed = fdc_phase_needed,
85d291a0
KW		 1183 .fields = (VMStateField[]) {
1184 VMSTATE_UINT8(phase, FDCtrl),
1185 VMSTATE_END_OF_LIST()
1186 }
1187};
1188
d7a6c270 1189static const VMStateDescription vmstate_fdc = {
aef30c3c 1190 .name = "fdc",
d7a6c270
JQ		 1191 .version_id = 2,
1192 .minimum_version_id = 2,
d7a6c270 1193 .pre_save = fdc_pre_save,
85d291a0 1194 .pre_load = fdc_pre_load,
d7a6c270 1195 .post_load = fdc_post_load,
d49805ae 1196 .fields = (VMStateField[]) {
d7a6c270 1197 /* Controller State */
5c02c033
BS		 1198 VMSTATE_UINT8(sra, FDCtrl),
1199 VMSTATE_UINT8(srb, FDCtrl),
1200 VMSTATE_UINT8(dor_vmstate, FDCtrl),
1201 VMSTATE_UINT8(tdr, FDCtrl),
1202 VMSTATE_UINT8(dsr, FDCtrl),
1203 VMSTATE_UINT8(msr, FDCtrl),
1204 VMSTATE_UINT8(status0, FDCtrl),
1205 VMSTATE_UINT8(status1, FDCtrl),
1206 VMSTATE_UINT8(status2, FDCtrl),
d7a6c270 1207 /* Command FIFO */
8ec68b06
BS		 1208 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
1209 uint8_t),
5c02c033
BS		 1210 VMSTATE_UINT32(data_pos, FDCtrl),
1211 VMSTATE_UINT32(data_len, FDCtrl),
1212 VMSTATE_UINT8(data_state, FDCtrl),
1213 VMSTATE_UINT8(data_dir, FDCtrl),
1214 VMSTATE_UINT8(eot, FDCtrl),
d7a6c270 1215 /* States kept only to be returned back */
5c02c033
BS		 1216 VMSTATE_UINT8(timer0, FDCtrl),
1217 VMSTATE_UINT8(timer1, FDCtrl),
1218 VMSTATE_UINT8(precomp_trk, FDCtrl),
1219 VMSTATE_UINT8(config, FDCtrl),
1220 VMSTATE_UINT8(lock, FDCtrl),
1221 VMSTATE_UINT8(pwrd, FDCtrl),
d2164ad3 1222 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl, NULL),
5c02c033
BS		 1223 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
1224 vmstate_fdrive, FDrive),
d7a6c270 1225 VMSTATE_END_OF_LIST()
c0b92f30 1226 },
5cd8cada
JQ		 1227 .subsections = (const VMStateDescription*[]) {
1228 &vmstate_fdc_reset_sensei,
1229 &vmstate_fdc_result_timer,
1230 &vmstate_fdc_phase,
1231 NULL
78ae820c 1232 }
d7a6c270 1233};
3ccacc4a 1234
2be37833 1235static void fdctrl_external_reset_sysbus(DeviceState *d)
3ccacc4a 1236{
dd3be742 1237 FDCtrlSysBus *sys = SYSBUS_FDC(d);
5c02c033 1238 FDCtrl *s = &sys->state;
2be37833
BS		 1239
1240 fdctrl_reset(s, 0);
1241}
1242
1243static void fdctrl_external_reset_isa(DeviceState *d)
1244{
020c8e76 1245 FDCtrlISABus *isa = ISA_FDC(d);
5c02c033 1246 FDCtrl *s = &isa->state;
3ccacc4a
BS		 1247
1248 fdctrl_reset(s, 0);
1249}
1250
2be17ebd
BS		 1251static void fdctrl_handle_tc(void *opaque, int irq, int level)
1252{
5c02c033 1253 //FDCtrl *s = opaque;
2be17ebd
BS		 1254
1255 if (level) {
1256 // XXX
1257 FLOPPY_DPRINTF("TC pulsed\n");
1258 }
1259}
1260
8977f3c1 1261/* Change IRQ state */
5c02c033 1262static void fdctrl_reset_irq(FDCtrl *fdctrl)
8977f3c1 1263{
d497d534 1264 fdctrl->status0 = 0;
8c6a4d77
BS		 1265 if (!(fdctrl->sra & FD_SRA_INTPEND))
1266 return;
ed5fd2cc 1267 FLOPPY_DPRINTF("Reset interrupt\n");
d537cf6c 1268 qemu_set_irq(fdctrl->irq, 0);
8c6a4d77 1269 fdctrl->sra &= ~FD_SRA_INTPEND;
8977f3c1
FB		 1270}
1271
d497d534 1272static void fdctrl_raise_irq(FDCtrl *fdctrl)
8977f3c1 1273{
8c6a4d77 1274 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
d537cf6c 1275 qemu_set_irq(fdctrl->irq, 1);
8c6a4d77 1276 fdctrl->sra |= FD_SRA_INTPEND;
8977f3c1 1277 }
21fcf360 1278
f2d81b33 1279 fdctrl->reset_sensei = 0;
77370520 1280 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
8977f3c1
FB		 1281}
1282
4b19ec0c 1283/* Reset controller */
5c02c033 1284static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
8977f3c1
FB		 1285{
1286 int i;
1287
4b19ec0c 1288 FLOPPY_DPRINTF("reset controller\n");
baca51fa 1289 fdctrl_reset_irq(fdctrl);
4b19ec0c 1290 /* Initialise controller */
8c6a4d77
BS		 1291 fdctrl->sra = 0;
1292 fdctrl->srb = 0xc0;
4be74634 1293 if (!fdctrl->drives[1].blk) {
8c6a4d77 1294 fdctrl->sra |= FD_SRA_nDRV2;
4be74634 1295 }
baca51fa 1296 fdctrl->cur_drv = 0;
1c346df2 1297 fdctrl->dor = FD_DOR_nRESET;
368df94d 1298 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
b9b3d225 1299 fdctrl->msr = FD_MSR_RQM;
c0b92f30
PD		 1300 fdctrl->reset_sensei = 0;
1301 timer_del(fdctrl->result_timer);
8977f3c1 1302 /* FIFO state */
baca51fa
FB		 1303 fdctrl->data_pos = 0;
1304 fdctrl->data_len = 0;
b9b3d225 1305 fdctrl->data_state = 0;
baca51fa 1306 fdctrl->data_dir = FD_DIR_WRITE;
8977f3c1 1307 for (i = 0; i < MAX_FD; i++)
1c346df2 1308 fd_recalibrate(&fdctrl->drives[i]);
07e415f2 1309 fdctrl_to_command_phase(fdctrl);
77370520 1310 if (do_irq) {
d497d534
HP		 1311 fdctrl->status0 |= FD_SR0_RDYCHG;
1312 fdctrl_raise_irq(fdctrl);
f2d81b33 1313 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
77370520 1314 }
baca51fa
FB		 1315}
1316
5c02c033 1317static inline FDrive *drv0(FDCtrl *fdctrl)
baca51fa 1318{
46d3233b 1319 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
baca51fa
FB		 1320}
1321
5c02c033 1322static inline FDrive *drv1(FDCtrl *fdctrl)
baca51fa 1323{
46d3233b
BS		 1324 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1325 return &fdctrl->drives[1];
1326 else
1327 return &fdctrl->drives[0];
baca51fa
FB		 1328}
1329
78ae820c 1330#if MAX_FD == 4
5c02c033 1331static inline FDrive *drv2(FDCtrl *fdctrl)
78ae820c
BS		 1332{
1333 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1334 return &fdctrl->drives[2];
1335 else
1336 return &fdctrl->drives[1];
1337}
1338
5c02c033 1339static inline FDrive *drv3(FDCtrl *fdctrl)
78ae820c
BS		 1340{
1341 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1342 return &fdctrl->drives[3];
1343 else
1344 return &fdctrl->drives[2];
1345}
1346#endif
1347
394ea2ca 1348static FDrive *get_drv(FDCtrl *fdctrl, int unit)
baca51fa 1349{
394ea2ca 1350 switch (unit) {
78ae820c
BS		 1351 case 0: return drv0(fdctrl);
1352 case 1: return drv1(fdctrl);
1353#if MAX_FD == 4
1354 case 2: return drv2(fdctrl);
1355 case 3: return drv3(fdctrl);
1356#endif
1357 default: return NULL;
1358 }
8977f3c1
FB		 1359}
1360
394ea2ca
KW		 1361static FDrive *get_cur_drv(FDCtrl *fdctrl)
1362{
1363 return get_drv(fdctrl, fdctrl->cur_drv);
1364}
1365
8c6a4d77 1366/* Status A register : 0x00 (read-only) */
5c02c033 1367static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
8c6a4d77
BS		 1368{
1369 uint32_t retval = fdctrl->sra;
1370
1371 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1372
1373 return retval;
1374}
1375
8977f3c1 1376/* Status B register : 0x01 (read-only) */
5c02c033 1377static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
8977f3c1 1378{
8c6a4d77
BS		 1379 uint32_t retval = fdctrl->srb;
1380
1381 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1382
1383 return retval;
8977f3c1
FB		 1384}
1385
1386/* Digital output register : 0x02 */
5c02c033 1387static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
8977f3c1 1388{
1c346df2 1389 uint32_t retval = fdctrl->dor;
8977f3c1 1390
8977f3c1 1391 /* Selected drive */
baca51fa 1392 retval |= fdctrl->cur_drv;
8977f3c1
FB		 1393 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1394
1395 return retval;
1396}
1397
5c02c033 1398static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1399{
8977f3c1 1400 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
8c6a4d77
BS		 1401
1402 /* Motors */
1403 if (value & FD_DOR_MOTEN0)
1404 fdctrl->srb |= FD_SRB_MTR0;
1405 else
1406 fdctrl->srb &= ~FD_SRB_MTR0;
1407 if (value & FD_DOR_MOTEN1)
1408 fdctrl->srb |= FD_SRB_MTR1;
1409 else
1410 fdctrl->srb &= ~FD_SRB_MTR1;
1411
1412 /* Drive */
1413 if (value & 1)
1414 fdctrl->srb |= FD_SRB_DR0;
1415 else
1416 fdctrl->srb &= ~FD_SRB_DR0;
1417
8977f3c1 1418 /* Reset */
9fea808a 1419 if (!(value & FD_DOR_nRESET)) {
1c346df2 1420 if (fdctrl->dor & FD_DOR_nRESET) {
4b19ec0c 1421 FLOPPY_DPRINTF("controller enter RESET state\n");
8977f3c1
FB		 1422 }
1423 } else {
1c346df2 1424 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1425 FLOPPY_DPRINTF("controller out of RESET state\n");
fb6cf1d0 1426 fdctrl_reset(fdctrl, 1);
b9b3d225 1427 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
8977f3c1
FB		 1428 }
1429 }
1430 /* Selected drive */
9fea808a 1431 fdctrl->cur_drv = value & FD_DOR_SELMASK;
368df94d
BS		 1432
1433 fdctrl->dor = value;
8977f3c1
FB		 1434}
1435
1436/* Tape drive register : 0x03 */
5c02c033 1437static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
8977f3c1 1438{
46d3233b 1439 uint32_t retval = fdctrl->tdr;
8977f3c1 1440
8977f3c1
FB		 1441 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1442
1443 return retval;
1444}
1445
5c02c033 1446static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1447{
8977f3c1 1448 /* Reset mode */
1c346df2 1449 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1450 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 1451 return;
1452 }
1453 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1454 /* Disk boot selection indicator */
46d3233b 1455 fdctrl->tdr = value & FD_TDR_BOOTSEL;
8977f3c1
FB		 1456 /* Tape indicators: never allow */
1457}
1458
1459/* Main status register : 0x04 (read) */
5c02c033 1460static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
8977f3c1 1461{
b9b3d225 1462 uint32_t retval = fdctrl->msr;
8977f3c1 1463
b9b3d225 1464 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1c346df2 1465 fdctrl->dor |= FD_DOR_nRESET;
b9b3d225 1466
8977f3c1
FB		 1467 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1468
1469 return retval;
1470}
1471
1472/* Data select rate register : 0x04 (write) */
5c02c033 1473static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1474{
8977f3c1 1475 /* Reset mode */
1c346df2 1476 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4f431960
JM		 1477 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1478 return;
1479 }
8977f3c1
FB		 1480 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1481 /* Reset: autoclear */
9fea808a 1482 if (value & FD_DSR_SWRESET) {
1c346df2 1483 fdctrl->dor &= ~FD_DOR_nRESET;
baca51fa 1484 fdctrl_reset(fdctrl, 1);
1c346df2 1485 fdctrl->dor |= FD_DOR_nRESET;
8977f3c1 1486 }
9fea808a 1487 if (value & FD_DSR_PWRDOWN) {
baca51fa 1488 fdctrl_reset(fdctrl, 1);
8977f3c1 1489 }
b9b3d225 1490 fdctrl->dsr = value;
8977f3c1
FB		 1491}
1492
a758f8f4
HP		 1493/* Configuration control register: 0x07 (write) */
1494static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1495{
1496 /* Reset mode */
1497 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1498 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1499 return;
1500 }
1501 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1502
1503 /* Only the rate selection bits used in AT mode, and we
1504 * store those in the DSR.
1505 */
1506 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1507 (value & FD_DSR_DRATEMASK);
1508}
1509
5c02c033 1510static int fdctrl_media_changed(FDrive *drv)
ea185bbd 1511{
21fcf360 1512 return drv->media_changed;
ea185bbd
FB		 1513}
1514
8977f3c1 1515/* Digital input register : 0x07 (read-only) */
5c02c033 1516static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
8977f3c1 1517{
8977f3c1
FB		 1518 uint32_t retval = 0;
1519
a2df5fa3 1520 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
9fea808a 1521 retval |= FD_DIR_DSKCHG;
a2df5fa3 1522 }
3c83eb4f 1523 if (retval != 0) {
baca51fa 1524 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
3c83eb4f 1525 }
8977f3c1
FB		 1526
1527 return retval;
1528}
1529
07e415f2
KW		 1530/* Clear the FIFO and update the state for receiving the next command */
1531static void fdctrl_to_command_phase(FDCtrl *fdctrl)
8977f3c1 1532{
85d291a0 1533 fdctrl->phase = FD_PHASE_COMMAND;
baca51fa
FB		 1534 fdctrl->data_dir = FD_DIR_WRITE;
1535 fdctrl->data_pos = 0;
6cc8a11c 1536 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
b9b3d225 1537 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
6cc8a11c 1538 fdctrl->msr |= FD_MSR_RQM;
8977f3c1
FB		 1539}
1540
83a26013
KW		 1541/* Update the state to allow the guest to read out the command status.
1542 * @fifo_len is the number of result bytes to be read out. */
1543static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
8977f3c1 1544{
85d291a0 1545 fdctrl->phase = FD_PHASE_RESULT;
baca51fa
FB		 1546 fdctrl->data_dir = FD_DIR_READ;
1547 fdctrl->data_len = fifo_len;
1548 fdctrl->data_pos = 0;
b9b3d225 1549 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
8977f3c1
FB		 1550}
1551
1552/* Set an error: unimplemented/unknown command */
5c02c033 1553static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
8977f3c1 1554{
cced7a13
BS		 1555 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1556 fdctrl->fifo[0]);
9fea808a 1557 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 1558 fdctrl_to_result_phase(fdctrl, 1);
8977f3c1
FB		 1559}
1560
6be01b1e
PH		 1561/* Seek to next sector
1562 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1563 * otherwise returns 1
1564 */
5c02c033 1565static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
746d6de7
BS		 1566{
1567 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1568 cur_drv->head, cur_drv->track, cur_drv->sect,
1569 fd_sector(cur_drv));
1570 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1571 error in fact */
6be01b1e
PH		 1572 uint8_t new_head = cur_drv->head;
1573 uint8_t new_track = cur_drv->track;
1574 uint8_t new_sect = cur_drv->sect;
1575
1576 int ret = 1;
1577
1578 if (new_sect >= cur_drv->last_sect ||
1579 new_sect == fdctrl->eot) {
1580 new_sect = 1;
746d6de7 1581 if (FD_MULTI_TRACK(fdctrl->data_state)) {
6be01b1e 1582 if (new_head == 0 &&
746d6de7 1583 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
6be01b1e 1584 new_head = 1;
746d6de7 1585 } else {
6be01b1e
PH		 1586 new_head = 0;
1587 new_track++;
c5139bd9 1588 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1589 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1590 ret = 0;
1591 }
746d6de7
BS		 1592 }
1593 } else {
c5139bd9 1594 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1595 new_track++;
1596 ret = 0;
1597 }
1598 if (ret == 1) {
1599 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1600 new_head, new_track, new_sect, fd_sector(cur_drv));
746d6de7 1601 }
746d6de7 1602 } else {
6be01b1e 1603 new_sect++;
746d6de7 1604 }
6be01b1e
PH		 1605 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1606 return ret;
746d6de7
BS		 1607}
1608
8977f3c1 1609/* Callback for transfer end (stop or abort) */
5c02c033
BS		 1610static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1611 uint8_t status1, uint8_t status2)
8977f3c1 1612{
5c02c033 1613 FDrive *cur_drv;
baca51fa 1614 cur_drv = get_cur_drv(fdctrl);
075f5532
HP		 1615
1616 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1617 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1618 if (cur_drv->head) {
1619 fdctrl->status0 |= FD_SR0_HEAD;
1620 }
1621 fdctrl->status0 |= status0;
2fee0088 1622
8977f3c1 1623 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
2fee0088
PH		 1624 status0, status1, status2, fdctrl->status0);
1625 fdctrl->fifo[0] = fdctrl->status0;
baca51fa
FB		 1626 fdctrl->fifo[1] = status1;
1627 fdctrl->fifo[2] = status2;
1628 fdctrl->fifo[3] = cur_drv->track;
1629 fdctrl->fifo[4] = cur_drv->head;
1630 fdctrl->fifo[5] = cur_drv->sect;
1631 fdctrl->fifo[6] = FD_SECTOR_SC;
1632 fdctrl->data_dir = FD_DIR_READ;
441f6692 1633 if (fdctrl->dma_chann != -1 && !(fdctrl->msr & FD_MSR_NONDMA)) {
c8a35f1c
HP		 1634 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1635 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann);
ed5fd2cc 1636 }
b9b3d225 1637 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
368df94d 1638 fdctrl->msr &= ~FD_MSR_NONDMA;
34abf9a7 1639
83a26013 1640 fdctrl_to_result_phase(fdctrl, 7);
d497d534 1641 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1642}
1643
1644/* Prepare a data transfer (either DMA or FIFO) */
5c02c033 1645static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
8977f3c1 1646{
5c02c033 1647 FDrive *cur_drv;
8977f3c1 1648 uint8_t kh, kt, ks;
8977f3c1 1649
cefec4f5 1650 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1651 cur_drv = get_cur_drv(fdctrl);
1652 kt = fdctrl->fifo[2];
1653 kh = fdctrl->fifo[3];
1654 ks = fdctrl->fifo[4];
4b19ec0c 1655 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
cefec4f5 1656 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1657 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1658 NUM_SIDES(cur_drv)));
77370520 1659 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
8977f3c1
FB		 1660 case 2:
1661 /* sect too big */
9fea808a 1662 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1663 fdctrl->fifo[3] = kt;
1664 fdctrl->fifo[4] = kh;
1665 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1666 return;
1667 case 3:
1668 /* track too big */
77370520 1669 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1670 fdctrl->fifo[3] = kt;
1671 fdctrl->fifo[4] = kh;
1672 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1673 return;
1674 case 4:
1675 /* No seek enabled */
9fea808a 1676 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1677 fdctrl->fifo[3] = kt;
1678 fdctrl->fifo[4] = kh;
1679 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1680 return;
1681 case 1:
d6ed4e21 1682 fdctrl->status0 |= FD_SR0_SEEK;
8977f3c1
FB		 1683 break;
1684 default:
1685 break;
1686 }
b9b3d225 1687
844f65d6
HP		 1688 /* Check the data rate. If the programmed data rate does not match
1689 * the currently inserted medium, the operation has to fail. */
1690 if (fdctrl->check_media_rate &&
1691 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1692 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1693 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1694 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1695 fdctrl->fifo[3] = kt;
1696 fdctrl->fifo[4] = kh;
1697 fdctrl->fifo[5] = ks;
1698 return;
1699 }
1700
8977f3c1 1701 /* Set the FIFO state */
baca51fa
FB		 1702 fdctrl->data_dir = direction;
1703 fdctrl->data_pos = 0;
27c86e24 1704 assert(fdctrl->msr & FD_MSR_CMDBUSY);
baca51fa
FB		 1705 if (fdctrl->fifo[0] & 0x80)
1706 fdctrl->data_state |= FD_STATE_MULTI;
1707 else
1708 fdctrl->data_state &= ~FD_STATE_MULTI;
c83f97b5 1709 if (fdctrl->fifo[5] == 0) {
baca51fa
FB		 1710 fdctrl->data_len = fdctrl->fifo[8];
1711 } else {
4f431960 1712 int tmp;
3bcb80f1 1713 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
771effeb 1714 tmp = (fdctrl->fifo[6] - ks + 1);
baca51fa 1715 if (fdctrl->fifo[0] & 0x80)
771effeb 1716 tmp += fdctrl->fifo[6];
4f431960 1717 fdctrl->data_len *= tmp;
baca51fa 1718 }
890fa6be 1719 fdctrl->eot = fdctrl->fifo[6];
368df94d 1720 if (fdctrl->dor & FD_DOR_DMAEN) {
9e58f172 1721 /* DMA transfer is enabled. */
c8a35f1c 1722 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
9e58f172
SS		 1723
1724 FLOPPY_DPRINTF("direction=%d (%d - %d)\n",
1725 direction, (128 << fdctrl->fifo[5]) *
4f431960 1726 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
9e58f172
SS		 1727
1728 /* No access is allowed until DMA transfer has completed */
1729 fdctrl->msr &= ~FD_MSR_RQM;
1730 if (direction != FD_DIR_VERIFY) {
1731 /*
1732 * Now, we just have to wait for the DMA controller to
1733 * recall us...
1734 */
1735 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann);
1736 k->schedule(fdctrl->dma);
baca51fa 1737 } else {
9e58f172
SS		 1738 /* Start transfer */
1739 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1740 fdctrl->data_len);
8977f3c1 1741 }
9e58f172 1742 return;
8977f3c1
FB		 1743 }
1744 FLOPPY_DPRINTF("start non-DMA transfer\n");
6cc8a11c 1745 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
b9b3d225
BS		 1746 if (direction != FD_DIR_WRITE)
1747 fdctrl->msr |= FD_MSR_DIO;
8977f3c1 1748 /* IO based transfer: calculate len */
d497d534 1749 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1750}
1751
1752/* Prepare a transfer of deleted data */
5c02c033 1753static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
8977f3c1 1754{
cced7a13 1755 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
77370520 1756
8977f3c1
FB		 1757 /* We don't handle deleted data,
1758 * so we don't return *ANYTHING*
1759 */
9fea808a 1760 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
8977f3c1
FB		 1761}
1762
1763/* handlers for DMA transfers */
85571bc7
FB		 1764static int fdctrl_transfer_handler (void *opaque, int nchan,
1765 int dma_pos, int dma_len)
8977f3c1 1766{
5c02c033
BS		 1767 FDCtrl *fdctrl;
1768 FDrive *cur_drv;
baca51fa 1769 int len, start_pos, rel_pos;
8977f3c1 1770 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
c8a35f1c 1771 IsaDmaClass *k;
8977f3c1 1772
baca51fa 1773 fdctrl = opaque;
b9b3d225 1774 if (fdctrl->msr & FD_MSR_RQM) {
8977f3c1
FB		 1775 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1776 return 0;
1777 }
c8a35f1c 1778 k = ISADMA_GET_CLASS(fdctrl->dma);
baca51fa
FB		 1779 cur_drv = get_cur_drv(fdctrl);
1780 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1781 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1782 status2 = FD_SR2_SNS;
85571bc7
FB		 1783 if (dma_len > fdctrl->data_len)
1784 dma_len = fdctrl->data_len;
4be74634 1785 if (cur_drv->blk == NULL) {
4f431960 1786 if (fdctrl->data_dir == FD_DIR_WRITE)
9fea808a 1787 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
4f431960 1788 else
9fea808a 1789 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
4f431960 1790 len = 0;
890fa6be
FB		 1791 goto transfer_error;
1792 }
baca51fa 1793 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
85571bc7
FB		 1794 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1795 len = dma_len - fdctrl->data_pos;
baca51fa
FB		 1796 if (len + rel_pos > FD_SECTOR_LEN)
1797 len = FD_SECTOR_LEN - rel_pos;
6f7e9aec
FB		 1798 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1799 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
cefec4f5 1800 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
baca51fa 1801 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
9fea808a 1802 fd_sector(cur_drv) * FD_SECTOR_LEN);
baca51fa 1803 if (fdctrl->data_dir != FD_DIR_WRITE ||
4f431960 1804 len < FD_SECTOR_LEN || rel_pos != 0) {
baca51fa 1805 /* READ & SCAN commands and realign to a sector for WRITE */
a7a5b7c0
EB		 1806 if (blk_pread(cur_drv->blk, fd_offset(cur_drv),
1807 fdctrl->fifo, BDRV_SECTOR_SIZE) < 0) {
8977f3c1
FB		 1808 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1809 fd_sector(cur_drv));
1810 /* Sure, image size is too small... */
baca51fa 1811 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
8977f3c1 1812 }
890fa6be 1813 }
4f431960
JM		 1814 switch (fdctrl->data_dir) {
1815 case FD_DIR_READ:
1816 /* READ commands */
c8a35f1c
HP		 1817 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1818 fdctrl->data_pos, len);
4f431960
JM		 1819 break;
1820 case FD_DIR_WRITE:
baca51fa 1821 /* WRITE commands */
8510854e
HP		 1822 if (cur_drv->ro) {
1823 /* Handle readonly medium early, no need to do DMA, touch the
1824 * LED or attempt any writes. A real floppy doesn't attempt
1825 * to write to readonly media either. */
1826 fdctrl_stop_transfer(fdctrl,
1827 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1828 0x00);
1829 goto transfer_error;
1830 }
1831
c8a35f1c
HP		 1832 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1833 fdctrl->data_pos, len);
a7a5b7c0
EB		 1834 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv),
1835 fdctrl->fifo, BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13
BS		 1836 FLOPPY_DPRINTF("error writing sector %d\n",
1837 fd_sector(cur_drv));
9fea808a 1838 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 1839 goto transfer_error;
890fa6be 1840 }
4f431960 1841 break;
7ea004ed
HP		 1842 case FD_DIR_VERIFY:
1843 /* VERIFY commands */
1844 break;
4f431960
JM		 1845 default:
1846 /* SCAN commands */
baca51fa 1847 {
4f431960 1848 uint8_t tmpbuf[FD_SECTOR_LEN];
baca51fa 1849 int ret;
c8a35f1c
HP		 1850 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos,
1851 len);
baca51fa 1852 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
8977f3c1 1853 if (ret == 0) {
77370520 1854 status2 = FD_SR2_SEH;
8977f3c1
FB		 1855 goto end_transfer;
1856 }
baca51fa
FB		 1857 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1858 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
8977f3c1
FB		 1859 status2 = 0x00;
1860 goto end_transfer;
1861 }
1862 }
4f431960 1863 break;
8977f3c1 1864 }
4f431960
JM		 1865 fdctrl->data_pos += len;
1866 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
baca51fa 1867 if (rel_pos == 0) {
8977f3c1 1868 /* Seek to next sector */
746d6de7
BS		 1869 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1870 break;
8977f3c1
FB		 1871 }
1872 }
4f431960 1873 end_transfer:
baca51fa
FB		 1874 len = fdctrl->data_pos - start_pos;
1875 FLOPPY_DPRINTF("end transfer %d %d %d\n",
4f431960 1876 fdctrl->data_pos, len, fdctrl->data_len);
baca51fa
FB		 1877 if (fdctrl->data_dir == FD_DIR_SCANE ||
1878 fdctrl->data_dir == FD_DIR_SCANL ||
1879 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1880 status2 = FD_SR2_SEH;
baca51fa 1881 fdctrl->data_len -= len;
890fa6be 1882 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
4f431960 1883 transfer_error:
8977f3c1 1884
baca51fa 1885 return len;
8977f3c1
FB		 1886}
1887
8977f3c1 1888/* Data register : 0x05 */
5c02c033 1889static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
8977f3c1 1890{
5c02c033 1891 FDrive *cur_drv;
8977f3c1 1892 uint32_t retval = 0;
e9077462 1893 uint32_t pos;
8977f3c1 1894
baca51fa 1895 cur_drv = get_cur_drv(fdctrl);
b9b3d225
BS		 1896 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1897 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
cced7a13 1898 FLOPPY_DPRINTF("error: controller not ready for reading\n");
8977f3c1
FB		 1899 return 0;
1900 }
f6c2d1d8
KW		 1901
1902 /* If data_len spans multiple sectors, the current position in the FIFO
1903 * wraps around while fdctrl->data_pos is the real position in the whole
1904 * request. */
baca51fa 1905 pos = fdctrl->data_pos;
e9077462 1906 pos %= FD_SECTOR_LEN;
f6c2d1d8
KW		 1907
1908 switch (fdctrl->phase) {
1909 case FD_PHASE_EXECUTION:
1910 assert(fdctrl->msr & FD_MSR_NONDMA);
8977f3c1 1911 if (pos == 0) {
746d6de7
BS		 1912 if (fdctrl->data_pos != 0)
1913 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1914 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1915 fd_sector(cur_drv));
1916 return 0;
1917 }
a7a5b7c0
EB		 1918 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1919 BDRV_SECTOR_SIZE)
4be74634 1920 < 0) {
77370520
BS		 1921 FLOPPY_DPRINTF("error getting sector %d\n",
1922 fd_sector(cur_drv));
1923 /* Sure, image size is too small... */
1924 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1925 }
8977f3c1 1926 }
f6c2d1d8
KW		 1927
1928 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1929 fdctrl->msr &= ~FD_MSR_RQM;
c5139bd9 1930 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
f6c2d1d8
KW		 1931 }
1932 break;
1933
1934 case FD_PHASE_RESULT:
1935 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1936 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1937 fdctrl->msr &= ~FD_MSR_RQM;
07e415f2 1938 fdctrl_to_command_phase(fdctrl);
ed5fd2cc
FB		 1939 fdctrl_reset_irq(fdctrl);
1940 }
f6c2d1d8
KW		 1941 break;
1942
1943 case FD_PHASE_COMMAND:
1944 default:
1945 abort();
8977f3c1 1946 }
f6c2d1d8
KW		 1947
1948 retval = fdctrl->fifo[pos];
8977f3c1
FB		 1949 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1950
1951 return retval;
1952}
1953
5c02c033 1954static void fdctrl_format_sector(FDCtrl *fdctrl)
8977f3c1 1955{
5c02c033 1956 FDrive *cur_drv;
baca51fa 1957 uint8_t kh, kt, ks;
8977f3c1 1958
cefec4f5 1959 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1960 cur_drv = get_cur_drv(fdctrl);
1961 kt = fdctrl->fifo[6];
1962 kh = fdctrl->fifo[7];
1963 ks = fdctrl->fifo[8];
1964 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
cefec4f5 1965 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1966 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1967 NUM_SIDES(cur_drv)));
9fea808a 1968 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
baca51fa
FB		 1969 case 2:
1970 /* sect too big */
9fea808a 1971 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1972 fdctrl->fifo[3] = kt;
1973 fdctrl->fifo[4] = kh;
1974 fdctrl->fifo[5] = ks;
1975 return;
1976 case 3:
1977 /* track too big */
77370520 1978 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1979 fdctrl->fifo[3] = kt;
1980 fdctrl->fifo[4] = kh;
1981 fdctrl->fifo[5] = ks;
1982 return;
1983 case 4:
1984 /* No seek enabled */
9fea808a 1985 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1986 fdctrl->fifo[3] = kt;
1987 fdctrl->fifo[4] = kh;
1988 fdctrl->fifo[5] = ks;
1989 return;
1990 case 1:
cd30b53d 1991 fdctrl->status0 |= FD_SR0_SEEK;
baca51fa
FB		 1992 break;
1993 default:
1994 break;
1995 }
1996 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
4be74634 1997 if (cur_drv->blk == NULL ||
a7a5b7c0
EB		 1998 blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1999 BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13 2000 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
9fea808a 2001 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 2002 } else {
4f431960
JM		 2003 if (cur_drv->sect == cur_drv->last_sect) {
2004 fdctrl->data_state &= ~FD_STATE_FORMAT;
2005 /* Last sector done */
cd30b53d 2006 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
4f431960
JM		 2007 } else {
2008 /* More to do */
2009 fdctrl->data_pos = 0;
2010 fdctrl->data_len = 4;
2011 }
baca51fa
FB		 2012 }
2013}
2014
5c02c033 2015static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
65cef780
BS		 2016{
2017 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
2018 fdctrl->fifo[0] = fdctrl->lock << 4;
83a26013 2019 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2020}
2021
5c02c033 2022static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
65cef780 2023{
5c02c033 2024 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2025
2026 /* Drives position */
2027 fdctrl->fifo[0] = drv0(fdctrl)->track;
2028 fdctrl->fifo[1] = drv1(fdctrl)->track;
78ae820c
BS		 2029#if MAX_FD == 4
2030 fdctrl->fifo[2] = drv2(fdctrl)->track;
2031 fdctrl->fifo[3] = drv3(fdctrl)->track;
2032#else
65cef780
BS		 2033 fdctrl->fifo[2] = 0;
2034 fdctrl->fifo[3] = 0;
78ae820c 2035#endif
65cef780
BS		 2036 /* timers */
2037 fdctrl->fifo[4] = fdctrl->timer0;
368df94d 2038 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
65cef780
BS		 2039 fdctrl->fifo[6] = cur_drv->last_sect;
2040 fdctrl->fifo[7] = (fdctrl->lock << 7) |
2041 (cur_drv->perpendicular << 2);
2042 fdctrl->fifo[8] = fdctrl->config;
2043 fdctrl->fifo[9] = fdctrl->precomp_trk;
83a26013 2044 fdctrl_to_result_phase(fdctrl, 10);
65cef780
BS		 2045}
2046
5c02c033 2047static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
65cef780
BS		 2048{
2049 /* Controller's version */
2050 fdctrl->fifo[0] = fdctrl->version;
83a26013 2051 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2052}
2053
5c02c033 2054static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
65cef780
BS		 2055{
2056 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
83a26013 2057 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2058}
2059
5c02c033 2060static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
65cef780 2061{
5c02c033 2062 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2063
2064 /* Drives position */
2065 drv0(fdctrl)->track = fdctrl->fifo[3];
2066 drv1(fdctrl)->track = fdctrl->fifo[4];
78ae820c
BS		 2067#if MAX_FD == 4
2068 drv2(fdctrl)->track = fdctrl->fifo[5];
2069 drv3(fdctrl)->track = fdctrl->fifo[6];
2070#endif
65cef780
BS		 2071 /* timers */
2072 fdctrl->timer0 = fdctrl->fifo[7];
2073 fdctrl->timer1 = fdctrl->fifo[8];
2074 cur_drv->last_sect = fdctrl->fifo[9];
2075 fdctrl->lock = fdctrl->fifo[10] >> 7;
2076 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
2077 fdctrl->config = fdctrl->fifo[11];
2078 fdctrl->precomp_trk = fdctrl->fifo[12];
2079 fdctrl->pwrd = fdctrl->fifo[13];
07e415f2 2080 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2081}
2082
5c02c033 2083static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
65cef780 2084{
5c02c033 2085 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2086
2087 fdctrl->fifo[0] = 0;
2088 fdctrl->fifo[1] = 0;
2089 /* Drives position */
2090 fdctrl->fifo[2] = drv0(fdctrl)->track;
2091 fdctrl->fifo[3] = drv1(fdctrl)->track;
78ae820c
BS		 2092#if MAX_FD == 4
2093 fdctrl->fifo[4] = drv2(fdctrl)->track;
2094 fdctrl->fifo[5] = drv3(fdctrl)->track;
2095#else
65cef780
BS		 2096 fdctrl->fifo[4] = 0;
2097 fdctrl->fifo[5] = 0;
78ae820c 2098#endif
65cef780
BS		 2099 /* timers */
2100 fdctrl->fifo[6] = fdctrl->timer0;
2101 fdctrl->fifo[7] = fdctrl->timer1;
2102 fdctrl->fifo[8] = cur_drv->last_sect;
2103 fdctrl->fifo[9] = (fdctrl->lock << 7) |
2104 (cur_drv->perpendicular << 2);
2105 fdctrl->fifo[10] = fdctrl->config;
2106 fdctrl->fifo[11] = fdctrl->precomp_trk;
2107 fdctrl->fifo[12] = fdctrl->pwrd;
2108 fdctrl->fifo[13] = 0;
2109 fdctrl->fifo[14] = 0;
83a26013 2110 fdctrl_to_result_phase(fdctrl, 15);
65cef780
BS		 2111}
2112
5c02c033 2113static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
65cef780 2114{
5c02c033 2115 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 2116
65cef780 2117 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
73bcb24d
RS		 2118 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2119 (NANOSECONDS_PER_SECOND / 50));
65cef780
BS		 2120}
2121
5c02c033 2122static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
65cef780 2123{
5c02c033 2124 FDrive *cur_drv;
65cef780 2125
cefec4f5 2126 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2127 cur_drv = get_cur_drv(fdctrl);
2128 fdctrl->data_state |= FD_STATE_FORMAT;
2129 if (fdctrl->fifo[0] & 0x80)
2130 fdctrl->data_state |= FD_STATE_MULTI;
2131 else
2132 fdctrl->data_state &= ~FD_STATE_MULTI;
65cef780
BS		 2133 cur_drv->bps =
2134 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
2135#if 0
2136 cur_drv->last_sect =
2137 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
2138 fdctrl->fifo[3] / 2;
2139#else
2140 cur_drv->last_sect = fdctrl->fifo[3];
2141#endif
2142 /* TODO: implement format using DMA expected by the Bochs BIOS
2143 * and Linux fdformat (read 3 bytes per sector via DMA and fill
2144 * the sector with the specified fill byte
2145 */
2146 fdctrl->data_state &= ~FD_STATE_FORMAT;
2147 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2148}
2149
5c02c033 2150static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
65cef780
BS		 2151{
2152 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
2153 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
368df94d
BS		 2154 if (fdctrl->fifo[2] & 1)
2155 fdctrl->dor &= ~FD_DOR_DMAEN;
2156 else
2157 fdctrl->dor |= FD_DOR_DMAEN;
65cef780 2158 /* No result back */
07e415f2 2159 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2160}
2161
5c02c033 2162static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
65cef780 2163{
5c02c033 2164 FDrive *cur_drv;
65cef780 2165
cefec4f5 2166 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2167 cur_drv = get_cur_drv(fdctrl);
2168 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2169 /* 1 Byte status back */
2170 fdctrl->fifo[0] = (cur_drv->ro << 6) |
2171 (cur_drv->track == 0 ? 0x10 : 0x00) |
2172 (cur_drv->head << 2) |
cefec4f5 2173 GET_CUR_DRV(fdctrl) |
65cef780 2174 0x28;
83a26013 2175 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2176}
2177
5c02c033 2178static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
65cef780 2179{
5c02c033 2180 FDrive *cur_drv;
65cef780 2181
cefec4f5 2182 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2183 cur_drv = get_cur_drv(fdctrl);
2184 fd_recalibrate(cur_drv);
07e415f2 2185 fdctrl_to_command_phase(fdctrl);
65cef780 2186 /* Raise Interrupt */
d497d534
HP		 2187 fdctrl->status0 |= FD_SR0_SEEK;
2188 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2189}
2190
5c02c033 2191static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
65cef780 2192{
5c02c033 2193 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 2194
2fee0088 2195 if (fdctrl->reset_sensei > 0) {
f2d81b33
BS		 2196 fdctrl->fifo[0] =
2197 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
2198 fdctrl->reset_sensei--;
2fee0088
PH		 2199 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
2200 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 2201 fdctrl_to_result_phase(fdctrl, 1);
2fee0088 2202 return;
f2d81b33 2203 } else {
f2d81b33 2204 fdctrl->fifo[0] =
2fee0088
PH		 2205 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
2206 | GET_CUR_DRV(fdctrl);
f2d81b33
BS		 2207 }
2208
65cef780 2209 fdctrl->fifo[1] = cur_drv->track;
83a26013 2210 fdctrl_to_result_phase(fdctrl, 2);
65cef780 2211 fdctrl_reset_irq(fdctrl);
77370520 2212 fdctrl->status0 = FD_SR0_RDYCHG;
65cef780
BS		 2213}
2214
5c02c033 2215static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
65cef780 2216{
5c02c033 2217 FDrive *cur_drv;
65cef780 2218
cefec4f5 2219 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2220 cur_drv = get_cur_drv(fdctrl);
07e415f2 2221 fdctrl_to_command_phase(fdctrl);
b072a3c8
HP		 2222 /* The seek command just sends step pulses to the drive and doesn't care if
2223 * there is a medium inserted of if it's banging the head against the drive.
2224 */
6be01b1e 2225 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
b072a3c8 2226 /* Raise Interrupt */
d497d534
HP		 2227 fdctrl->status0 |= FD_SR0_SEEK;
2228 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2229}
2230
5c02c033 2231static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
65cef780 2232{
5c02c033 2233 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2234
2235 if (fdctrl->fifo[1] & 0x80)
2236 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
2237 /* No result back */
07e415f2 2238 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2239}
2240
5c02c033 2241static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
65cef780
BS		 2242{
2243 fdctrl->config = fdctrl->fifo[2];
2244 fdctrl->precomp_trk = fdctrl->fifo[3];
2245 /* No result back */
07e415f2 2246 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2247}
2248
5c02c033 2249static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
65cef780
BS		 2250{
2251 fdctrl->pwrd = fdctrl->fifo[1];
2252 fdctrl->fifo[0] = fdctrl->fifo[1];
83a26013 2253 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2254}
2255
5c02c033 2256static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
65cef780
BS		 2257{
2258 /* No result back */
07e415f2 2259 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2260}
2261
5c02c033 2262static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
65cef780 2263{
5c02c033 2264 FDrive *cur_drv = get_cur_drv(fdctrl);
e9077462 2265 uint32_t pos;
65cef780 2266
e9077462
PM		 2267 pos = fdctrl->data_pos - 1;
2268 pos %= FD_SECTOR_LEN;
2269 if (fdctrl->fifo[pos] & 0x80) {
65cef780 2270 /* Command parameters done */
e9077462 2271 if (fdctrl->fifo[pos] & 0x40) {
65cef780
BS		 2272 fdctrl->fifo[0] = fdctrl->fifo[1];
2273 fdctrl->fifo[2] = 0;
2274 fdctrl->fifo[3] = 0;
83a26013 2275 fdctrl_to_result_phase(fdctrl, 4);
65cef780 2276 } else {
07e415f2 2277 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2278 }
2279 } else if (fdctrl->data_len > 7) {
2280 /* ERROR */
2281 fdctrl->fifo[0] = 0x80 |
cefec4f5 2282 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
83a26013 2283 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2284 }
2285}
2286
6d013772 2287static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
65cef780 2288{
5c02c033 2289 FDrive *cur_drv;
65cef780 2290
cefec4f5 2291 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2292 cur_drv = get_cur_drv(fdctrl);
65cef780 2293 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
6be01b1e
PH		 2294 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2295 cur_drv->sect, 1);
65cef780 2296 } else {
6d013772
PH		 2297 fd_seek(cur_drv, cur_drv->head,
2298 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2299 }
07e415f2 2300 fdctrl_to_command_phase(fdctrl);
77370520 2301 /* Raise Interrupt */
d497d534
HP		 2302 fdctrl->status0 |= FD_SR0_SEEK;
2303 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2304}
2305
6d013772 2306static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
65cef780 2307{
5c02c033 2308 FDrive *cur_drv;
65cef780 2309
cefec4f5 2310 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2311 cur_drv = get_cur_drv(fdctrl);
65cef780 2312 if (fdctrl->fifo[2] > cur_drv->track) {
6be01b1e 2313 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
65cef780 2314 } else {
6d013772
PH		 2315 fd_seek(cur_drv, cur_drv->head,
2316 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2317 }
07e415f2 2318 fdctrl_to_command_phase(fdctrl);
65cef780 2319 /* Raise Interrupt */
d497d534
HP		 2320 fdctrl->status0 |= FD_SR0_SEEK;
2321 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2322}
2323
85d291a0
KW		 2324/*
2325 * Handlers for the execution phase of each command
2326 */
d275b33d 2327typedef struct FDCtrlCommand {
678803ab
BS		 2328 uint8_t value;
2329 uint8_t mask;
2330 const char* name;
2331 int parameters;
5c02c033 2332 void (*handler)(FDCtrl *fdctrl, int direction);
678803ab 2333 int direction;
d275b33d
KW		 2334} FDCtrlCommand;
2335
2336static const FDCtrlCommand handlers[] = {
678803ab
BS		 2337 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2338 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2339 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2340 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2341 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2342 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2343 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2344 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2345 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2346 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2347 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
7ea004ed 2348 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
678803ab
BS		 2349 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2350 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2351 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2352 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2353 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2354 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2355 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2356 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2357 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2358 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2359 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2360 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2361 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2362 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2363 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2364 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2365 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2366 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2367 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2368 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2369};
2370/* Associate command to an index in the 'handlers' array */
2371static uint8_t command_to_handler[256];
2372
d275b33d
KW		 2373static const FDCtrlCommand *get_command(uint8_t cmd)
2374{
2375 int idx;
2376
2377 idx = command_to_handler[cmd];
2378 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2379 return &handlers[idx];
2380}
2381
5c02c033 2382static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
baca51fa 2383{
5c02c033 2384 FDrive *cur_drv;
d275b33d 2385 const FDCtrlCommand *cmd;
e9077462 2386 uint32_t pos;
baca51fa 2387
8977f3c1 2388 /* Reset mode */
1c346df2 2389 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 2390 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 2391 return;
2392 }
b9b3d225 2393 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
cced7a13 2394 FLOPPY_DPRINTF("error: controller not ready for writing\n");
8977f3c1
FB		 2395 return;
2396 }
b9b3d225 2397 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
5b0a25e8 2398
d275b33d
KW		 2399 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2400
2401 /* If data_len spans multiple sectors, the current position in the FIFO
2402 * wraps around while fdctrl->data_pos is the real position in the whole
2403 * request. */
2404 pos = fdctrl->data_pos++;
2405 pos %= FD_SECTOR_LEN;
2406 fdctrl->fifo[pos] = value;
2407
6cc8a11c
KW		 2408 if (fdctrl->data_pos == fdctrl->data_len) {
2409 fdctrl->msr &= ~FD_MSR_RQM;
2410 }
2411
5b0a25e8
KW		 2412 switch (fdctrl->phase) {
2413 case FD_PHASE_EXECUTION:
2414 /* For DMA requests, RQM should be cleared during execution phase, so
2415 * we would have errored out above. */
2416 assert(fdctrl->msr & FD_MSR_NONDMA);
d275b33d 2417
8977f3c1 2418 /* FIFO data write */
b3bc1540 2419 if (pos == FD_SECTOR_LEN - 1 ||
baca51fa 2420 fdctrl->data_pos == fdctrl->data_len) {
77370520 2421 cur_drv = get_cur_drv(fdctrl);
a7a5b7c0
EB		 2422 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2423 BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13
BS		 2424 FLOPPY_DPRINTF("error writing sector %d\n",
2425 fd_sector(cur_drv));
5b0a25e8 2426 break;
77370520 2427 }
746d6de7
BS		 2428 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2429 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2430 fd_sector(cur_drv));
5b0a25e8 2431 break;
746d6de7 2432 }
8977f3c1 2433 }
d275b33d
KW		 2434
2435 /* Switch to result phase when done with the transfer */
2436 if (fdctrl->data_pos == fdctrl->data_len) {
c5139bd9 2437 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
d275b33d 2438 }
5b0a25e8 2439 break;
678803ab 2440
5b0a25e8
KW		 2441 case FD_PHASE_COMMAND:
2442 assert(!(fdctrl->msr & FD_MSR_NONDMA));
d275b33d 2443 assert(fdctrl->data_pos < FD_SECTOR_LEN);
5b0a25e8 2444
d275b33d
KW		 2445 if (pos == 0) {
2446 /* The first byte specifies the command. Now we start reading
2447 * as many parameters as this command requires. */
2448 cmd = get_command(value);
2449 fdctrl->data_len = cmd->parameters + 1;
6cc8a11c
KW		 2450 if (cmd->parameters) {
2451 fdctrl->msr |= FD_MSR_RQM;
2452 }
5b0a25e8 2453 fdctrl->msr |= FD_MSR_CMDBUSY;
8977f3c1 2454 }
65cef780 2455
5b0a25e8 2456 if (fdctrl->data_pos == fdctrl->data_len) {
d275b33d 2457 /* We have all parameters now, execute the command */
5b0a25e8 2458 fdctrl->phase = FD_PHASE_EXECUTION;
d275b33d 2459
5b0a25e8
KW		 2460 if (fdctrl->data_state & FD_STATE_FORMAT) {
2461 fdctrl_format_sector(fdctrl);
2462 break;
2463 }
2464
d275b33d
KW		 2465 cmd = get_command(fdctrl->fifo[0]);
2466 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2467 cmd->handler(fdctrl, cmd->direction);
5b0a25e8
KW		 2468 }
2469 break;
2470
2471 case FD_PHASE_RESULT:
2472 default:
2473 abort();
8977f3c1
FB		 2474 }
2475}
ed5fd2cc
FB		 2476
2477static void fdctrl_result_timer(void *opaque)
2478{
5c02c033
BS		 2479 FDCtrl *fdctrl = opaque;
2480 FDrive *cur_drv = get_cur_drv(fdctrl);
4f431960 2481
b7ffa3b1
TS		 2482 /* Pretend we are spinning.
2483 * This is needed for Coherent, which uses READ ID to check for
2484 * sector interleaving.
2485 */
2486 if (cur_drv->last_sect != 0) {
2487 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2488 }
844f65d6
HP		 2489 /* READ_ID can't automatically succeed! */
2490 if (fdctrl->check_media_rate &&
2491 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2492 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2493 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2494 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2495 } else {
2496 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2497 }
ed5fd2cc 2498}
678803ab
BS		 2499
2500/* Init functions */
6172e067
MA		 2501
2502static void fdctrl_init_drives(FloppyBus *bus, DriveInfo **fds)
2503{
2504 DeviceState *dev;
2505 int i;
2506
2507 for (i = 0; i < MAX_FD; i++) {
2508 if (fds[i]) {
2509 dev = qdev_new("floppy");
2510 qdev_prop_set_uint32(dev, "unit", i);
2511 qdev_prop_set_enum(dev, "drive-type", FLOPPY_DRIVE_TYPE_AUTO);
934df912
MA		 2512 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(fds[i]),
2513 &error_fatal);
6172e067
MA		 2514 qdev_realize_and_unref(dev, &bus->bus, &error_fatal);
2515 }
2516 }
2517}
2518
2519void isa_fdc_init_drives(ISADevice *fdc, DriveInfo **fds)
2520{
2521 fdctrl_init_drives(&ISA_FDC(fdc)->state.bus, fds);
2522}
2523
c0ca74f6
FZ		 2524static void fdctrl_connect_drives(FDCtrl *fdctrl, DeviceState *fdc_dev,
2525 Error **errp)
678803ab 2526{
12a71a02 2527 unsigned int i;
7d0d6950 2528 FDrive *drive;
394ea2ca 2529 DeviceState *dev;
a92bd191 2530 BlockBackend *blk;
394ea2ca 2531 Error *local_err = NULL;
4a27a638 2532 const char *fdc_name, *drive_suffix;
678803ab 2533
678803ab 2534 for (i = 0; i < MAX_FD; i++) {
7d0d6950 2535 drive = &fdctrl->drives[i];
844f65d6 2536 drive->fdctrl = fdctrl;
7d0d6950 2537
394ea2ca
KW		 2538 /* If the drive is not present, we skip creating the qdev device, but
2539 * still have to initialise the controller. */
a92bd191
KW		 2540 blk = fdctrl->qdev_for_drives[i].blk;
2541 if (!blk) {
394ea2ca
KW		 2542 fd_init(drive);
2543 fd_revalidate(drive);
2544 continue;
b47b3525
MA		 2545 }
2546
4a27a638
MA		 2547 fdc_name = object_get_typename(OBJECT(fdc_dev));
2548 drive_suffix = !strcmp(fdc_name, "SUNW,fdtwo") ? "" : i ? "B" : "A";
2549 warn_report("warning: property %s.drive%s is deprecated",
2550 fdc_name, drive_suffix);
2551 error_printf("Use -device floppy,unit=%d,drive=... instead.\n", i);
2552
3e80f690 2553 dev = qdev_new("floppy");
394ea2ca 2554 qdev_prop_set_uint32(dev, "unit", i);
a92bd191
KW		 2555 qdev_prop_set_enum(dev, "drive-type", fdctrl->qdev_for_drives[i].type);
2556
4a27a638
MA		 2557 /*
2558 * Hack alert: we move the backend from the floppy controller
2559 * device to the floppy device. We first need to detach the
2560 * controller, or else floppy_create()'s qdev_prop_set_drive()
2561 * will die when it attaches floppy device. We also need to
2562 * take another reference so that blk_detach_dev() doesn't
2563 * free blk while we still need it.
2564 *
2565 * The hack is probably a bad idea.
2566 */
a92bd191
KW		 2567 blk_ref(blk);
2568 blk_detach_dev(blk, fdc_dev);
2569 fdctrl->qdev_for_drives[i].blk = NULL;
934df912 2570 qdev_prop_set_drive_err(dev, "drive", blk, &local_err);
a92bd191
KW		 2571 blk_unref(blk);
2572
2573 if (local_err) {
2574 error_propagate(errp, local_err);
2575 return;
2576 }
2577
668f62ec 2578 if (!qdev_realize_and_unref(dev, &fdctrl->bus.bus, errp)) {
394ea2ca 2579 return;
7d0d6950 2580 }
678803ab 2581 }
678803ab
BS		 2582}
2583
63ffb564 2584void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
a8170e5e 2585 hwaddr mmio_base, DriveInfo **fds)
2091ba23 2586{
5c02c033 2587 FDCtrl *fdctrl;
2091ba23 2588 DeviceState *dev;
dd3be742 2589 SysBusDevice *sbd;
5c02c033 2590 FDCtrlSysBus *sys;
2091ba23 2591
3e80f690 2592 dev = qdev_new("sysbus-fdc");
dd3be742 2593 sys = SYSBUS_FDC(dev);
99244fa1
GH		 2594 fdctrl = &sys->state;
2595 fdctrl->dma_chann = dma_chann; /* FIXME */
dd3be742 2596 sbd = SYS_BUS_DEVICE(dev);
3c6ef471 2597 sysbus_realize_and_unref(sbd, &error_fatal);
dd3be742
HT		 2598 sysbus_connect_irq(sbd, 0, irq);
2599 sysbus_mmio_map(sbd, 0, mmio_base);
6172e067
MA		 2600
2601 fdctrl_init_drives(&sys->state.bus, fds);
678803ab
BS		 2602}
2603
a8170e5e 2604void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
63ffb564 2605 DriveInfo **fds, qemu_irq *fdc_tc)
678803ab 2606{
f64ab228 2607 DeviceState *dev;
5c02c033 2608 FDCtrlSysBus *sys;
678803ab 2609
3e80f690 2610 dev = qdev_new("SUNW,fdtwo");
3c6ef471 2611 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
dd3be742
HT		 2612 sys = SYSBUS_FDC(dev);
2613 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2614 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
f64ab228 2615 *fdc_tc = qdev_get_gpio_in(dev, 0);
6172e067
MA		 2616
2617 fdctrl_init_drives(&sys->state.bus, fds);
678803ab 2618}
f64ab228 2619
51e6e90e
KW		 2620static void fdctrl_realize_common(DeviceState *dev, FDCtrl *fdctrl,
2621 Error **errp)
f64ab228 2622{
12a71a02
BS		 2623 int i, j;
2624 static int command_tables_inited = 0;
f64ab228 2625
a73275dd
JS		 2626 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2627 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
07a978ef 2628 return;
a73275dd
JS		 2629 }
2630
12a71a02
BS		 2631 /* Fill 'command_to_handler' lookup table */
2632 if (!command_tables_inited) {
2633 command_tables_inited = 1;
2634 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2635 for (j = 0; j < sizeof(command_to_handler); j++) {
2636 if ((j & handlers[i].mask) == handlers[i].value) {
2637 command_to_handler[j] = i;
2638 }
2639 }
2640 }
2641 }
2642
2643 FLOPPY_DPRINTF("init controller\n");
2644 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
6653d131 2645 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
d7a6c270 2646 fdctrl->fifo_size = 512;
bc72ad67 2647 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
a3ef7a61 2648 fdctrl_result_timer, fdctrl);
12a71a02
BS		 2649
2650 fdctrl->version = 0x90; /* Intel 82078 controller */
2651 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
d7a6c270 2652 fdctrl->num_floppies = MAX_FD;
12a71a02 2653
a3ef7a61 2654 if (fdctrl->dma_chann != -1) {
c8a35f1c
HP		 2655 IsaDmaClass *k;
2656 assert(fdctrl->dma);
2657 k = ISADMA_GET_CLASS(fdctrl->dma);
2658 k->register_channel(fdctrl->dma, fdctrl->dma_chann,
2659 &fdctrl_transfer_handler, fdctrl);
a3ef7a61 2660 }
51e6e90e
KW		 2661
2662 floppy_bus_create(fdctrl, &fdctrl->bus, dev);
c0ca74f6 2663 fdctrl_connect_drives(fdctrl, dev, errp);
f64ab228
BS		 2664}
2665
212ec7ba 2666static const MemoryRegionPortio fdc_portio_list[] = {
2f290a8c 2667 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
212ec7ba
RH		 2668 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2669 PORTIO_END_OF_LIST(),
2f290a8c
RH		 2670};
2671
db895a1e 2672static void isabus_fdc_realize(DeviceState *dev, Error **errp)
8baf73ad 2673{
db895a1e 2674 ISADevice *isadev = ISA_DEVICE(dev);
020c8e76 2675 FDCtrlISABus *isa = ISA_FDC(dev);
5c02c033 2676 FDCtrl *fdctrl = &isa->state;
a3ef7a61 2677 Error *err = NULL;
8baf73ad 2678
e305a165
MAL		 2679 isa_register_portio_list(isadev, &fdctrl->portio_list,
2680 isa->iobase, fdc_portio_list, fdctrl,
db895a1e 2681 "fdc");
dee41d58 2682
db895a1e 2683 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
c9ae703d 2684 fdctrl->dma_chann = isa->dma;
c8a35f1c
HP		 2685 if (fdctrl->dma_chann != -1) {
2686 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
b3da5513
AK		 2687 if (!fdctrl->dma) {
2688 error_setg(errp, "ISA controller does not support DMA");
2689 return;
2690 }
c8a35f1c 2691 }
8baf73ad 2692
db895a1e 2693 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
51e6e90e 2694 fdctrl_realize_common(dev, fdctrl, &err);
a3ef7a61
AF		 2695 if (err != NULL) {
2696 error_propagate(errp, err);
db895a1e
AF		 2697 return;
2698 }
8baf73ad
GH		 2699}
2700
940194c2 2701static void sysbus_fdc_initfn(Object *obj)
12a71a02 2702{
19d46d71 2703 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
940194c2 2704 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
5c02c033 2705 FDCtrl *fdctrl = &sys->state;
12a71a02 2706
19d46d71
AF		 2707 fdctrl->dma_chann = -1;
2708
940194c2 2709 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2d256e6f 2710 "fdc", 0x08);
19d46d71 2711 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2
HT		 2712}
2713
19d46d71 2714static void sun4m_fdc_initfn(Object *obj)
940194c2 2715{
19d46d71
AF		 2716 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2717 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
940194c2 2718 FDCtrl *fdctrl = &sys->state;
940194c2 2719
dd446051
HP		 2720 fdctrl->dma_chann = -1;
2721
19d46d71
AF		 2722 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2723 fdctrl, "fdctrl", 0x08);
2724 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2 2725}
2be37833 2726
19d46d71 2727static void sysbus_fdc_common_initfn(Object *obj)
940194c2 2728{
19d46d71
AF		 2729 DeviceState *dev = DEVICE(obj);
2730 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
940194c2
HT		 2731 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2732 FDCtrl *fdctrl = &sys->state;
2733
19d46d71
AF		 2734 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2735
2736 sysbus_init_irq(sbd, &fdctrl->irq);
2737 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
12a71a02
BS		 2738}
2739
19d46d71 2740static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
12a71a02 2741{
dd3be742
HT		 2742 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2743 FDCtrl *fdctrl = &sys->state;
12a71a02 2744
51e6e90e 2745 fdctrl_realize_common(dev, fdctrl, errp);
12a71a02 2746}
f64ab228 2747
2da44dd0 2748FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
34d4260e 2749{
020c8e76 2750 FDCtrlISABus *isa = ISA_FDC(fdc);
34d4260e 2751
61a8d649 2752 return isa->state.drives[i].drive;
34d4260e
KW		 2753}
2754
ffdf43ed
GH		 2755static void isa_fdc_get_drive_max_chs(FloppyDriveType type, uint8_t *maxc,
2756 uint8_t *maxh, uint8_t *maxs)
e08fde0c
RK		 2757{
2758 const FDFormat *fdf;
2759
2760 *maxc = *maxh = *maxs = 0;
2761 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) {
2762 if (fdf->drive != type) {
2763 continue;
2764 }
2765 if (*maxc < fdf->max_track) {
2766 *maxc = fdf->max_track;
2767 }
2768 if (*maxh < fdf->max_head) {
2769 *maxh = fdf->max_head;
2770 }
2771 if (*maxs < fdf->last_sect) {
2772 *maxs = fdf->last_sect;
2773 }
2774 }
2775 (*maxc)--;
2776}
2777
2055dbc1
GH		 2778static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
2779{
2780 Aml *dev, *fdi;
2781 uint8_t maxc, maxh, maxs;
2782
2783 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
2784
2785 dev = aml_device("FLP%c", 'A' + idx);
2786
2787 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
2788
2789 fdi = aml_package(16);
2790 aml_append(fdi, aml_int(idx)); /* Drive Number */
2791 aml_append(fdi,
2792 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
2793 /*
2794 * the values below are the limits of the drive, and are thus independent
2795 * of the inserted media
2796 */
2797 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
2798 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
2799 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
2800 /*
2801 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
2802 * the drive type, so shall we
2803 */
2804 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
2805 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
2806 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
2807 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
2808 aml_append(fdi, aml_int(0x12)); /* disk_eot */
2809 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
2810 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
2811 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
2812 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
2813 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
2814 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
2815
2816 aml_append(dev, aml_name_decl("_FDI", fdi));
2817 return dev;
2818}
2819
89ed90e3
GH		 2820int cmos_get_fd_drive_type(FloppyDriveType fd0)
2821{
2822 int val;
2823
2824 switch (fd0) {
2825 case FLOPPY_DRIVE_TYPE_144:
2826 /* 1.44 Mb 3"5 drive */
2827 val = 4;
2828 break;
2829 case FLOPPY_DRIVE_TYPE_288:
2830 /* 2.88 Mb 3"5 drive */
2831 val = 5;
2832 break;
2833 case FLOPPY_DRIVE_TYPE_120:
2834 /* 1.2 Mb 5"5 drive */
2835 val = 2;
2836 break;
2837 case FLOPPY_DRIVE_TYPE_NONE:
2838 default:
2839 val = 0;
2840 break;
2841 }
2842 return val;
2843}
2844
2055dbc1
GH		 2845static void fdc_isa_build_aml(ISADevice *isadev, Aml *scope)
2846{
2847 Aml *dev;
2848 Aml *crs;
2849 int i;
2850
2851#define ACPI_FDE_MAX_FD 4
2852 uint32_t fde_buf[5] = {
2853 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
2854 cpu_to_le32(2) /* tape presence (2 == never present) */
2855 };
2856
2857 crs = aml_resource_template();
2858 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
2859 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
2860 aml_append(crs, aml_irq_no_flags(6));
2861 aml_append(crs,
2862 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
2863
2864 dev = aml_device("FDC0");
2865 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
2866 aml_append(dev, aml_name_decl("_CRS", crs));
2867
2868 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
2869 FloppyDriveType type = isa_fdc_get_drive_type(isadev, i);
2870
2871 if (type < FLOPPY_DRIVE_TYPE_NONE) {
2872 fde_buf[i] = cpu_to_le32(1); /* drive present */
2873 aml_append(dev, build_fdinfo_aml(i, type));
2874 }
2875 }
2876 aml_append(dev, aml_name_decl("_FDE",
2877 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
2878
2879 aml_append(scope, dev);
2880}
2881
a64405d1
JK		 2882static const VMStateDescription vmstate_isa_fdc ={
2883 .name = "fdc",
2884 .version_id = 2,
2885 .minimum_version_id = 2,
d49805ae 2886 .fields = (VMStateField[]) {
a64405d1
JK		 2887 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2888 VMSTATE_END_OF_LIST()
2889 }
2890};
2891
39bffca2 2892static Property isa_fdc_properties[] = {
c7bcc85d 2893 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
c9ae703d
HP		 2894 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2895 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
a92bd191
KW		 2896 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.qdev_for_drives[0].blk),
2897 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.qdev_for_drives[1].blk),
09c6d585
HP		 2898 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2899 0, true),
85bbd1e7 2900 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlISABus, state.qdev_for_drives[0].type,
fff4687b
JS		 2901 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2902 FloppyDriveType),
85bbd1e7 2903 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlISABus, state.qdev_for_drives[1].type,
fff4687b
JS		 2904 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2905 FloppyDriveType),
85bbd1e7 2906 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
4812fa27 2907 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type,
a73275dd 2908 FloppyDriveType),
39bffca2
AL		 2909 DEFINE_PROP_END_OF_LIST(),
2910};
2911
020c8e76 2912static void isabus_fdc_class_init(ObjectClass *klass, void *data)
8f04ee08 2913{
39bffca2 2914 DeviceClass *dc = DEVICE_CLASS(klass);
2055dbc1 2915 ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
db895a1e
AF		 2916
2917 dc->realize = isabus_fdc_realize;
39bffca2 2918 dc->fw_name = "fdc";
39bffca2
AL		 2919 dc->reset = fdctrl_external_reset_isa;
2920 dc->vmsd = &vmstate_isa_fdc;
2055dbc1 2921 isa->build_aml = fdc_isa_build_aml;
4f67d30b 2922 device_class_set_props(dc, isa_fdc_properties);
125ee0ed 2923 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
39bffca2
AL		 2924}
2925
81782b6a
GA		 2926static void isabus_fdc_instance_init(Object *obj)
2927{
2928 FDCtrlISABus *isa = ISA_FDC(obj);
2929
2930 device_add_bootindex_property(obj, &isa->bootindexA,
2931 "bootindexA", "/floppy@0",
40c2281c 2932 DEVICE(obj));
81782b6a
GA		 2933 device_add_bootindex_property(obj, &isa->bootindexB,
2934 "bootindexB", "/floppy@1",
40c2281c 2935 DEVICE(obj));
81782b6a
GA		 2936}
2937
8c43a6f0 2938static const TypeInfo isa_fdc_info = {
020c8e76 2939 .name = TYPE_ISA_FDC,
39bffca2
AL		 2940 .parent = TYPE_ISA_DEVICE,
2941 .instance_size = sizeof(FDCtrlISABus),
020c8e76 2942 .class_init = isabus_fdc_class_init,
81782b6a 2943 .instance_init = isabus_fdc_instance_init,
8baf73ad
GH		 2944};
2945
a64405d1
JK		 2946static const VMStateDescription vmstate_sysbus_fdc ={
2947 .name = "fdc",
2948 .version_id = 2,
2949 .minimum_version_id = 2,
d49805ae 2950 .fields = (VMStateField[]) {
a64405d1
JK		 2951 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2952 VMSTATE_END_OF_LIST()
2953 }
2954};
2955
999e12bb 2956static Property sysbus_fdc_properties[] = {
a92bd191
KW		 2957 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.qdev_for_drives[0].blk),
2958 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.qdev_for_drives[1].blk),
85bbd1e7 2959 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlSysBus, state.qdev_for_drives[0].type,
fff4687b
JS		 2960 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2961 FloppyDriveType),
85bbd1e7 2962 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlSysBus, state.qdev_for_drives[1].type,
fff4687b
JS		 2963 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2964 FloppyDriveType),
85bbd1e7 2965 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
a73275dd
JS		 2966 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2967 FloppyDriveType),
999e12bb 2968 DEFINE_PROP_END_OF_LIST(),
12a71a02
BS		 2969};
2970
999e12bb
AL		 2971static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2972{
39bffca2 2973 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2974
4f67d30b 2975 device_class_set_props(dc, sysbus_fdc_properties);
125ee0ed 2976 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2977}
2978
8c43a6f0 2979static const TypeInfo sysbus_fdc_info = {
19d46d71
AF		 2980 .name = "sysbus-fdc",
2981 .parent = TYPE_SYSBUS_FDC,
940194c2 2982 .instance_init = sysbus_fdc_initfn,
39bffca2 2983 .class_init = sysbus_fdc_class_init,
999e12bb
AL		 2984};
2985
2986static Property sun4m_fdc_properties[] = {
a92bd191 2987 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.qdev_for_drives[0].blk),
85bbd1e7 2988 DEFINE_PROP_SIGNED("fdtype", FDCtrlSysBus, state.qdev_for_drives[0].type,
fff4687b
JS		 2989 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2990 FloppyDriveType),
85bbd1e7 2991 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
a73275dd
JS		 2992 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2993 FloppyDriveType),
999e12bb
AL		 2994 DEFINE_PROP_END_OF_LIST(),
2995};
2996
2997static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2998{
39bffca2 2999 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 3000
4f67d30b 3001 device_class_set_props(dc, sun4m_fdc_properties);
125ee0ed 3002 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 3003}
3004
8c43a6f0 3005static const TypeInfo sun4m_fdc_info = {
39bffca2 3006 .name = "SUNW,fdtwo",
19d46d71 3007 .parent = TYPE_SYSBUS_FDC,
940194c2 3008 .instance_init = sun4m_fdc_initfn,
39bffca2 3009 .class_init = sun4m_fdc_class_init,
f64ab228
BS		 3010};
3011
19d46d71
AF		 3012static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
3013{
3014 DeviceClass *dc = DEVICE_CLASS(klass);
3015
3016 dc->realize = sysbus_fdc_common_realize;
3017 dc->reset = fdctrl_external_reset_sysbus;
3018 dc->vmsd = &vmstate_sysbus_fdc;
3019}
3020
3021static const TypeInfo sysbus_fdc_type_info = {
3022 .name = TYPE_SYSBUS_FDC,
3023 .parent = TYPE_SYS_BUS_DEVICE,
3024 .instance_size = sizeof(FDCtrlSysBus),
3025 .instance_init = sysbus_fdc_common_initfn,
3026 .abstract = true,
3027 .class_init = sysbus_fdc_common_class_init,
3028};
3029
83f7d43a 3030static void fdc_register_types(void)
f64ab228 3031{
39bffca2 3032 type_register_static(&isa_fdc_info);
19d46d71 3033 type_register_static(&sysbus_fdc_type_info);
39bffca2
AL		 3034 type_register_static(&sysbus_fdc_info);
3035 type_register_static(&sun4m_fdc_info);
51e6e90e 3036 type_register_static(&floppy_bus_info);
394ea2ca 3037 type_register_static(&floppy_drive_info);
f64ab228
BS		 3038}
3039
83f7d43a 3040type_init(fdc_register_types)
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