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Commit | Line | Data |
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29133e9a FB |
1 | /* |
2 | * CFI parallel flash with AMD command set emulation | |
5fafdf24 | 3 | * |
29133e9a FB |
4 | * Copyright (c) 2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
29133e9a FB |
18 | */ |
19 | ||
20 | /* | |
21 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
22 | * Supported commands/modes are: | |
23 | * - flash read | |
24 | * - flash write | |
25 | * - flash ID read | |
26 | * - sector erase | |
27 | * - chip erase | |
28 | * - unlock bypass command | |
29 | * - CFI queries | |
30 | * | |
31 | * It does not support flash interleaving. | |
32 | * It does not implement boot blocs with reduced size | |
33 | * It does not implement software data protection as found in many real chips | |
34 | * It does not implement erase suspend/resume commands | |
35 | * It does not implement multiple sectors erase | |
36 | */ | |
37 | ||
80c71a24 | 38 | #include "qemu/osdep.h" |
83c9f4ca | 39 | #include "hw/hw.h" |
0d09e41a | 40 | #include "hw/block/flash.h" |
da34e65c | 41 | #include "qapi/error.h" |
1de7afc9 | 42 | #include "qemu/timer.h" |
4be74634 | 43 | #include "sysemu/block-backend.h" |
022c62cb | 44 | #include "exec/address-spaces.h" |
1de7afc9 | 45 | #include "qemu/host-utils.h" |
83c9f4ca | 46 | #include "hw/sysbus.h" |
29133e9a FB |
47 | |
48 | //#define PFLASH_DEBUG | |
49 | #ifdef PFLASH_DEBUG | |
ec9ea489 PC |
50 | #define DPRINTF(fmt, ...) \ |
51 | do { \ | |
56f99ea1 | 52 | fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \ |
29133e9a FB |
53 | } while (0) |
54 | #else | |
001faf32 | 55 | #define DPRINTF(fmt, ...) do { } while (0) |
29133e9a FB |
56 | #endif |
57 | ||
661bfc80 JK |
58 | #define PFLASH_LAZY_ROMD_THRESHOLD 42 |
59 | ||
3509c396 HT |
60 | #define TYPE_CFI_PFLASH02 "cfi.pflash02" |
61 | #define CFI_PFLASH02(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH02) | |
62 | ||
c227f099 | 63 | struct pflash_t { |
3509c396 HT |
64 | /*< private >*/ |
65 | SysBusDevice parent_obj; | |
66 | /*< public >*/ | |
67 | ||
4be74634 | 68 | BlockBackend *blk; |
71db710f | 69 | uint32_t sector_len; |
368a354f | 70 | uint32_t nb_blocs; |
4fbd24ba | 71 | uint32_t chip_len; |
368a354f PC |
72 | uint8_t mappings; |
73 | uint8_t width; | |
74 | uint8_t be; | |
29133e9a FB |
75 | int wcycle; /* if 0, the flash is read normally */ |
76 | int bypass; | |
77 | int ro; | |
78 | uint8_t cmd; | |
79 | uint8_t status; | |
368a354f PC |
80 | /* FIXME: implement array device properties */ |
81 | uint16_t ident0; | |
82 | uint16_t ident1; | |
83 | uint16_t ident2; | |
84 | uint16_t ident3; | |
85 | uint16_t unlock_addr0; | |
86 | uint16_t unlock_addr1; | |
29133e9a FB |
87 | uint8_t cfi_len; |
88 | uint8_t cfi_table[0x52]; | |
89 | QEMUTimer *timer; | |
cfe5f011 AK |
90 | /* The device replicates the flash memory across its memory space. Emulate |
91 | * that by having a container (.mem) filled with an array of aliases | |
92 | * (.mem_mappings) pointing to the flash memory (.orig_mem). | |
93 | */ | |
94 | MemoryRegion mem; | |
95 | MemoryRegion *mem_mappings; /* array; one per mapping */ | |
96 | MemoryRegion orig_mem; | |
9c9bb6c8 | 97 | int rom_mode; |
661bfc80 | 98 | int read_counter; /* used for lazy switch-back to rom mode */ |
368a354f | 99 | char *name; |
29133e9a FB |
100 | void *storage; |
101 | }; | |
102 | ||
cfe5f011 AK |
103 | /* |
104 | * Set up replicated mappings of the same region. | |
105 | */ | |
106 | static void pflash_setup_mappings(pflash_t *pfl) | |
c8a50e59 | 107 | { |
cfe5f011 | 108 | unsigned i; |
a8170e5e | 109 | hwaddr size = memory_region_size(&pfl->orig_mem); |
cfe5f011 | 110 | |
2d256e6f | 111 | memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size); |
cfe5f011 AK |
112 | pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); |
113 | for (i = 0; i < pfl->mappings; ++i) { | |
2d256e6f PB |
114 | memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl), |
115 | "pflash-alias", &pfl->orig_mem, 0, size); | |
cfe5f011 AK |
116 | memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]); |
117 | } | |
118 | } | |
01e0451a | 119 | |
cfe5f011 AK |
120 | static void pflash_register_memory(pflash_t *pfl, int rom_mode) |
121 | { | |
5f9a5ea1 | 122 | memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode); |
bda254da | 123 | pfl->rom_mode = rom_mode; |
4fbd24ba AZ |
124 | } |
125 | ||
29133e9a FB |
126 | static void pflash_timer (void *opaque) |
127 | { | |
c227f099 | 128 | pflash_t *pfl = opaque; |
29133e9a FB |
129 | |
130 | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd); | |
131 | /* Reset flash */ | |
132 | pfl->status ^= 0x80; | |
133 | if (pfl->bypass) { | |
134 | pfl->wcycle = 2; | |
135 | } else { | |
4fbd24ba | 136 | pflash_register_memory(pfl, 1); |
29133e9a FB |
137 | pfl->wcycle = 0; |
138 | } | |
139 | pfl->cmd = 0; | |
140 | } | |
141 | ||
a8170e5e | 142 | static uint32_t pflash_read (pflash_t *pfl, hwaddr offset, |
5f9fc5ad | 143 | int width, int be) |
29133e9a | 144 | { |
a8170e5e | 145 | hwaddr boff; |
29133e9a FB |
146 | uint32_t ret; |
147 | uint8_t *p; | |
148 | ||
f8be67ee | 149 | DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset); |
29133e9a | 150 | ret = -1; |
661bfc80 JK |
151 | /* Lazy reset to ROMD mode after a certain amount of read accesses */ |
152 | if (!pfl->rom_mode && pfl->wcycle == 0 && | |
153 | ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { | |
154 | pflash_register_memory(pfl, 1); | |
0f459d16 | 155 | } |
4fbd24ba | 156 | offset &= pfl->chip_len - 1; |
29133e9a FB |
157 | boff = offset & 0xFF; |
158 | if (pfl->width == 2) | |
159 | boff = boff >> 1; | |
160 | else if (pfl->width == 4) | |
161 | boff = boff >> 2; | |
162 | switch (pfl->cmd) { | |
163 | default: | |
164 | /* This should never happen : reset state & treat it as a read*/ | |
165 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); | |
166 | pfl->wcycle = 0; | |
167 | pfl->cmd = 0; | |
30954850 | 168 | /* fall through to the read code */ |
29133e9a FB |
169 | case 0x80: |
170 | /* We accept reads during second unlock sequence... */ | |
171 | case 0x00: | |
172 | flash_read: | |
173 | /* Flash area read */ | |
174 | p = pfl->storage; | |
175 | switch (width) { | |
176 | case 1: | |
177 | ret = p[offset]; | |
178 | // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret); | |
179 | break; | |
180 | case 2: | |
5f9fc5ad BS |
181 | if (be) { |
182 | ret = p[offset] << 8; | |
183 | ret |= p[offset + 1]; | |
184 | } else { | |
185 | ret = p[offset]; | |
186 | ret |= p[offset + 1] << 8; | |
187 | } | |
29133e9a FB |
188 | // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret); |
189 | break; | |
190 | case 4: | |
5f9fc5ad BS |
191 | if (be) { |
192 | ret = p[offset] << 24; | |
193 | ret |= p[offset + 1] << 16; | |
194 | ret |= p[offset + 2] << 8; | |
195 | ret |= p[offset + 3]; | |
196 | } else { | |
197 | ret = p[offset]; | |
198 | ret |= p[offset + 1] << 8; | |
199 | ret |= p[offset + 2] << 16; | |
200 | ret |= p[offset + 3] << 24; | |
201 | } | |
29133e9a FB |
202 | // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret); |
203 | break; | |
204 | } | |
205 | break; | |
206 | case 0x90: | |
207 | /* flash ID read */ | |
208 | switch (boff) { | |
209 | case 0x00: | |
210 | case 0x01: | |
368a354f | 211 | ret = boff & 0x01 ? pfl->ident1 : pfl->ident0; |
29133e9a FB |
212 | break; |
213 | case 0x02: | |
214 | ret = 0x00; /* Pretend all sectors are unprotected */ | |
215 | break; | |
216 | case 0x0E: | |
217 | case 0x0F: | |
368a354f PC |
218 | ret = boff & 0x01 ? pfl->ident3 : pfl->ident2; |
219 | if (ret == (uint8_t)-1) { | |
29133e9a | 220 | goto flash_read; |
368a354f | 221 | } |
29133e9a FB |
222 | break; |
223 | default: | |
224 | goto flash_read; | |
225 | } | |
b9055c3c | 226 | DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret); |
29133e9a FB |
227 | break; |
228 | case 0xA0: | |
229 | case 0x10: | |
230 | case 0x30: | |
231 | /* Status register read */ | |
232 | ret = pfl->status; | |
233 | DPRINTF("%s: status %x\n", __func__, ret); | |
234 | /* Toggle bit 6 */ | |
235 | pfl->status ^= 0x40; | |
236 | break; | |
237 | case 0x98: | |
238 | /* CFI query mode */ | |
239 | if (boff > pfl->cfi_len) | |
240 | ret = 0; | |
241 | else | |
242 | ret = pfl->cfi_table[boff]; | |
243 | break; | |
244 | } | |
245 | ||
246 | return ret; | |
247 | } | |
248 | ||
249 | /* update flash content on disk */ | |
c227f099 | 250 | static void pflash_update(pflash_t *pfl, int offset, |
29133e9a FB |
251 | int size) |
252 | { | |
253 | int offset_end; | |
4be74634 | 254 | if (pfl->blk) { |
29133e9a FB |
255 | offset_end = offset + size; |
256 | /* round to sectors */ | |
257 | offset = offset >> 9; | |
258 | offset_end = (offset_end + 511) >> 9; | |
4be74634 MA |
259 | blk_write(pfl->blk, offset, pfl->storage + (offset << 9), |
260 | offset_end - offset); | |
29133e9a FB |
261 | } |
262 | } | |
263 | ||
a8170e5e | 264 | static void pflash_write (pflash_t *pfl, hwaddr offset, |
5f9fc5ad | 265 | uint32_t value, int width, int be) |
29133e9a | 266 | { |
a8170e5e | 267 | hwaddr boff; |
29133e9a FB |
268 | uint8_t *p; |
269 | uint8_t cmd; | |
270 | ||
95d1f3ed JM |
271 | cmd = value; |
272 | if (pfl->cmd != 0xA0 && cmd == 0xF0) { | |
273 | #if 0 | |
274 | DPRINTF("%s: flash reset asked (%02x %02x)\n", | |
275 | __func__, pfl->cmd, cmd); | |
276 | #endif | |
277 | goto reset_flash; | |
278 | } | |
f8be67ee | 279 | DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__, |
95d1f3ed | 280 | offset, value, width, pfl->wcycle); |
4fbd24ba | 281 | offset &= pfl->chip_len - 1; |
3b46e624 | 282 | |
f8be67ee | 283 | DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__, |
e96efcfc | 284 | offset, value, width); |
29133e9a FB |
285 | boff = offset & (pfl->sector_len - 1); |
286 | if (pfl->width == 2) | |
287 | boff = boff >> 1; | |
288 | else if (pfl->width == 4) | |
289 | boff = boff >> 2; | |
290 | switch (pfl->wcycle) { | |
291 | case 0: | |
9c9bb6c8 AZ |
292 | /* Set the device in I/O access mode if required */ |
293 | if (pfl->rom_mode) | |
294 | pflash_register_memory(pfl, 0); | |
661bfc80 | 295 | pfl->read_counter = 0; |
29133e9a FB |
296 | /* We're in read mode */ |
297 | check_unlock0: | |
298 | if (boff == 0x55 && cmd == 0x98) { | |
299 | enter_CFI_mode: | |
300 | /* Enter CFI query mode */ | |
301 | pfl->wcycle = 7; | |
302 | pfl->cmd = 0x98; | |
303 | return; | |
304 | } | |
368a354f | 305 | if (boff != pfl->unlock_addr0 || cmd != 0xAA) { |
f8be67ee | 306 | DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", |
368a354f | 307 | __func__, boff, cmd, pfl->unlock_addr0); |
29133e9a FB |
308 | goto reset_flash; |
309 | } | |
310 | DPRINTF("%s: unlock sequence started\n", __func__); | |
311 | break; | |
312 | case 1: | |
313 | /* We started an unlock sequence */ | |
314 | check_unlock1: | |
368a354f | 315 | if (boff != pfl->unlock_addr1 || cmd != 0x55) { |
f8be67ee | 316 | DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, |
e96efcfc | 317 | boff, cmd); |
29133e9a FB |
318 | goto reset_flash; |
319 | } | |
320 | DPRINTF("%s: unlock sequence done\n", __func__); | |
321 | break; | |
322 | case 2: | |
323 | /* We finished an unlock sequence */ | |
368a354f | 324 | if (!pfl->bypass && boff != pfl->unlock_addr0) { |
f8be67ee | 325 | DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, |
e96efcfc | 326 | boff, cmd); |
29133e9a FB |
327 | goto reset_flash; |
328 | } | |
329 | switch (cmd) { | |
330 | case 0x20: | |
331 | pfl->bypass = 1; | |
332 | goto do_bypass; | |
333 | case 0x80: | |
334 | case 0x90: | |
335 | case 0xA0: | |
336 | pfl->cmd = cmd; | |
337 | DPRINTF("%s: starting command %02x\n", __func__, cmd); | |
338 | break; | |
339 | default: | |
340 | DPRINTF("%s: unknown command %02x\n", __func__, cmd); | |
341 | goto reset_flash; | |
342 | } | |
343 | break; | |
344 | case 3: | |
345 | switch (pfl->cmd) { | |
346 | case 0x80: | |
347 | /* We need another unlock sequence */ | |
348 | goto check_unlock0; | |
349 | case 0xA0: | |
f8be67ee | 350 | DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n", |
29133e9a FB |
351 | __func__, offset, value, width); |
352 | p = pfl->storage; | |
de8efe8f JJ |
353 | if (!pfl->ro) { |
354 | switch (width) { | |
355 | case 1: | |
5f9fc5ad | 356 | p[offset] &= value; |
de8efe8f JJ |
357 | pflash_update(pfl, offset, 1); |
358 | break; | |
359 | case 2: | |
360 | if (be) { | |
361 | p[offset] &= value >> 8; | |
362 | p[offset + 1] &= value; | |
363 | } else { | |
364 | p[offset] &= value; | |
365 | p[offset + 1] &= value >> 8; | |
366 | } | |
367 | pflash_update(pfl, offset, 2); | |
368 | break; | |
369 | case 4: | |
370 | if (be) { | |
371 | p[offset] &= value >> 24; | |
372 | p[offset + 1] &= value >> 16; | |
373 | p[offset + 2] &= value >> 8; | |
374 | p[offset + 3] &= value; | |
375 | } else { | |
376 | p[offset] &= value; | |
377 | p[offset + 1] &= value >> 8; | |
378 | p[offset + 2] &= value >> 16; | |
379 | p[offset + 3] &= value >> 24; | |
380 | } | |
381 | pflash_update(pfl, offset, 4); | |
382 | break; | |
5f9fc5ad | 383 | } |
29133e9a FB |
384 | } |
385 | pfl->status = 0x00 | ~(value & 0x80); | |
386 | /* Let's pretend write is immediate */ | |
387 | if (pfl->bypass) | |
388 | goto do_bypass; | |
389 | goto reset_flash; | |
390 | case 0x90: | |
391 | if (pfl->bypass && cmd == 0x00) { | |
392 | /* Unlock bypass reset */ | |
393 | goto reset_flash; | |
394 | } | |
395 | /* We can enter CFI query mode from autoselect mode */ | |
396 | if (boff == 0x55 && cmd == 0x98) | |
397 | goto enter_CFI_mode; | |
398 | /* No break here */ | |
399 | default: | |
400 | DPRINTF("%s: invalid write for command %02x\n", | |
401 | __func__, pfl->cmd); | |
402 | goto reset_flash; | |
403 | } | |
404 | case 4: | |
405 | switch (pfl->cmd) { | |
406 | case 0xA0: | |
a1c7273b | 407 | /* Ignore writes while flash data write is occurring */ |
29133e9a FB |
408 | /* As we suppose write is immediate, this should never happen */ |
409 | return; | |
410 | case 0x80: | |
411 | goto check_unlock1; | |
412 | default: | |
413 | /* Should never happen */ | |
414 | DPRINTF("%s: invalid command state %02x (wc 4)\n", | |
415 | __func__, pfl->cmd); | |
416 | goto reset_flash; | |
417 | } | |
418 | break; | |
419 | case 5: | |
420 | switch (cmd) { | |
421 | case 0x10: | |
368a354f | 422 | if (boff != pfl->unlock_addr0) { |
f8be67ee | 423 | DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", |
29133e9a FB |
424 | __func__, offset); |
425 | goto reset_flash; | |
426 | } | |
427 | /* Chip erase */ | |
428 | DPRINTF("%s: start chip erase\n", __func__); | |
de8efe8f JJ |
429 | if (!pfl->ro) { |
430 | memset(pfl->storage, 0xFF, pfl->chip_len); | |
431 | pflash_update(pfl, 0, pfl->chip_len); | |
432 | } | |
29133e9a | 433 | pfl->status = 0x00; |
29133e9a | 434 | /* Let's wait 5 seconds before chip erase is done */ |
73bcb24d RS |
435 | timer_mod(pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
436 | (NANOSECONDS_PER_SECOND * 5)); | |
29133e9a FB |
437 | break; |
438 | case 0x30: | |
439 | /* Sector erase */ | |
440 | p = pfl->storage; | |
441 | offset &= ~(pfl->sector_len - 1); | |
f8be67ee | 442 | DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__, |
e96efcfc | 443 | offset); |
de8efe8f JJ |
444 | if (!pfl->ro) { |
445 | memset(p + offset, 0xFF, pfl->sector_len); | |
446 | pflash_update(pfl, offset, pfl->sector_len); | |
447 | } | |
29133e9a FB |
448 | pfl->status = 0x00; |
449 | /* Let's wait 1/2 second before sector erase is done */ | |
73bcb24d RS |
450 | timer_mod(pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
451 | (NANOSECONDS_PER_SECOND / 2)); | |
29133e9a FB |
452 | break; |
453 | default: | |
454 | DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); | |
455 | goto reset_flash; | |
456 | } | |
457 | pfl->cmd = cmd; | |
458 | break; | |
459 | case 6: | |
460 | switch (pfl->cmd) { | |
461 | case 0x10: | |
462 | /* Ignore writes during chip erase */ | |
463 | return; | |
464 | case 0x30: | |
465 | /* Ignore writes during sector erase */ | |
466 | return; | |
467 | default: | |
468 | /* Should never happen */ | |
469 | DPRINTF("%s: invalid command state %02x (wc 6)\n", | |
470 | __func__, pfl->cmd); | |
471 | goto reset_flash; | |
472 | } | |
473 | break; | |
474 | case 7: /* Special value for CFI queries */ | |
475 | DPRINTF("%s: invalid write in CFI query mode\n", __func__); | |
476 | goto reset_flash; | |
477 | default: | |
478 | /* Should never happen */ | |
479 | DPRINTF("%s: invalid write state (wc 7)\n", __func__); | |
480 | goto reset_flash; | |
481 | } | |
482 | pfl->wcycle++; | |
483 | ||
484 | return; | |
485 | ||
486 | /* Reset flash */ | |
487 | reset_flash: | |
29133e9a FB |
488 | pfl->bypass = 0; |
489 | pfl->wcycle = 0; | |
490 | pfl->cmd = 0; | |
491 | return; | |
492 | ||
493 | do_bypass: | |
494 | pfl->wcycle = 2; | |
495 | pfl->cmd = 0; | |
29133e9a FB |
496 | } |
497 | ||
498 | ||
a8170e5e | 499 | static uint32_t pflash_readb_be(void *opaque, hwaddr addr) |
5f9fc5ad BS |
500 | { |
501 | return pflash_read(opaque, addr, 1, 1); | |
502 | } | |
503 | ||
a8170e5e | 504 | static uint32_t pflash_readb_le(void *opaque, hwaddr addr) |
5f9fc5ad BS |
505 | { |
506 | return pflash_read(opaque, addr, 1, 0); | |
507 | } | |
508 | ||
a8170e5e | 509 | static uint32_t pflash_readw_be(void *opaque, hwaddr addr) |
5f9fc5ad BS |
510 | { |
511 | pflash_t *pfl = opaque; | |
512 | ||
513 | return pflash_read(pfl, addr, 2, 1); | |
514 | } | |
515 | ||
a8170e5e | 516 | static uint32_t pflash_readw_le(void *opaque, hwaddr addr) |
5f9fc5ad BS |
517 | { |
518 | pflash_t *pfl = opaque; | |
519 | ||
520 | return pflash_read(pfl, addr, 2, 0); | |
521 | } | |
522 | ||
a8170e5e | 523 | static uint32_t pflash_readl_be(void *opaque, hwaddr addr) |
29133e9a | 524 | { |
5f9fc5ad BS |
525 | pflash_t *pfl = opaque; |
526 | ||
527 | return pflash_read(pfl, addr, 4, 1); | |
29133e9a FB |
528 | } |
529 | ||
a8170e5e | 530 | static uint32_t pflash_readl_le(void *opaque, hwaddr addr) |
29133e9a | 531 | { |
c227f099 | 532 | pflash_t *pfl = opaque; |
29133e9a | 533 | |
5f9fc5ad BS |
534 | return pflash_read(pfl, addr, 4, 0); |
535 | } | |
536 | ||
a8170e5e | 537 | static void pflash_writeb_be(void *opaque, hwaddr addr, |
5f9fc5ad BS |
538 | uint32_t value) |
539 | { | |
540 | pflash_write(opaque, addr, value, 1, 1); | |
29133e9a FB |
541 | } |
542 | ||
a8170e5e | 543 | static void pflash_writeb_le(void *opaque, hwaddr addr, |
5f9fc5ad BS |
544 | uint32_t value) |
545 | { | |
546 | pflash_write(opaque, addr, value, 1, 0); | |
547 | } | |
548 | ||
a8170e5e | 549 | static void pflash_writew_be(void *opaque, hwaddr addr, |
5f9fc5ad | 550 | uint32_t value) |
29133e9a | 551 | { |
c227f099 | 552 | pflash_t *pfl = opaque; |
29133e9a | 553 | |
5f9fc5ad | 554 | pflash_write(pfl, addr, value, 2, 1); |
29133e9a FB |
555 | } |
556 | ||
a8170e5e | 557 | static void pflash_writew_le(void *opaque, hwaddr addr, |
5f9fc5ad | 558 | uint32_t value) |
29133e9a | 559 | { |
5f9fc5ad BS |
560 | pflash_t *pfl = opaque; |
561 | ||
562 | pflash_write(pfl, addr, value, 2, 0); | |
29133e9a FB |
563 | } |
564 | ||
a8170e5e | 565 | static void pflash_writel_be(void *opaque, hwaddr addr, |
5f9fc5ad | 566 | uint32_t value) |
29133e9a | 567 | { |
c227f099 | 568 | pflash_t *pfl = opaque; |
29133e9a | 569 | |
5f9fc5ad | 570 | pflash_write(pfl, addr, value, 4, 1); |
29133e9a FB |
571 | } |
572 | ||
a8170e5e | 573 | static void pflash_writel_le(void *opaque, hwaddr addr, |
5f9fc5ad | 574 | uint32_t value) |
29133e9a | 575 | { |
c227f099 | 576 | pflash_t *pfl = opaque; |
29133e9a | 577 | |
5f9fc5ad | 578 | pflash_write(pfl, addr, value, 4, 0); |
29133e9a FB |
579 | } |
580 | ||
cfe5f011 AK |
581 | static const MemoryRegionOps pflash_cfi02_ops_be = { |
582 | .old_mmio = { | |
583 | .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, | |
584 | .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, | |
585 | }, | |
586 | .endianness = DEVICE_NATIVE_ENDIAN, | |
5f9fc5ad BS |
587 | }; |
588 | ||
cfe5f011 AK |
589 | static const MemoryRegionOps pflash_cfi02_ops_le = { |
590 | .old_mmio = { | |
591 | .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, | |
592 | .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, | |
593 | }, | |
594 | .endianness = DEVICE_NATIVE_ENDIAN, | |
29133e9a FB |
595 | }; |
596 | ||
da3bd642 | 597 | static void pflash_cfi02_realize(DeviceState *dev, Error **errp) |
29133e9a | 598 | { |
3509c396 | 599 | pflash_t *pfl = CFI_PFLASH02(dev); |
368a354f | 600 | uint32_t chip_len; |
d0e7605e | 601 | int ret; |
33e0eb52 | 602 | Error *local_err = NULL; |
29133e9a | 603 | |
368a354f | 604 | chip_len = pfl->sector_len * pfl->nb_blocs; |
29133e9a | 605 | /* XXX: to be fixed */ |
95d1f3ed | 606 | #if 0 |
29133e9a FB |
607 | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && |
608 | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) | |
609 | return NULL; | |
95d1f3ed | 610 | #endif |
368a354f | 611 | |
2d256e6f | 612 | memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), pfl->be ? |
368a354f | 613 | &pflash_cfi02_ops_be : &pflash_cfi02_ops_le, |
33e0eb52 HT |
614 | pfl, pfl->name, chip_len, &local_err); |
615 | if (local_err) { | |
616 | error_propagate(errp, local_err); | |
617 | return; | |
618 | } | |
619 | ||
368a354f | 620 | vmstate_register_ram(&pfl->orig_mem, DEVICE(pfl)); |
cfe5f011 | 621 | pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); |
4fbd24ba | 622 | pfl->chip_len = chip_len; |
4be74634 | 623 | if (pfl->blk) { |
29133e9a | 624 | /* read the initial flash content */ |
4be74634 | 625 | ret = blk_read(pfl->blk, 0, pfl->storage, chip_len >> 9); |
d0e7605e | 626 | if (ret < 0) { |
da3bd642 | 627 | vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl)); |
da3bd642 HT |
628 | error_setg(errp, "failed to read the initial flash content"); |
629 | return; | |
d0e7605e | 630 | } |
29133e9a | 631 | } |
de8efe8f | 632 | |
cfe5f011 AK |
633 | pflash_setup_mappings(pfl); |
634 | pfl->rom_mode = 1; | |
da3bd642 | 635 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); |
de8efe8f | 636 | |
4be74634 MA |
637 | if (pfl->blk) { |
638 | pfl->ro = blk_is_read_only(pfl->blk); | |
de8efe8f JJ |
639 | } else { |
640 | pfl->ro = 0; | |
641 | } | |
642 | ||
bc72ad67 | 643 | pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); |
29133e9a FB |
644 | pfl->wcycle = 0; |
645 | pfl->cmd = 0; | |
646 | pfl->status = 0; | |
29133e9a FB |
647 | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ |
648 | pfl->cfi_len = 0x52; | |
649 | /* Standard "QRY" string */ | |
650 | pfl->cfi_table[0x10] = 'Q'; | |
651 | pfl->cfi_table[0x11] = 'R'; | |
652 | pfl->cfi_table[0x12] = 'Y'; | |
653 | /* Command set (AMD/Fujitsu) */ | |
654 | pfl->cfi_table[0x13] = 0x02; | |
655 | pfl->cfi_table[0x14] = 0x00; | |
78556820 EI |
656 | /* Primary extended table address */ |
657 | pfl->cfi_table[0x15] = 0x31; | |
29133e9a FB |
658 | pfl->cfi_table[0x16] = 0x00; |
659 | /* Alternate command set (none) */ | |
660 | pfl->cfi_table[0x17] = 0x00; | |
661 | pfl->cfi_table[0x18] = 0x00; | |
662 | /* Alternate extended table (none) */ | |
663 | pfl->cfi_table[0x19] = 0x00; | |
664 | pfl->cfi_table[0x1A] = 0x00; | |
665 | /* Vcc min */ | |
666 | pfl->cfi_table[0x1B] = 0x27; | |
667 | /* Vcc max */ | |
668 | pfl->cfi_table[0x1C] = 0x36; | |
669 | /* Vpp min (no Vpp pin) */ | |
670 | pfl->cfi_table[0x1D] = 0x00; | |
671 | /* Vpp max (no Vpp pin) */ | |
672 | pfl->cfi_table[0x1E] = 0x00; | |
673 | /* Reserved */ | |
674 | pfl->cfi_table[0x1F] = 0x07; | |
78556820 EI |
675 | /* Timeout for min size buffer write (NA) */ |
676 | pfl->cfi_table[0x20] = 0x00; | |
29133e9a FB |
677 | /* Typical timeout for block erase (512 ms) */ |
678 | pfl->cfi_table[0x21] = 0x09; | |
679 | /* Typical timeout for full chip erase (4096 ms) */ | |
680 | pfl->cfi_table[0x22] = 0x0C; | |
681 | /* Reserved */ | |
682 | pfl->cfi_table[0x23] = 0x01; | |
78556820 EI |
683 | /* Max timeout for buffer write (NA) */ |
684 | pfl->cfi_table[0x24] = 0x00; | |
29133e9a FB |
685 | /* Max timeout for block erase */ |
686 | pfl->cfi_table[0x25] = 0x0A; | |
687 | /* Max timeout for chip erase */ | |
688 | pfl->cfi_table[0x26] = 0x0D; | |
689 | /* Device size */ | |
78556820 | 690 | pfl->cfi_table[0x27] = ctz32(chip_len); |
29133e9a FB |
691 | /* Flash device interface (8 & 16 bits) */ |
692 | pfl->cfi_table[0x28] = 0x02; | |
693 | pfl->cfi_table[0x29] = 0x00; | |
694 | /* Max number of bytes in multi-bytes write */ | |
95d1f3ed JM |
695 | /* XXX: disable buffered write as it's not supported */ |
696 | // pfl->cfi_table[0x2A] = 0x05; | |
697 | pfl->cfi_table[0x2A] = 0x00; | |
29133e9a FB |
698 | pfl->cfi_table[0x2B] = 0x00; |
699 | /* Number of erase block regions (uniform) */ | |
700 | pfl->cfi_table[0x2C] = 0x01; | |
701 | /* Erase block region 1 */ | |
368a354f PC |
702 | pfl->cfi_table[0x2D] = pfl->nb_blocs - 1; |
703 | pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8; | |
704 | pfl->cfi_table[0x2F] = pfl->sector_len >> 8; | |
705 | pfl->cfi_table[0x30] = pfl->sector_len >> 16; | |
29133e9a | 706 | |
78556820 EI |
707 | /* Extended */ |
708 | pfl->cfi_table[0x31] = 'P'; | |
709 | pfl->cfi_table[0x32] = 'R'; | |
710 | pfl->cfi_table[0x33] = 'I'; | |
711 | ||
712 | pfl->cfi_table[0x34] = '1'; | |
713 | pfl->cfi_table[0x35] = '0'; | |
714 | ||
715 | pfl->cfi_table[0x36] = 0x00; | |
716 | pfl->cfi_table[0x37] = 0x00; | |
717 | pfl->cfi_table[0x38] = 0x00; | |
718 | pfl->cfi_table[0x39] = 0x00; | |
719 | ||
720 | pfl->cfi_table[0x3a] = 0x00; | |
721 | ||
722 | pfl->cfi_table[0x3b] = 0x00; | |
723 | pfl->cfi_table[0x3c] = 0x00; | |
368a354f PC |
724 | } |
725 | ||
726 | static Property pflash_cfi02_properties[] = { | |
4be74634 | 727 | DEFINE_PROP_DRIVE("drive", struct pflash_t, blk), |
368a354f PC |
728 | DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), |
729 | DEFINE_PROP_UINT32("sector-length", struct pflash_t, sector_len, 0), | |
730 | DEFINE_PROP_UINT8("width", struct pflash_t, width, 0), | |
731 | DEFINE_PROP_UINT8("mappings", struct pflash_t, mappings, 0), | |
732 | DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0), | |
733 | DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), | |
734 | DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0), | |
735 | DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0), | |
736 | DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0), | |
737 | DEFINE_PROP_UINT16("unlock-addr0", struct pflash_t, unlock_addr0, 0), | |
738 | DEFINE_PROP_UINT16("unlock-addr1", struct pflash_t, unlock_addr1, 0), | |
739 | DEFINE_PROP_STRING("name", struct pflash_t, name), | |
740 | DEFINE_PROP_END_OF_LIST(), | |
741 | }; | |
742 | ||
743 | static void pflash_cfi02_class_init(ObjectClass *klass, void *data) | |
744 | { | |
745 | DeviceClass *dc = DEVICE_CLASS(klass); | |
368a354f | 746 | |
da3bd642 | 747 | dc->realize = pflash_cfi02_realize; |
368a354f | 748 | dc->props = pflash_cfi02_properties; |
df6f9318 | 749 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
368a354f PC |
750 | } |
751 | ||
752 | static const TypeInfo pflash_cfi02_info = { | |
3509c396 | 753 | .name = TYPE_CFI_PFLASH02, |
368a354f PC |
754 | .parent = TYPE_SYS_BUS_DEVICE, |
755 | .instance_size = sizeof(struct pflash_t), | |
756 | .class_init = pflash_cfi02_class_init, | |
757 | }; | |
758 | ||
759 | static void pflash_cfi02_register_types(void) | |
760 | { | |
761 | type_register_static(&pflash_cfi02_info); | |
762 | } | |
763 | ||
764 | type_init(pflash_cfi02_register_types) | |
765 | ||
766 | pflash_t *pflash_cfi02_register(hwaddr base, | |
767 | DeviceState *qdev, const char *name, | |
768 | hwaddr size, | |
4be74634 | 769 | BlockBackend *blk, uint32_t sector_len, |
368a354f PC |
770 | int nb_blocs, int nb_mappings, int width, |
771 | uint16_t id0, uint16_t id1, | |
772 | uint16_t id2, uint16_t id3, | |
773 | uint16_t unlock_addr0, uint16_t unlock_addr1, | |
774 | int be) | |
775 | { | |
3509c396 | 776 | DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH02); |
368a354f | 777 | |
9b3d111a MA |
778 | if (blk) { |
779 | qdev_prop_set_drive(dev, "drive", blk, &error_abort); | |
368a354f PC |
780 | } |
781 | qdev_prop_set_uint32(dev, "num-blocks", nb_blocs); | |
782 | qdev_prop_set_uint32(dev, "sector-length", sector_len); | |
783 | qdev_prop_set_uint8(dev, "width", width); | |
784 | qdev_prop_set_uint8(dev, "mappings", nb_mappings); | |
785 | qdev_prop_set_uint8(dev, "big-endian", !!be); | |
786 | qdev_prop_set_uint16(dev, "id0", id0); | |
787 | qdev_prop_set_uint16(dev, "id1", id1); | |
788 | qdev_prop_set_uint16(dev, "id2", id2); | |
789 | qdev_prop_set_uint16(dev, "id3", id3); | |
790 | qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); | |
791 | qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); | |
792 | qdev_prop_set_string(dev, "name", name); | |
793 | qdev_init_nofail(dev); | |
794 | ||
3509c396 HT |
795 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
796 | return CFI_PFLASH02(dev); | |
29133e9a | 797 | } |