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Commit | Line | Data |
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f7c70325 PB |
1 | /* |
2 | * ARM11MPCore internal peripheral emulation. | |
3 | * | |
4 | * Copyright (c) 2006-2007 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
f7c70325 PB |
8 | */ |
9 | ||
17b7f2db | 10 | #include "qemu/osdep.h" |
da34e65c | 11 | #include "qapi/error.h" |
0b8fa32f | 12 | #include "qemu/module.h" |
7b960dc3 | 13 | #include "hw/cpu/arm11mpcore.h" |
306476ea | 14 | #include "hw/intc/realview_gic.h" |
64552b6b | 15 | #include "hw/irq.h" |
a27bd6c7 | 16 | #include "hw/qdev-properties.h" |
2a6ab1e3 | 17 | |
25f1d9f3 | 18 | #define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4 |
2a6ab1e3 | 19 | |
2e9dfe20 | 20 | static void mpcore_priv_set_irq(void *opaque, int irq, int level) |
2a6ab1e3 | 21 | { |
845769fc | 22 | ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
08602ac5 AF |
23 | |
24 | qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); | |
2a6ab1e3 PM |
25 | } |
26 | ||
845769fc | 27 | static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) |
2a6ab1e3 PM |
28 | { |
29 | int i; | |
53cb9a1c | 30 | SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu); |
08602ac5 AF |
31 | DeviceState *gicdev = DEVICE(&s->gic); |
32 | SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic); | |
33 | SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer); | |
34 | SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer); | |
53cb9a1c AF |
35 | |
36 | memory_region_add_subregion(&s->container, 0, | |
37 | sysbus_mmio_get_region(scubusdev, 0)); | |
2a6ab1e3 PM |
38 | /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs |
39 | * at 0x200, 0x300... | |
40 | */ | |
41 | for (i = 0; i < (s->num_cpu + 1); i++) { | |
a8170e5e | 42 | hwaddr offset = 0x100 + (i * 0x100); |
2e9dfe20 PM |
43 | memory_region_add_subregion(&s->container, offset, |
44 | sysbus_mmio_get_region(gicbusdev, i + 1)); | |
2a6ab1e3 PM |
45 | } |
46 | /* Add the regions for timer and watchdog for "current CPU" and | |
47 | * for each specific CPU. | |
48 | */ | |
cde4577f | 49 | for (i = 0; i < (s->num_cpu + 1); i++) { |
2a6ab1e3 | 50 | /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ |
cde4577f | 51 | hwaddr offset = 0x600 + i * 0x100; |
2a6ab1e3 | 52 | memory_region_add_subregion(&s->container, offset, |
cde4577f PC |
53 | sysbus_mmio_get_region(timerbusdev, i)); |
54 | memory_region_add_subregion(&s->container, offset + 0x20, | |
55 | sysbus_mmio_get_region(wdtbusdev, i)); | |
2a6ab1e3 | 56 | } |
2e9dfe20 PM |
57 | memory_region_add_subregion(&s->container, 0x1000, |
58 | sysbus_mmio_get_region(gicbusdev, 0)); | |
59 | /* Wire up the interrupt from each watchdog and timer. | |
60 | * For each core the timer is PPI 29 and the watchdog PPI 30. | |
61 | */ | |
62 | for (i = 0; i < s->num_cpu; i++) { | |
63 | int ppibase = (s->num_irq - 32) + i * 32; | |
cde4577f | 64 | sysbus_connect_irq(timerbusdev, i, |
08602ac5 | 65 | qdev_get_gpio_in(gicdev, ppibase + 29)); |
cde4577f | 66 | sysbus_connect_irq(wdtbusdev, i, |
08602ac5 | 67 | qdev_get_gpio_in(gicdev, ppibase + 30)); |
2a6ab1e3 PM |
68 | } |
69 | } | |
70 | ||
08602ac5 | 71 | static void mpcore_priv_realize(DeviceState *dev, Error **errp) |
2a6ab1e3 | 72 | { |
08602ac5 | 73 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
56fc0281 | 74 | ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev); |
53cb9a1c | 75 | DeviceState *scudev = DEVICE(&s->scu); |
08602ac5 AF |
76 | DeviceState *gicdev = DEVICE(&s->gic); |
77 | DeviceState *mptimerdev = DEVICE(&s->mptimer); | |
78 | DeviceState *wdtimerdev = DEVICE(&s->wdtimer); | |
79 | Error *err = NULL; | |
53cb9a1c AF |
80 | |
81 | qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); | |
118bfd76 | 82 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err)) { |
08602ac5 AF |
83 | error_propagate(errp, err); |
84 | return; | |
85 | } | |
2e9dfe20 | 86 | |
08602ac5 AF |
87 | qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); |
88 | qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); | |
25f1d9f3 SPB |
89 | qdev_prop_set_uint32(gicdev, "num-priority-bits", |
90 | ARM11MPCORE_NUM_GIC_PRIORITY_BITS); | |
91 | ||
92 | ||
118bfd76 | 93 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err)) { |
08602ac5 AF |
94 | error_propagate(errp, err); |
95 | return; | |
96 | } | |
2e9dfe20 PM |
97 | |
98 | /* Pass through outbound IRQ lines from the GIC */ | |
08602ac5 | 99 | sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic)); |
2e9dfe20 PM |
100 | |
101 | /* Pass through inbound GPIO lines to the GIC */ | |
56fc0281 | 102 | qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); |
2a6ab1e3 | 103 | |
08602ac5 | 104 | qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); |
118bfd76 | 105 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), &err)) { |
08602ac5 AF |
106 | error_propagate(errp, err); |
107 | return; | |
108 | } | |
cde4577f | 109 | |
08602ac5 | 110 | qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu); |
118bfd76 | 111 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdtimer), &err)) { |
08602ac5 AF |
112 | error_propagate(errp, err); |
113 | return; | |
114 | } | |
cde4577f | 115 | |
2a6ab1e3 | 116 | mpcore_priv_map_setup(s); |
2a6ab1e3 | 117 | } |
f7c70325 | 118 | |
2c42c3a0 AF |
119 | static void mpcore_priv_initfn(Object *obj) |
120 | { | |
121 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
122 | ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); | |
123 | ||
124 | memory_region_init(&s->container, OBJECT(s), | |
125 | "mpcore-priv-container", 0x2000); | |
126 | sysbus_init_mmio(sbd, &s->container); | |
53cb9a1c | 127 | |
db873cc5 | 128 | object_initialize_child(obj, "scu", &s->scu, TYPE_ARM11_SCU); |
08602ac5 | 129 | |
db873cc5 | 130 | object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); |
08602ac5 AF |
131 | /* Request the legacy 11MPCore GIC behaviour: */ |
132 | qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); | |
133 | ||
db873cc5 | 134 | object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); |
08602ac5 | 135 | |
db873cc5 | 136 | object_initialize_child(obj, "wdtimer", &s->wdtimer, TYPE_ARM_MPTIMER); |
2c42c3a0 AF |
137 | } |
138 | ||
999e12bb | 139 | static Property mpcore_priv_properties[] = { |
845769fc | 140 | DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), |
0f58a188 PM |
141 | /* The ARM11 MPCORE TRM says the on-chip controller may have |
142 | * anything from 0 to 224 external interrupt IRQ lines (with another | |
143 | * 32 internal). We default to 32+32, which is the number provided by | |
144 | * the ARM11 MPCore test chip in the Realview Versatile Express | |
145 | * coretile. Other boards may differ and should set this property | |
146 | * appropriately. Some Linux kernels may not boot if the hardware | |
147 | * has more IRQ lines than the kernel expects. | |
148 | */ | |
845769fc | 149 | DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), |
999e12bb AL |
150 | DEFINE_PROP_END_OF_LIST(), |
151 | }; | |
152 | ||
153 | static void mpcore_priv_class_init(ObjectClass *klass, void *data) | |
154 | { | |
39bffca2 | 155 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 156 | |
08602ac5 | 157 | dc->realize = mpcore_priv_realize; |
4f67d30b | 158 | device_class_set_props(dc, mpcore_priv_properties); |
999e12bb AL |
159 | } |
160 | ||
8c43a6f0 | 161 | static const TypeInfo mpcore_priv_info = { |
56fc0281 | 162 | .name = TYPE_ARM11MPCORE_PRIV, |
39bffca2 | 163 | .parent = TYPE_SYS_BUS_DEVICE, |
845769fc | 164 | .instance_size = sizeof(ARM11MPCorePriveState), |
2c42c3a0 | 165 | .instance_init = mpcore_priv_initfn, |
39bffca2 | 166 | .class_init = mpcore_priv_class_init, |
f7c70325 PB |
167 | }; |
168 | ||
83f7d43a | 169 | static void arm11mpcore_register_types(void) |
f7c70325 | 170 | { |
39bffca2 | 171 | type_register_static(&mpcore_priv_info); |
f7c70325 PB |
172 | } |
173 | ||
83f7d43a | 174 | type_init(arm11mpcore_register_types) |