[mirror_qemu.git] / hw / display / ati_2d.c

/*
 * QEMU ATI SVGA emulation
 * 2D engine functions
 *
 * Copyright (c) 2019 BALATON Zoltan
 *
 * This work is licensed under the GNU GPL license version 2 or later.
 */

#include "qemu/osdep.h"
#include "ati_int.h"
#include "ati_regs.h"
#include "qemu/log.h"
#include "ui/pixel_ops.h"

/*
 * NOTE:
 * This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to
 * reinvent the wheel (unlikely to get better with a naive implementation than
 * existing libraries) and avoid (poorly) reimplementing gfx primitives.
 * That is unnecessary and would become a performance problem. Instead, try to
 * map to and reuse existing optimised facilities (e.g. pixman) wherever
 * possible.
 */

static int ati_bpp_from_datatype(ATIVGAState *s)
{
    switch (s->regs.dp_datatype & 0xf) {
    case 2:
        return 8;
    case 3:
    case 4:
        return 16;
    case 5:
        return 24;
    case 6:
        return 32;
    default:
        qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n",
                      s->regs.dp_datatype & 0xf);
        return 0;
    }
}

#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)

void ati_2d_blt(ATIVGAState *s)
{
    /* FIXME it is probably more complex than this and may need to be */
    /* rewritten but for now as a start just to get some output: */
    DisplaySurface *ds = qemu_console_surface(s->vga.con);
    DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr,
            s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),
            surface_bits_per_pixel(ds),
            (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
    int bpp = ati_bpp_from_datatype(s);
    int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;
    uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
                        s->regs.dst_offset : s->regs.default_offset);

    if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
        dst_bits += s->regs.crtc_offset & 0x07ffffff;
        dst_stride *= bpp;
    }
    uint8_t *end = s->vga.vram_ptr + s->vga.vram_size;
    if (dst_bits >= end ||
        dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height) *
        dst_stride >= end) {
        qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
        return;
    }
    DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d\n",
            s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset,
            s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch,
            s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
            s->regs.dst_width, s->regs.dst_height);
    switch (s->regs.dp_mix & GMC_ROP3_MASK) {
    case ROP3_SRCCOPY:
    {
        int src_stride = DEFAULT_CNTL ?
                         s->regs.src_pitch : s->regs.default_pitch;
        uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
                            s->regs.src_offset : s->regs.default_offset);

        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
            src_bits += s->regs.crtc_offset & 0x07ffffff;
            src_stride *= bpp;
        }
        if (src_bits >= end ||
            src_bits + s->regs.src_x + (s->regs.src_y + s->regs.dst_height) *
            src_stride >= end) {
            qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
            return;
        }

        src_stride /= sizeof(uint32_t);
        dst_stride /= sizeof(uint32_t);
        DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n",
                src_bits, dst_bits, src_stride, dst_stride, bpp, bpp,
                s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
                s->regs.dst_width, s->regs.dst_height);
        pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits,
                   src_stride, dst_stride, bpp, bpp,
                   s->regs.src_x, s->regs.src_y,
                   s->regs.dst_x, s->regs.dst_y,
                   s->regs.dst_width, s->regs.dst_height);
        if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
            dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
            s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
            memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
                                    s->regs.dst_offset +
                                    s->regs.dst_y * surface_stride(ds),
                                    s->regs.dst_height * surface_stride(ds));
        }
        s->regs.dst_x += s->regs.dst_width;
        s->regs.dst_y += s->regs.dst_height;
        break;
    }
    case ROP3_PATCOPY:
    case ROP3_BLACKNESS:
    case ROP3_WHITENESS:
    {
        uint32_t filler = 0;

        switch (s->regs.dp_mix & GMC_ROP3_MASK) {
        case ROP3_PATCOPY:
            filler = bswap32(s->regs.dp_brush_frgd_clr);
            break;
        case ROP3_BLACKNESS:
            filler = rgb_to_pixel32(s->vga.palette[0], s->vga.palette[1],
                                    s->vga.palette[2]) << 8 | 0xff;
            break;
        case ROP3_WHITENESS:
            filler = rgb_to_pixel32(s->vga.palette[3], s->vga.palette[4],
                                    s->vga.palette[5]) << 8 | 0xff;
            break;
        }

        dst_stride /= sizeof(uint32_t);
        DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n",
                dst_bits, dst_stride, bpp,
                s->regs.dst_x, s->regs.dst_y,
                s->regs.dst_width, s->regs.dst_height,
                filler);
        pixman_fill((uint32_t *)dst_bits, dst_stride, bpp,
                    s->regs.dst_x, s->regs.dst_y,
                    s->regs.dst_width, s->regs.dst_height,
                    filler);
        if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
            dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
            s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
            memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
                                    s->regs.dst_offset +
                                    s->regs.dst_y * surface_stride(ds),
                                    s->regs.dst_height * surface_stride(ds));
        }
        s->regs.dst_y += s->regs.dst_height;
        break;
    }
    default:
        qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n",
                      (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
    }
}
Commit	Line	Data
862b4a29 BZ	1	/*
	2	* QEMU ATI SVGA emulation
	3	* 2D engine functions
	4	*
	5	* Copyright (c) 2019 BALATON Zoltan
	6	*
	7	* This work is licensed under the GNU GPL license version 2 or later.
	8	*/
	9
bbfff196	10	#include "qemu/osdep.h"
862b4a29 BZ	11	#include "ati_int.h"
	12	#include "ati_regs.h"
	13	#include "qemu/log.h"
	14	#include "ui/pixel_ops.h"
	15
	16	/*
	17	* NOTE:
	18	* This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to
	19	* reinvent the wheel (unlikely to get better with a naive implementation than
	20	* existing libraries) and avoid (poorly) reimplementing gfx primitives.
	21	* That is unnecessary and would become a performance problem. Instead, try to
	22	* map to and reuse existing optimised facilities (e.g. pixman) wherever
	23	* possible.
	24	*/
	25
	26	static int ati_bpp_from_datatype(ATIVGAState *s)
	27	{
	28	switch (s->regs.dp_datatype & 0xf) {
	29	case 2:
	30	return 8;
	31	case 3:
	32	case 4:
	33	return 16;
	34	case 5:
	35	return 24;
	36	case 6:
	37	return 32;
	38	default:
	39	qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n",
	40	s->regs.dp_datatype & 0xf);
	41	return 0;
	42	}
	43	}
	44
c799d2ee BZ	45	#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)
c799d2ee BZ	46
862b4a29 BZ	47	void ati_2d_blt(ATIVGAState *s)
	48	{
	49	/* FIXME it is probably more complex than this and may need to be */
	50	/* rewritten but for now as a start just to get some output: */
	51	DisplaySurface *ds = qemu_console_surface(s->vga.con);
	52	DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr,
	53	s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),
	54	surface_bits_per_pixel(ds),
	55	(s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
c799d2ee BZ	56	int bpp = ati_bpp_from_datatype(s);
	57	int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;
	58	uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
	59	s->regs.dst_offset : s->regs.default_offset);
	60
	61	if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
	62	dst_bits += s->regs.crtc_offset & 0x07ffffff;
	63	dst_stride *= bpp;
	64	}
	65	uint8_t *end = s->vga.vram_ptr + s->vga.vram_size;
	66	if (dst_bits >= end \|\|
	67	dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height) *
	68	dst_stride >= end) {
	69	qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
	70	return;
	71	}
866ad5f5 BZ	72	DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d\n",
	73	s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset,
	74	s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch,
862b4a29 BZ	75	s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
	76	s->regs.dst_width, s->regs.dst_height);
	77	switch (s->regs.dp_mix & GMC_ROP3_MASK) {
	78	case ROP3_SRCCOPY:
	79	{
c799d2ee BZ	80	int src_stride = DEFAULT_CNTL ?
	81	s->regs.src_pitch : s->regs.default_pitch;
	82	uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
	83	s->regs.src_offset : s->regs.default_offset);
862b4a29 BZ	84
	85	if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
	86	src_bits += s->regs.crtc_offset & 0x07ffffff;
862b4a29	87	src_stride *= bpp;
862b4a29	88	}
c799d2ee BZ	89	if (src_bits >= end \|\|
	90	src_bits + s->regs.src_x + (s->regs.src_y + s->regs.dst_height) *
	91	src_stride >= end) {
	92	qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
	93	return;
	94	}
	95
862b4a29 BZ	96	src_stride /= sizeof(uint32_t);
862b4a29 BZ	97	dst_stride /= sizeof(uint32_t);
862b4a29 BZ	98	DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n",
	99	src_bits, dst_bits, src_stride, dst_stride, bpp, bpp,
	100	s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
	101	s->regs.dst_width, s->regs.dst_height);
862b4a29 BZ	102	pixman_blt((uint32_t )src_bits, (uint32_t )dst_bits,
	103	src_stride, dst_stride, bpp, bpp,
	104	s->regs.src_x, s->regs.src_y,
	105	s->regs.dst_x, s->regs.dst_y,
	106	s->regs.dst_width, s->regs.dst_height);
	107	if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
	108	dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
	109	s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
	110	memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
	111	s->regs.dst_offset +
	112	s->regs.dst_y * surface_stride(ds),
	113	s->regs.dst_height * surface_stride(ds));
	114	}
	115	s->regs.dst_x += s->regs.dst_width;
	116	s->regs.dst_y += s->regs.dst_height;
	117	break;
	118	}
	119	case ROP3_PATCOPY:
	120	case ROP3_BLACKNESS:
	121	case ROP3_WHITENESS:
	122	{
862b4a29	123	uint32_t filler = 0;
862b4a29 BZ	124
	125	switch (s->regs.dp_mix & GMC_ROP3_MASK) {
	126	case ROP3_PATCOPY:
	127	filler = bswap32(s->regs.dp_brush_frgd_clr);
	128	break;
	129	case ROP3_BLACKNESS:
	130	filler = rgb_to_pixel32(s->vga.palette[0], s->vga.palette[1],
	131	s->vga.palette[2]) << 8 \| 0xff;
	132	break;
	133	case ROP3_WHITENESS:
	134	filler = rgb_to_pixel32(s->vga.palette[3], s->vga.palette[4],
	135	s->vga.palette[5]) << 8 \| 0xff;
	136	break;
	137	}
	138
c799d2ee	139	dst_stride /= sizeof(uint32_t);
862b4a29 BZ	140	DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n",
	141	dst_bits, dst_stride, bpp,
	142	s->regs.dst_x, s->regs.dst_y,
	143	s->regs.dst_width, s->regs.dst_height,
	144	filler);
862b4a29	145	pixman_fill((uint32_t *)dst_bits, dst_stride, bpp,
c799d2ee BZ	146	s->regs.dst_x, s->regs.dst_y,
	147	s->regs.dst_width, s->regs.dst_height,
	148	filler);
862b4a29 BZ	149	if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
	150	dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
	151	s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
	152	memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
	153	s->regs.dst_offset +
	154	s->regs.dst_y * surface_stride(ds),
	155	s->regs.dst_height * surface_stride(ds));
	156	}
	157	s->regs.dst_y += s->regs.dst_height;
	158	break;
	159	}
	160	default:
	161	qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n",
	162	(s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
	163	}
	164	}