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CommitLineData
bbfff196 1#include "qemu/osdep.h"
862b4a29
BZ
2#include "ati_int.h"
3
4#ifdef DEBUG_ATI
5struct ati_regdesc {
6 const char *name;
7 int num;
8};
9
10static struct ati_regdesc ati_reg_names[] = {
11 {"MM_INDEX", 0x0000},
12 {"MM_DATA", 0x0004},
13 {"CLOCK_CNTL_INDEX", 0x0008},
14 {"CLOCK_CNTL_DATA", 0x000c},
15 {"BIOS_0_SCRATCH", 0x0010},
16 {"BUS_CNTL", 0x0030},
17 {"BUS_CNTL1", 0x0034},
18 {"GEN_INT_CNTL", 0x0040},
19 {"CRTC_GEN_CNTL", 0x0050},
20 {"CRTC_EXT_CNTL", 0x0054},
21 {"DAC_CNTL", 0x0058},
c82c7336
BZ
22 {"GPIO_VGA_DDC", 0x0060},
23 {"GPIO_DVI_DDC", 0x0064},
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24 {"GPIO_MONID", 0x0068},
25 {"I2C_CNTL_1", 0x0094},
26 {"PALETTE_INDEX", 0x00b0},
27 {"PALETTE_DATA", 0x00b4},
28 {"CNFG_CNTL", 0x00e0},
29 {"GEN_RESET_CNTL", 0x00f0},
30 {"CNFG_MEMSIZE", 0x00f8},
31 {"MEM_CNTL", 0x0140},
32 {"MC_FB_LOCATION", 0x0148},
33 {"MC_AGP_LOCATION", 0x014C},
34 {"MC_STATUS", 0x0150},
35 {"MEM_POWER_MISC", 0x015c},
36 {"AGP_BASE", 0x0170},
37 {"AGP_CNTL", 0x0174},
38 {"AGP_APER_OFFSET", 0x0178},
39 {"PCI_GART_PAGE", 0x017c},
40 {"PC_NGUI_MODE", 0x0180},
41 {"PC_NGUI_CTLSTAT", 0x0184},
42 {"MPP_TB_CONFIG", 0x01C0},
43 {"MPP_GP_CONFIG", 0x01C8},
44 {"VIPH_CONTROL", 0x01D0},
45 {"CRTC_H_TOTAL_DISP", 0x0200},
46 {"CRTC_H_SYNC_STRT_WID", 0x0204},
47 {"CRTC_V_TOTAL_DISP", 0x0208},
48 {"CRTC_V_SYNC_STRT_WID", 0x020c},
49 {"CRTC_VLINE_CRNT_VLINE", 0x0210},
50 {"CRTC_CRNT_FRAME", 0x0214},
51 {"CRTC_GUI_TRIG_VLINE", 0x0218},
52 {"CRTC_OFFSET", 0x0224},
53 {"CRTC_OFFSET_CNTL", 0x0228},
54 {"CRTC_PITCH", 0x022c},
55 {"OVR_CLR", 0x0230},
56 {"OVR_WID_LEFT_RIGHT", 0x0234},
57 {"OVR_WID_TOP_BOTTOM", 0x0238},
58 {"CUR_OFFSET", 0x0260},
59 {"CUR_HORZ_VERT_POSN", 0x0264},
60 {"CUR_HORZ_VERT_OFF", 0x0268},
61 {"CUR_CLR0", 0x026c},
62 {"CUR_CLR1", 0x0270},
63 {"LVDS_GEN_CNTL", 0x02d0},
64 {"DDA_CONFIG", 0x02e0},
65 {"DDA_ON_OFF", 0x02e4},
66 {"VGA_DDA_CONFIG", 0x02e8},
67 {"VGA_DDA_ON_OFF", 0x02ec},
68 {"CRTC2_H_TOTAL_DISP", 0x0300},
69 {"CRTC2_H_SYNC_STRT_WID", 0x0304},
70 {"CRTC2_V_TOTAL_DISP", 0x0308},
71 {"CRTC2_V_SYNC_STRT_WID", 0x030c},
72 {"CRTC2_VLINE_CRNT_VLINE", 0x0310},
73 {"CRTC2_CRNT_FRAME", 0x0314},
74 {"CRTC2_GUI_TRIG_VLINE", 0x0318},
75 {"CRTC2_OFFSET", 0x0324},
76 {"CRTC2_OFFSET_CNTL", 0x0328},
77 {"CRTC2_PITCH", 0x032c},
78 {"DDA2_CONFIG", 0x03e0},
79 {"DDA2_ON_OFF", 0x03e4},
80 {"CRTC2_GEN_CNTL", 0x03f8},
81 {"CRTC2_STATUS", 0x03fc},
82 {"OV0_SCALE_CNTL", 0x0420},
83 {"SUBPIC_CNTL", 0x0540},
84 {"PM4_BUFFER_OFFSET", 0x0700},
85 {"PM4_BUFFER_CNTL", 0x0704},
86 {"PM4_BUFFER_WM_CNTL", 0x0708},
87 {"PM4_BUFFER_DL_RPTR_ADDR", 0x070c},
88 {"PM4_BUFFER_DL_RPTR", 0x0710},
89 {"PM4_BUFFER_DL_WPTR", 0x0714},
90 {"PM4_VC_FPU_SETUP", 0x071c},
91 {"PM4_FPU_CNTL", 0x0720},
92 {"PM4_VC_FORMAT", 0x0724},
93 {"PM4_VC_CNTL", 0x0728},
94 {"PM4_VC_I01", 0x072c},
95 {"PM4_VC_VLOFF", 0x0730},
96 {"PM4_VC_VLSIZE", 0x0734},
97 {"PM4_IW_INDOFF", 0x0738},
98 {"PM4_IW_INDSIZE", 0x073c},
99 {"PM4_FPU_FPX0", 0x0740},
100 {"PM4_FPU_FPY0", 0x0744},
101 {"PM4_FPU_FPX1", 0x0748},
102 {"PM4_FPU_FPY1", 0x074c},
103 {"PM4_FPU_FPX2", 0x0750},
104 {"PM4_FPU_FPY2", 0x0754},
105 {"PM4_FPU_FPY3", 0x0758},
106 {"PM4_FPU_FPY4", 0x075c},
107 {"PM4_FPU_FPY5", 0x0760},
108 {"PM4_FPU_FPY6", 0x0764},
109 {"PM4_FPU_FPR", 0x0768},
110 {"PM4_FPU_FPG", 0x076c},
111 {"PM4_FPU_FPB", 0x0770},
112 {"PM4_FPU_FPA", 0x0774},
113 {"PM4_FPU_INTXY0", 0x0780},
114 {"PM4_FPU_INTXY1", 0x0784},
115 {"PM4_FPU_INTXY2", 0x0788},
116 {"PM4_FPU_INTARGB", 0x078c},
117 {"PM4_FPU_FPTWICEAREA", 0x0790},
118 {"PM4_FPU_DMAJOR01", 0x0794},
119 {"PM4_FPU_DMAJOR12", 0x0798},
120 {"PM4_FPU_DMAJOR02", 0x079c},
121 {"PM4_FPU_STAT", 0x07a0},
122 {"PM4_STAT", 0x07b8},
123 {"PM4_TEST_CNTL", 0x07d0},
124 {"PM4_MICROCODE_ADDR", 0x07d4},
125 {"PM4_MICROCODE_RADDR", 0x07d8},
126 {"PM4_MICROCODE_DATAH", 0x07dc},
127 {"PM4_MICROCODE_DATAL", 0x07e0},
128 {"PM4_CMDFIFO_ADDR", 0x07e4},
129 {"PM4_CMDFIFO_DATAH", 0x07e8},
130 {"PM4_CMDFIFO_DATAL", 0x07ec},
131 {"PM4_BUFFER_ADDR", 0x07f0},
132 {"PM4_BUFFER_DATAH", 0x07f4},
133 {"PM4_BUFFER_DATAL", 0x07f8},
134 {"PM4_MICRO_CNTL", 0x07fc},
135 {"CAP0_TRIG_CNTL", 0x0950},
136 {"CAP1_TRIG_CNTL", 0x09c0},
137 {"RBBM_STATUS", 0x0e40},
138 {"PM4_FIFO_DATA_EVEN", 0x1000},
139 {"PM4_FIFO_DATA_ODD", 0x1004},
140 {"DST_OFFSET", 0x1404},
141 {"DST_PITCH", 0x1408},
142 {"DST_WIDTH", 0x140c},
143 {"DST_HEIGHT", 0x1410},
144 {"SRC_X", 0x1414},
145 {"SRC_Y", 0x1418},
146 {"DST_X", 0x141c},
147 {"DST_Y", 0x1420},
148 {"SRC_PITCH_OFFSET", 0x1428},
149 {"DST_PITCH_OFFSET", 0x142c},
150 {"SRC_Y_X", 0x1434},
151 {"DST_Y_X", 0x1438},
152 {"DST_HEIGHT_WIDTH", 0x143c},
153 {"DP_GUI_MASTER_CNTL", 0x146c},
154 {"BRUSH_SCALE", 0x1470},
155 {"BRUSH_Y_X", 0x1474},
156 {"DP_BRUSH_BKGD_CLR", 0x1478},
157 {"DP_BRUSH_FRGD_CLR", 0x147c},
158 {"DST_WIDTH_X", 0x1588},
159 {"DST_HEIGHT_WIDTH_8", 0x158c},
160 {"SRC_X_Y", 0x1590},
161 {"DST_X_Y", 0x1594},
162 {"DST_WIDTH_HEIGHT", 0x1598},
163 {"DST_WIDTH_X_INCY", 0x159c},
164 {"DST_HEIGHT_Y", 0x15a0},
165 {"DST_X_SUB", 0x15a4},
166 {"DST_Y_SUB", 0x15a8},
167 {"SRC_OFFSET", 0x15ac},
168 {"SRC_PITCH", 0x15b0},
169 {"DST_HEIGHT_WIDTH_BW", 0x15b4},
170 {"CLR_CMP_CNTL", 0x15c0},
171 {"CLR_CMP_CLR_SRC", 0x15c4},
172 {"CLR_CMP_CLR_DST", 0x15c8},
173 {"CLR_CMP_MASK", 0x15cc},
174 {"DP_SRC_FRGD_CLR", 0x15d8},
175 {"DP_SRC_BKGD_CLR", 0x15dc},
176 {"DST_BRES_ERR", 0x1628},
177 {"DST_BRES_INC", 0x162c},
178 {"DST_BRES_DEC", 0x1630},
179 {"DST_BRES_LNTH", 0x1634},
180 {"DST_BRES_LNTH_SUB", 0x1638},
181 {"SC_LEFT", 0x1640},
182 {"SC_RIGHT", 0x1644},
183 {"SC_TOP", 0x1648},
184 {"SC_BOTTOM", 0x164c},
185 {"SRC_SC_RIGHT", 0x1654},
186 {"SRC_SC_BOTTOM", 0x165c},
187 {"GUI_DEBUG0", 0x16a0},
188 {"GUI_DEBUG1", 0x16a4},
189 {"GUI_TIMEOUT", 0x16b0},
190 {"GUI_TIMEOUT0", 0x16b4},
191 {"GUI_TIMEOUT1", 0x16b8},
192 {"GUI_PROBE", 0x16bc},
193 {"DP_CNTL", 0x16c0},
194 {"DP_DATATYPE", 0x16c4},
195 {"DP_MIX", 0x16c8},
196 {"DP_WRITE_MASK", 0x16cc},
197 {"DP_CNTL_XDIR_YDIR_YMAJOR", 0x16d0},
198 {"DEFAULT_OFFSET", 0x16e0},
199 {"DEFAULT_PITCH", 0x16e4},
200 {"DEFAULT_SC_BOTTOM_RIGHT", 0x16e8},
201 {"SC_TOP_LEFT", 0x16ec},
202 {"SC_BOTTOM_RIGHT", 0x16f0},
203 {"SRC_SC_BOTTOM_RIGHT", 0x16f4},
204 {"DST_TILE", 0x1700},
205 {"WAIT_UNTIL", 0x1720},
206 {"CACHE_CNTL", 0x1724},
207 {"GUI_STAT", 0x1740},
208 {"PC_GUI_MODE", 0x1744},
209 {"PC_GUI_CTLSTAT", 0x1748},
210 {"PC_DEBUG_MODE", 0x1760},
211 {"BRES_DST_ERR_DEC", 0x1780},
212 {"TRAIL_BRES_T12_ERR_DEC", 0x1784},
213 {"TRAIL_BRES_T12_INC", 0x1788},
214 {"DP_T12_CNTL", 0x178c},
215 {"DST_BRES_T1_LNTH", 0x1790},
216 {"DST_BRES_T2_LNTH", 0x1794},
217 {"SCALE_SRC_HEIGHT_WIDTH", 0x1994},
218 {"SCALE_OFFSET_0", 0x1998},
219 {"SCALE_PITCH", 0x199c},
220 {"SCALE_X_INC", 0x19a0},
221 {"SCALE_Y_INC", 0x19a4},
222 {"SCALE_HACC", 0x19a8},
223 {"SCALE_VACC", 0x19ac},
224 {"SCALE_DST_X_Y", 0x19b0},
225 {"SCALE_DST_HEIGHT_WIDTH", 0x19b4},
226 {"SCALE_3D_CNTL", 0x1a00},
227 {"SCALE_3D_DATATYPE", 0x1a20},
228 {"SETUP_CNTL", 0x1bc4},
229 {"SOLID_COLOR", 0x1bc8},
230 {"WINDOW_XY_OFFSET", 0x1bcc},
231 {"DRAW_LINE_POINT", 0x1bd0},
232 {"SETUP_CNTL_PM4", 0x1bd4},
233 {"DST_PITCH_OFFSET_C", 0x1c80},
234 {"DP_GUI_MASTER_CNTL_C", 0x1c84},
235 {"SC_TOP_LEFT_C", 0x1c88},
236 {"SC_BOTTOM_RIGHT_C", 0x1c8c},
237 {"CLR_CMP_MASK_3D", 0x1A28},
238 {"MISC_3D_STATE_CNTL_REG", 0x1CA0},
239 {"MC_SRC1_CNTL", 0x19D8},
240 {"TEX_CNTL", 0x1800},
241 {"RAGE128_MPP_TB_CONFIG", 0x01c0},
242 {NULL, -1}
243};
244
245const char *ati_reg_name(int num)
246{
247 int i;
248
249 num &= ~3;
250 for (i = 0; ati_reg_names[i].name; i++) {
251 if (ati_reg_names[i].num == num) {
252 return ati_reg_names[i].name;
253 }
254 }
255 return "unknown";
256}
257#else
258const char *ati_reg_name(int num)
259{
260 return "";
261}
262#endif