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Commit | Line | Data |
---|---|---|
87e0331c | 1 | # See docs/devel/tracing.txt for syntax documentation. |
14750ef1 | 2 | |
500016e5 | 3 | # jazz_led.c |
14750ef1 DB |
4 | jazz_led_read(uint64_t addr, uint8_t val) "read addr=0x%"PRIx64": 0x%x" |
5 | jazz_led_write(uint64_t addr, uint8_t new) "write addr=0x%"PRIx64": 0x%x" | |
6 | ||
500016e5 | 7 | # xenfb.c |
db73ee4b | 8 | xenfb_mouse_event(void *opaque, int dx, int dy, int dz, int button_state, int abs_pointer_wanted) "%p x %d y %d z %d bs 0x%x abs %d" |
6ec83bef | 9 | xenfb_key_event(void *opaque, int scancode, int button_state) "%p scancode %d bs 0x%x" |
14750ef1 DB |
10 | xenfb_input_connected(void *xendev, int abs_pointer_wanted) "%p abs %d" |
11 | ||
500016e5 | 12 | # g364fb.c |
14750ef1 DB |
13 | g364fb_read(uint64_t addr, uint32_t val) "read addr=0x%"PRIx64": 0x%x" |
14 | g364fb_write(uint64_t addr, uint32_t new) "write addr=0x%"PRIx64": 0x%x" | |
15 | ||
500016e5 | 16 | # vmware_vga.c |
14750ef1 DB |
17 | vmware_value_read(uint32_t index, uint32_t value) "index %d, value 0x%x" |
18 | vmware_value_write(uint32_t index, uint32_t value) "index %d, value 0x%x" | |
19 | vmware_palette_read(uint32_t index, uint32_t value) "index %d, value 0x%x" | |
20 | vmware_palette_write(uint32_t index, uint32_t value) "index %d, value 0x%x" | |
21 | vmware_scratch_read(uint32_t index, uint32_t value) "index %d, value 0x%x" | |
22 | vmware_scratch_write(uint32_t index, uint32_t value) "index %d, value 0x%x" | |
23 | vmware_setmode(uint32_t w, uint32_t h, uint32_t bpp) "%dx%d @ %d bpp" | |
24 | ||
b15e402f MA |
25 | # virtio-gpu-base.c |
26 | virtio_gpu_features(bool virgl) "virgl %d" | |
27 | ||
dec97760 | 28 | # virtio-gpu-3d.c |
500016e5 | 29 | # virtio-gpu.c |
14750ef1 | 30 | virtio_gpu_cmd_get_display_info(void) "" |
1ed2cb32 | 31 | virtio_gpu_cmd_get_edid(uint32_t scanout) "scanout %d" |
14750ef1 DB |
32 | virtio_gpu_cmd_set_scanout(uint32_t id, uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y) "id %d, res 0x%x, w %d, h %d, x %d, y %d" |
33 | virtio_gpu_cmd_res_create_2d(uint32_t res, uint32_t fmt, uint32_t w, uint32_t h) "res 0x%x, fmt 0x%x, w %d, h %d" | |
34 | virtio_gpu_cmd_res_create_3d(uint32_t res, uint32_t fmt, uint32_t w, uint32_t h, uint32_t d) "res 0x%x, fmt 0x%x, w %d, h %d, d %d" | |
35 | virtio_gpu_cmd_res_unref(uint32_t res) "res 0x%x" | |
36 | virtio_gpu_cmd_res_back_attach(uint32_t res) "res 0x%x" | |
37 | virtio_gpu_cmd_res_back_detach(uint32_t res) "res 0x%x" | |
38 | virtio_gpu_cmd_res_xfer_toh_2d(uint32_t res) "res 0x%x" | |
39 | virtio_gpu_cmd_res_xfer_toh_3d(uint32_t res) "res 0x%x" | |
40 | virtio_gpu_cmd_res_xfer_fromh_3d(uint32_t res) "res 0x%x" | |
41 | virtio_gpu_cmd_res_flush(uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y) "res 0x%x, w %d, h %d, x %d, y %d" | |
42 | virtio_gpu_cmd_ctx_create(uint32_t ctx, const char *name) "ctx 0x%x, name %s" | |
43 | virtio_gpu_cmd_ctx_destroy(uint32_t ctx) "ctx 0x%x" | |
44 | virtio_gpu_cmd_ctx_res_attach(uint32_t ctx, uint32_t res) "ctx 0x%x, res 0x%x" | |
45 | virtio_gpu_cmd_ctx_res_detach(uint32_t ctx, uint32_t res) "ctx 0x%x, res 0x%x" | |
46 | virtio_gpu_cmd_ctx_submit(uint32_t ctx, uint32_t size) "ctx 0x%x, size %d" | |
47 | virtio_gpu_update_cursor(uint32_t scanout, uint32_t x, uint32_t y, const char *type, uint32_t res) "scanout %d, x %d, y %d, %s, res 0x%x" | |
48 | virtio_gpu_fence_ctrl(uint64_t fence, uint32_t type) "fence 0x%" PRIx64 ", type 0x%x" | |
49 | virtio_gpu_fence_resp(uint64_t fence) "fence 0x%" PRIx64 | |
50 | ||
500016e5 | 51 | # qxl.c |
14750ef1 DB |
52 | disable qxl_interface_set_mm_time(int qid, uint32_t mm_time) "%d %d" |
53 | disable qxl_io_write_vga(int qid, const char *mode, uint32_t addr, uint32_t val) "%d %s addr=%u val=%u" | |
8908eb1a | 54 | qxl_create_guest_primary(int qid, uint32_t width, uint32_t height, uint64_t mem, uint32_t format, uint32_t position) "%d %ux%u mem=0x%" PRIx64 " %u,%u" |
14750ef1 DB |
55 | qxl_create_guest_primary_rest(int qid, int32_t stride, uint32_t type, uint32_t flags) "%d %d,%d,%d" |
56 | qxl_destroy_primary(int qid) "%d" | |
57 | qxl_enter_vga_mode(int qid) "%d" | |
58 | qxl_exit_vga_mode(int qid) "%d" | |
59 | qxl_hard_reset(int qid, int64_t loadvm) "%d loadvm=%"PRId64 | |
60 | qxl_interface_async_complete_io(int qid, uint32_t current_async, void *cookie) "%d current=%d cookie=%p" | |
61 | qxl_interface_attach_worker(int qid) "%d" | |
62 | qxl_interface_get_init_info(int qid) "%d" | |
63 | qxl_interface_set_compression_level(int qid, int64_t level) "%d %"PRId64 | |
64 | qxl_interface_update_area_complete(int qid, uint32_t surface_id, uint32_t dirty_left, uint32_t dirty_right, uint32_t dirty_top, uint32_t dirty_bottom) "%d surface=%d [%d,%d,%d,%d]" | |
65 | qxl_interface_update_area_complete_rest(int qid, uint32_t num_updated_rects) "%d #=%d" | |
66 | qxl_interface_update_area_complete_overflow(int qid, int max) "%d max=%d" | |
67 | qxl_interface_update_area_complete_schedule_bh(int qid, uint32_t num_dirty) "%d #dirty=%d" | |
68 | qxl_io_destroy_primary_ignored(int qid, const char *mode) "%d %s" | |
00f42697 | 69 | qxl_io_log(int qid, const char *log_buf) "%d %s" |
14750ef1 DB |
70 | qxl_io_read_unexpected(int qid) "%d" |
71 | qxl_io_unexpected_vga_mode(int qid, uint64_t addr, uint64_t val, const char *desc) "%d 0x%"PRIx64"=%"PRIu64" (%s)" | |
72 | qxl_io_write(int qid, const char *mode, uint64_t addr, const char *aname, uint64_t val, unsigned size, int async) "%d %s addr=%"PRIu64 " (%s) val=%"PRIu64" size=%u async=%d" | |
73 | qxl_memslot_add_guest(int qid, uint32_t slot_id, uint64_t guest_start, uint64_t guest_end) "%d %u: guest phys 0x%"PRIx64 " - 0x%" PRIx64 | |
74 | qxl_post_load(int qid, const char *mode) "%d %s" | |
75 | qxl_pre_load(int qid) "%d" | |
76 | qxl_pre_save(int qid) "%d" | |
77 | qxl_reset_surfaces(int qid) "%d" | |
78 | qxl_ring_command_check(int qid, const char *mode) "%d %s" | |
79 | qxl_ring_command_get(int qid, const char *mode) "%d %s" | |
80 | qxl_ring_command_req_notification(int qid) "%d" | |
81 | qxl_ring_cursor_check(int qid, const char *mode) "%d %s" | |
82 | qxl_ring_cursor_get(int qid, const char *mode) "%d %s" | |
83 | qxl_ring_cursor_req_notification(int qid) "%d" | |
84 | qxl_ring_res_push(int qid, const char *mode, uint32_t surface_count, uint32_t free_res, void *last_release, const char *notify) "%d %s s#=%d res#=%d last=%p notify=%s" | |
85 | qxl_ring_res_push_rest(int qid, uint32_t ring_has, uint32_t ring_size, uint32_t prod, uint32_t cons) "%d ring %d/%d [%d,%d]" | |
86 | qxl_ring_res_put(int qid, uint32_t free_res) "%d #res=%d" | |
87 | qxl_set_mode(int qid, int modenr, uint32_t x_res, uint32_t y_res, uint32_t bits, uint64_t devmem) "%d mode=%d [ x=%d y=%d @ bpp=%d devmem=0x%" PRIx64 " ]" | |
88 | qxl_soft_reset(int qid) "%d" | |
89 | qxl_spice_destroy_surfaces_complete(int qid) "%d" | |
90 | qxl_spice_destroy_surfaces(int qid, int async) "%d async=%d" | |
91 | qxl_spice_destroy_surface_wait_complete(int qid, uint32_t id) "%d sid=%d" | |
92 | qxl_spice_destroy_surface_wait(int qid, uint32_t id, int async) "%d sid=%d async=%d" | |
93 | qxl_spice_flush_surfaces_async(int qid, uint32_t surface_count, uint32_t num_free_res) "%d s#=%d, res#=%d" | |
94 | qxl_spice_monitors_config(int qid) "%d" | |
95 | qxl_spice_loadvm_commands(int qid, void *ext, uint32_t count) "%d ext=%p count=%d" | |
96 | qxl_spice_oom(int qid) "%d" | |
97 | qxl_spice_reset_cursor(int qid) "%d" | |
98 | qxl_spice_reset_image_cache(int qid) "%d" | |
99 | qxl_spice_reset_memslots(int qid) "%d" | |
100 | qxl_spice_update_area(int qid, uint32_t surface_id, uint32_t left, uint32_t right, uint32_t top, uint32_t bottom) "%d sid=%d [%d,%d,%d,%d]" | |
101 | qxl_spice_update_area_rest(int qid, uint32_t num_dirty_rects, uint32_t clear_dirty_region) "%d #d=%d clear=%d" | |
e0127d2e | 102 | qxl_surfaces_dirty(int qid, uint64_t offset, uint64_t size) "%d offset=0x%"PRIx64" size=0x%"PRIx64 |
14750ef1 DB |
103 | qxl_send_events(int qid, uint32_t events) "%d %d" |
104 | qxl_send_events_vm_stopped(int qid, uint32_t events) "%d %d" | |
105 | qxl_set_guest_bug(int qid) "%d" | |
106 | qxl_interrupt_client_monitors_config(int qid, int num_heads, void *heads) "%d %d %p" | |
8908eb1a | 107 | qxl_client_monitors_config_unsupported_by_guest(int qid, uint32_t int_mask, void *client_monitors_config) "%d 0x%X %p" |
14750ef1 DB |
108 | qxl_client_monitors_config_unsupported_by_device(int qid, int revision) "%d revision=%d" |
109 | qxl_client_monitors_config_capped(int qid, int requested, int limit) "%d %d %d" | |
110 | qxl_client_monitors_config_crc(int qid, unsigned size, uint32_t crc32) "%d %u %u" | |
111 | qxl_set_client_capabilities_unsupported_by_revision(int qid, int revision) "%d revision=%d" | |
112 | ||
500016e5 | 113 | # qxl-render.c |
14750ef1 DB |
114 | qxl_render_blit(int32_t stride, int32_t left, int32_t right, int32_t top, int32_t bottom) "stride=%d [%d, %d, %d, %d]" |
115 | qxl_render_guest_primary_resized(int32_t width, int32_t height, int32_t stride, int32_t bytes_pp, int32_t bits_pp) "%dx%d, stride %d, bpp %d, depth %d" | |
116 | qxl_render_update_area_done(void *cookie) "%p" | |
cf7dabee | 117 | |
500016e5 | 118 | # vga.c |
cf7dabee GH |
119 | vga_std_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" |
120 | vga_std_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" | |
121 | vga_vbe_read(uint32_t index, uint32_t val) "index 0x%x, val 0x%x" | |
122 | vga_vbe_write(uint32_t index, uint32_t val) "index 0x%x, val 0x%x" | |
ec87f206 | 123 | |
500016e5 | 124 | # cirrus_vga.c |
ec87f206 GH |
125 | vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" |
126 | vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" | |
ec87f206 | 127 | vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x" |
bee61ca2 | 128 | vga_cirrus_write_gr(uint8_t index, uint8_t val) "GR addr 0x%02x, val 0x%02x" |
61527721 | 129 | vga_cirrus_bitblt_start(uint8_t blt_rop, uint8_t blt_mode, uint8_t blt_modeext, int blt_width, int blt_height, int blt_dstpitch, int blt_srcpitch, uint32_t blt_dstaddr, uint32_t blt_srcaddr, uint8_t gr_val) "rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08"PRIx32" saddr=0x%08"PRIx32" writemask=0x%02x" |
a643bd77 | 130 | |
500016e5 | 131 | # sii9022.c |
a643bd77 LW |
132 | sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x" |
133 | sii9022_write_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x" | |
134 | sii9022_switch_mode(const char *mode) "mode: %s" | |
862b4a29 | 135 | |
dec97760 | 136 | # ati.c |
a223b478 GH |
137 | ati_mm_read(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 " %s -> 0x%"PRIx64 |
138 | ati_mm_write(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 " %s <- 0x%"PRIx64 | |
4765384c SS |
139 | |
140 | # artist.c | |
141 | artist_reg_read(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 "%s -> 0x%"PRIx64 | |
142 | artist_reg_write(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 "%s <- 0x%"PRIx64 | |
143 | artist_vram_read(unsigned int size, uint64_t addr, int posx, int posy, uint64_t val) "%u 0x%"PRIx64 " %ux%u-> 0x%"PRIx64 | |
144 | artist_vram_write(unsigned int size, uint64_t addr, uint64_t val) "%u 0x%"PRIx64 " <- 0x%"PRIx64 | |
145 | artist_fill_window(unsigned int start_x, unsigned int start_y, unsigned int width, unsigned int height, uint32_t op, uint32_t ctlpln) "start=%ux%u length=%ux%u op=0x%08x ctlpln=0x%08x" | |
146 | artist_block_move(unsigned int start_x, unsigned int start_y, unsigned int dest_x, unsigned int dest_y, unsigned int width, unsigned int height) "source %ux%u -> dest %ux%u size %ux%u" | |
147 | artist_draw_line(unsigned int start_x, unsigned int start_y, unsigned int end_x, unsigned int end_y) "%ux%u %ux%u" | |
85664cf0 PMD |
148 | |
149 | # cg3.c | |
150 | cg3_read(uint32_t addr, uint32_t val, unsigned size) "read addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u" | |
151 | cg3_write(uint32_t addr, uint32_t val, unsigned size) "write addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u" | |
eeb11680 PMD |
152 | |
153 | # dpcd.c | |
154 | dpcd_read(uint32_t addr, uint8_t val) "read addr:0x%"PRIx32" val:0x%02x" | |
155 | dpcd_write(uint32_t addr, uint8_t val) "write addr:0x%"PRIx32" val:0x%02x" | |
d8327a68 BZ |
156 | |
157 | # sm501.c | |
158 | sm501_system_config_read(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" | |
159 | sm501_system_config_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" | |
160 | sm501_i2c_read(uint32_t addr, uint8_t val) "addr=0x%x, val=0x%x" | |
161 | sm501_i2c_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" | |
162 | sm501_palette_read(uint32_t addr) "addr=0x%x" | |
163 | sm501_palette_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" | |
164 | sm501_disp_ctrl_read(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" | |
165 | sm501_disp_ctrl_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" | |
166 | sm501_2d_engine_read(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" | |
167 | sm501_2d_engine_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" |