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Commit | Line | Data |
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47d37dd9 JQ |
1 | /* |
2 | * QEMU PCI VGA Emulator. | |
3 | * | |
cc228248 GH |
4 | * see docs/specs/standard-vga.txt for virtual hardware specs. |
5 | * | |
47d37dd9 JQ |
6 | * Copyright (c) 2003 Fabrice Bellard |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | */ | |
0b8fa32f | 26 | |
47df5154 | 27 | #include "qemu/osdep.h" |
83c9f4ca | 28 | #include "hw/pci/pci.h" |
a27bd6c7 | 29 | #include "hw/qdev-properties.h" |
d6454270 | 30 | #include "migration/vmstate.h" |
47b43a1f | 31 | #include "vga_int.h" |
28ecbaee | 32 | #include "ui/pixel_ops.h" |
0b8fa32f | 33 | #include "qemu/module.h" |
1de7afc9 | 34 | #include "qemu/timer.h" |
83c9f4ca | 35 | #include "hw/loader.h" |
d46b40fc | 36 | #include "hw/display/edid.h" |
db1015e9 | 37 | #include "qom/object.h" |
cfead313 | 38 | #include "hw/acpi/acpi_aml_interface.h" |
47d37dd9 | 39 | |
803ff052 GH |
40 | enum vga_pci_flags { |
41 | PCI_VGA_FLAG_ENABLE_MMIO = 1, | |
b5682aa4 | 42 | PCI_VGA_FLAG_ENABLE_QEXT = 2, |
d46b40fc | 43 | PCI_VGA_FLAG_ENABLE_EDID = 3, |
803ff052 GH |
44 | }; |
45 | ||
db1015e9 | 46 | struct PCIVGAState { |
47d37dd9 JQ |
47 | PCIDevice dev; |
48 | VGACommonState vga; | |
803ff052 | 49 | uint32_t flags; |
d46b40fc | 50 | qemu_edid_info edid_info; |
803ff052 | 51 | MemoryRegion mmio; |
d46b40fc | 52 | MemoryRegion mrs[4]; |
35f171a2 | 53 | uint8_t edid[384]; |
db1015e9 | 54 | }; |
47d37dd9 | 55 | |
176c324f | 56 | #define TYPE_PCI_VGA "pci-vga" |
8063396b | 57 | OBJECT_DECLARE_SIMPLE_TYPE(PCIVGAState, PCI_VGA) |
176c324f | 58 | |
a4f9631c JQ |
59 | static const VMStateDescription vmstate_vga_pci = { |
60 | .name = "vga", | |
61 | .version_id = 2, | |
62 | .minimum_version_id = 2, | |
d49805ae | 63 | .fields = (VMStateField[]) { |
a4f9631c JQ |
64 | VMSTATE_PCI_DEVICE(dev, PCIVGAState), |
65 | VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState), | |
66 | VMSTATE_END_OF_LIST() | |
47d37dd9 | 67 | } |
a4f9631c | 68 | }; |
47d37dd9 | 69 | |
a8170e5e | 70 | static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr, |
803ff052 GH |
71 | unsigned size) |
72 | { | |
cf45ec6a | 73 | VGACommonState *s = ptr; |
803ff052 GH |
74 | uint64_t ret = 0; |
75 | ||
76 | switch (size) { | |
77 | case 1: | |
cf45ec6a | 78 | ret = vga_ioport_read(s, addr + 0x3c0); |
803ff052 GH |
79 | break; |
80 | case 2: | |
cf45ec6a GH |
81 | ret = vga_ioport_read(s, addr + 0x3c0); |
82 | ret |= vga_ioport_read(s, addr + 0x3c1) << 8; | |
803ff052 GH |
83 | break; |
84 | } | |
85 | return ret; | |
86 | } | |
87 | ||
a8170e5e | 88 | static void pci_vga_ioport_write(void *ptr, hwaddr addr, |
803ff052 GH |
89 | uint64_t val, unsigned size) |
90 | { | |
cf45ec6a | 91 | VGACommonState *s = ptr; |
c96c53b5 | 92 | |
803ff052 GH |
93 | switch (size) { |
94 | case 1: | |
cf45ec6a | 95 | vga_ioport_write(s, addr + 0x3c0, val); |
803ff052 GH |
96 | break; |
97 | case 2: | |
98 | /* | |
99 | * Update bytes in little endian order. Allows to update | |
100 | * indexed registers with a single word write because the | |
101 | * index byte is updated first. | |
102 | */ | |
cf45ec6a GH |
103 | vga_ioport_write(s, addr + 0x3c0, val & 0xff); |
104 | vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff); | |
803ff052 GH |
105 | break; |
106 | } | |
107 | } | |
108 | ||
109 | static const MemoryRegionOps pci_vga_ioport_ops = { | |
110 | .read = pci_vga_ioport_read, | |
111 | .write = pci_vga_ioport_write, | |
112 | .valid.min_access_size = 1, | |
113 | .valid.max_access_size = 4, | |
114 | .impl.min_access_size = 1, | |
115 | .impl.max_access_size = 2, | |
116 | .endianness = DEVICE_LITTLE_ENDIAN, | |
117 | }; | |
118 | ||
a8170e5e | 119 | static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr, |
803ff052 GH |
120 | unsigned size) |
121 | { | |
cf45ec6a | 122 | VGACommonState *s = ptr; |
803ff052 GH |
123 | int index = addr >> 1; |
124 | ||
cf45ec6a GH |
125 | vbe_ioport_write_index(s, 0, index); |
126 | return vbe_ioport_read_data(s, 0); | |
803ff052 GH |
127 | } |
128 | ||
a8170e5e | 129 | static void pci_vga_bochs_write(void *ptr, hwaddr addr, |
803ff052 GH |
130 | uint64_t val, unsigned size) |
131 | { | |
cf45ec6a | 132 | VGACommonState *s = ptr; |
803ff052 GH |
133 | int index = addr >> 1; |
134 | ||
cf45ec6a GH |
135 | vbe_ioport_write_index(s, 0, index); |
136 | vbe_ioport_write_data(s, 0, val); | |
803ff052 GH |
137 | } |
138 | ||
139 | static const MemoryRegionOps pci_vga_bochs_ops = { | |
140 | .read = pci_vga_bochs_read, | |
141 | .write = pci_vga_bochs_write, | |
142 | .valid.min_access_size = 1, | |
143 | .valid.max_access_size = 4, | |
144 | .impl.min_access_size = 2, | |
145 | .impl.max_access_size = 2, | |
146 | .endianness = DEVICE_LITTLE_ENDIAN, | |
147 | }; | |
148 | ||
b5682aa4 GH |
149 | static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size) |
150 | { | |
cf45ec6a | 151 | VGACommonState *s = ptr; |
b5682aa4 GH |
152 | |
153 | switch (addr) { | |
154 | case PCI_VGA_QEXT_REG_SIZE: | |
155 | return PCI_VGA_QEXT_SIZE; | |
156 | case PCI_VGA_QEXT_REG_BYTEORDER: | |
cf45ec6a | 157 | return s->big_endian_fb ? |
b5682aa4 GH |
158 | PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN; |
159 | default: | |
160 | return 0; | |
161 | } | |
162 | } | |
163 | ||
164 | static void pci_vga_qext_write(void *ptr, hwaddr addr, | |
165 | uint64_t val, unsigned size) | |
166 | { | |
cf45ec6a | 167 | VGACommonState *s = ptr; |
b5682aa4 GH |
168 | |
169 | switch (addr) { | |
170 | case PCI_VGA_QEXT_REG_BYTEORDER: | |
171 | if (val == PCI_VGA_QEXT_BIG_ENDIAN) { | |
cf45ec6a | 172 | s->big_endian_fb = true; |
b5682aa4 GH |
173 | } |
174 | if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) { | |
cf45ec6a | 175 | s->big_endian_fb = false; |
b5682aa4 GH |
176 | } |
177 | break; | |
178 | } | |
179 | } | |
180 | ||
3c2784fc DG |
181 | static bool vga_get_big_endian_fb(Object *obj, Error **errp) |
182 | { | |
176c324f | 183 | PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj)); |
3c2784fc DG |
184 | |
185 | return d->vga.big_endian_fb; | |
186 | } | |
187 | ||
188 | static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp) | |
189 | { | |
176c324f | 190 | PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj)); |
3c2784fc DG |
191 | |
192 | d->vga.big_endian_fb = value; | |
193 | } | |
194 | ||
b5682aa4 GH |
195 | static const MemoryRegionOps pci_vga_qext_ops = { |
196 | .read = pci_vga_qext_read, | |
197 | .write = pci_vga_qext_write, | |
198 | .valid.min_access_size = 4, | |
199 | .valid.max_access_size = 4, | |
200 | .endianness = DEVICE_LITTLE_ENDIAN, | |
201 | }; | |
202 | ||
c5d4dac8 | 203 | void pci_std_vga_mmio_region_init(VGACommonState *s, |
93abfc88 | 204 | Object *owner, |
c5d4dac8 GH |
205 | MemoryRegion *parent, |
206 | MemoryRegion *subs, | |
d46b40fc | 207 | bool qext, bool edid) |
220869e1 | 208 | { |
d46b40fc GH |
209 | PCIVGAState *d = container_of(s, PCIVGAState, vga); |
210 | ||
93abfc88 | 211 | memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s, |
220869e1 GH |
212 | "vga ioports remapped", PCI_VGA_IOPORT_SIZE); |
213 | memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET, | |
214 | &subs[0]); | |
215 | ||
93abfc88 | 216 | memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s, |
220869e1 GH |
217 | "bochs dispi interface", PCI_VGA_BOCHS_SIZE); |
218 | memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET, | |
219 | &subs[1]); | |
220 | ||
221 | if (qext) { | |
93abfc88 | 222 | memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s, |
220869e1 GH |
223 | "qemu extended regs", PCI_VGA_QEXT_SIZE); |
224 | memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET, | |
225 | &subs[2]); | |
226 | } | |
d46b40fc GH |
227 | |
228 | if (edid) { | |
229 | qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info); | |
230 | qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid)); | |
231 | memory_region_add_subregion(parent, 0, &subs[3]); | |
232 | } | |
220869e1 GH |
233 | } |
234 | ||
9af21dbe | 235 | static void pci_std_vga_realize(PCIDevice *dev, Error **errp) |
47d37dd9 | 236 | { |
176c324f | 237 | PCIVGAState *d = PCI_VGA(dev); |
0d0302e2 | 238 | VGACommonState *s = &d->vga; |
220869e1 | 239 | bool qext = false; |
d46b40fc | 240 | bool edid = false; |
47d37dd9 | 241 | |
0d0302e2 | 242 | /* vga + console init */ |
6832deb8 TH |
243 | if (!vga_common_init(s, OBJECT(dev), errp)) { |
244 | return; | |
245 | } | |
712f0cc7 PB |
246 | vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev), |
247 | true); | |
47d37dd9 | 248 | |
5643706a | 249 | s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); |
47d37dd9 | 250 | |
0d0302e2 GH |
251 | /* XXX: VGA_RAM_SIZE must be a power of two */ |
252 | pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); | |
47d37dd9 | 253 | |
803ff052 GH |
254 | /* mmio bar for vga register access */ |
255 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) { | |
f872c762 GH |
256 | memory_region_init_io(&d->mmio, OBJECT(dev), &unassigned_io_ops, NULL, |
257 | "vga.mmio", PCI_VGA_MMIO_SIZE); | |
b5682aa4 GH |
258 | |
259 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { | |
220869e1 | 260 | qext = true; |
b5682aa4 GH |
261 | pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); |
262 | } | |
d46b40fc GH |
263 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) { |
264 | edid = true; | |
265 | } | |
266 | pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, | |
267 | qext, edid); | |
b5682aa4 | 268 | |
803ff052 GH |
269 | pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); |
270 | } | |
47d37dd9 JQ |
271 | } |
272 | ||
9af21dbe | 273 | static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp) |
63e3e24d | 274 | { |
176c324f | 275 | PCIVGAState *d = PCI_VGA(dev); |
63e3e24d | 276 | VGACommonState *s = &d->vga; |
220869e1 | 277 | bool qext = false; |
d46b40fc | 278 | bool edid = false; |
63e3e24d GH |
279 | |
280 | /* vga + console init */ | |
6832deb8 TH |
281 | if (!vga_common_init(s, OBJECT(dev), errp)) { |
282 | return; | |
283 | } | |
63e3e24d GH |
284 | s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); |
285 | ||
286 | /* mmio bar */ | |
f872c762 GH |
287 | memory_region_init_io(&d->mmio, OBJECT(dev), &unassigned_io_ops, NULL, |
288 | "vga.mmio", PCI_VGA_MMIO_SIZE); | |
63e3e24d | 289 | |
b5682aa4 | 290 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { |
220869e1 | 291 | qext = true; |
b5682aa4 GH |
292 | pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); |
293 | } | |
d46b40fc GH |
294 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) { |
295 | edid = true; | |
296 | } | |
297 | pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid); | |
b5682aa4 | 298 | |
63e3e24d GH |
299 | pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); |
300 | pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); | |
3c2784fc | 301 | } |
63e3e24d | 302 | |
fc70514c GH |
303 | static void pci_secondary_vga_exit(PCIDevice *dev) |
304 | { | |
305 | PCIVGAState *d = PCI_VGA(dev); | |
306 | VGACommonState *s = &d->vga; | |
307 | ||
308 | graphic_console_close(s->con); | |
0ab90e61 RN |
309 | memory_region_del_subregion(&d->mmio, &d->mrs[0]); |
310 | memory_region_del_subregion(&d->mmio, &d->mrs[1]); | |
311 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { | |
312 | memory_region_del_subregion(&d->mmio, &d->mrs[2]); | |
313 | } | |
314 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) { | |
315 | memory_region_del_subregion(&d->mmio, &d->mrs[3]); | |
316 | } | |
fc70514c GH |
317 | } |
318 | ||
3c2784fc DG |
319 | static void pci_secondary_vga_init(Object *obj) |
320 | { | |
321 | /* Expose framebuffer byteorder via QOM */ | |
322 | object_property_add_bool(obj, "big-endian-framebuffer", | |
d2623129 | 323 | vga_get_big_endian_fb, vga_set_big_endian_fb); |
63e3e24d GH |
324 | } |
325 | ||
326 | static void pci_secondary_vga_reset(DeviceState *dev) | |
327 | { | |
176c324f | 328 | PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev)); |
63e3e24d GH |
329 | vga_common_reset(&d->vga); |
330 | } | |
331 | ||
4a1e244e | 332 | static Property vga_pci_properties[] = { |
9e56edcf | 333 | DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), |
803ff052 | 334 | DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true), |
b5682aa4 GH |
335 | DEFINE_PROP_BIT("qemu-extended-regs", |
336 | PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), | |
d46b40fc | 337 | DEFINE_PROP_BIT("edid", |
0a719662 | 338 | PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true), |
d46b40fc | 339 | DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info), |
1fcfdc43 | 340 | DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false), |
4a1e244e GH |
341 | DEFINE_PROP_END_OF_LIST(), |
342 | }; | |
343 | ||
63e3e24d GH |
344 | static Property secondary_pci_properties[] = { |
345 | DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), | |
b5682aa4 GH |
346 | DEFINE_PROP_BIT("qemu-extended-regs", |
347 | PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), | |
d46b40fc | 348 | DEFINE_PROP_BIT("edid", |
0a719662 | 349 | PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true), |
d46b40fc | 350 | DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info), |
63e3e24d GH |
351 | DEFINE_PROP_END_OF_LIST(), |
352 | }; | |
353 | ||
176c324f GA |
354 | static void vga_pci_class_init(ObjectClass *klass, void *data) |
355 | { | |
356 | DeviceClass *dc = DEVICE_CLASS(klass); | |
357 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
cfead313 | 358 | AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); |
176c324f GA |
359 | |
360 | k->vendor_id = PCI_VENDOR_ID_QEMU; | |
361 | k->device_id = PCI_DEVICE_ID_QEMU_VGA; | |
362 | dc->vmsd = &vmstate_vga_pci; | |
363 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
cfead313 | 364 | adevc->build_dev_aml = build_vga_aml; |
176c324f GA |
365 | } |
366 | ||
367 | static const TypeInfo vga_pci_type_info = { | |
368 | .name = TYPE_PCI_VGA, | |
369 | .parent = TYPE_PCI_DEVICE, | |
370 | .instance_size = sizeof(PCIVGAState), | |
371 | .abstract = true, | |
372 | .class_init = vga_pci_class_init, | |
fd3b02c8 EH |
373 | .interfaces = (InterfaceInfo[]) { |
374 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
cfead313 | 375 | { TYPE_ACPI_DEV_AML_IF }, |
fd3b02c8 EH |
376 | { }, |
377 | }, | |
176c324f GA |
378 | }; |
379 | ||
40021f08 AL |
380 | static void vga_class_init(ObjectClass *klass, void *data) |
381 | { | |
39bffca2 | 382 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
383 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
384 | ||
9af21dbe | 385 | k->realize = pci_std_vga_realize; |
40021f08 | 386 | k->romfile = "vgabios-stdvga.bin"; |
40021f08 | 387 | k->class_id = PCI_CLASS_DISPLAY_VGA; |
4f67d30b | 388 | device_class_set_props(dc, vga_pci_properties); |
2897ae02 | 389 | dc->hotpluggable = false; |
59497037 EH |
390 | |
391 | /* Expose framebuffer byteorder via QOM */ | |
392 | object_class_property_add_bool(klass, "big-endian-framebuffer", | |
393 | vga_get_big_endian_fb, vga_set_big_endian_fb); | |
40021f08 | 394 | } |
32902772 | 395 | |
63e3e24d GH |
396 | static void secondary_class_init(ObjectClass *klass, void *data) |
397 | { | |
398 | DeviceClass *dc = DEVICE_CLASS(klass); | |
399 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
400 | ||
9af21dbe | 401 | k->realize = pci_secondary_vga_realize; |
fc70514c | 402 | k->exit = pci_secondary_vga_exit; |
63e3e24d | 403 | k->class_id = PCI_CLASS_DISPLAY_OTHER; |
4f67d30b | 404 | device_class_set_props(dc, secondary_pci_properties); |
63e3e24d GH |
405 | dc->reset = pci_secondary_vga_reset; |
406 | } | |
407 | ||
8c43a6f0 | 408 | static const TypeInfo vga_info = { |
39bffca2 | 409 | .name = "VGA", |
176c324f | 410 | .parent = TYPE_PCI_VGA, |
39bffca2 | 411 | .class_init = vga_class_init, |
47d37dd9 JQ |
412 | }; |
413 | ||
63e3e24d GH |
414 | static const TypeInfo secondary_info = { |
415 | .name = "secondary-vga", | |
176c324f | 416 | .parent = TYPE_PCI_VGA, |
3c2784fc | 417 | .instance_init = pci_secondary_vga_init, |
63e3e24d GH |
418 | .class_init = secondary_class_init, |
419 | }; | |
420 | ||
83f7d43a | 421 | static void vga_register_types(void) |
47d37dd9 | 422 | { |
176c324f | 423 | type_register_static(&vga_pci_type_info); |
39bffca2 | 424 | type_register_static(&vga_info); |
63e3e24d | 425 | type_register_static(&secondary_info); |
47d37dd9 | 426 | } |
83f7d43a AF |
427 | |
428 | type_init(vga_register_types) |