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Commit | Line | Data |
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47d37dd9 JQ |
1 | /* |
2 | * QEMU PCI VGA Emulator. | |
3 | * | |
cc228248 GH |
4 | * see docs/specs/standard-vga.txt for virtual hardware specs. |
5 | * | |
47d37dd9 JQ |
6 | * Copyright (c) 2003 Fabrice Bellard |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | */ | |
0b8fa32f | 26 | |
47df5154 | 27 | #include "qemu/osdep.h" |
83c9f4ca | 28 | #include "hw/pci/pci.h" |
a27bd6c7 | 29 | #include "hw/qdev-properties.h" |
d6454270 | 30 | #include "migration/vmstate.h" |
47b43a1f | 31 | #include "vga_int.h" |
28ecbaee | 32 | #include "ui/pixel_ops.h" |
0b8fa32f | 33 | #include "qemu/module.h" |
1de7afc9 | 34 | #include "qemu/timer.h" |
83c9f4ca | 35 | #include "hw/loader.h" |
d46b40fc | 36 | #include "hw/display/edid.h" |
47d37dd9 | 37 | |
803ff052 GH |
38 | enum vga_pci_flags { |
39 | PCI_VGA_FLAG_ENABLE_MMIO = 1, | |
b5682aa4 | 40 | PCI_VGA_FLAG_ENABLE_QEXT = 2, |
d46b40fc | 41 | PCI_VGA_FLAG_ENABLE_EDID = 3, |
803ff052 GH |
42 | }; |
43 | ||
47d37dd9 JQ |
44 | typedef struct PCIVGAState { |
45 | PCIDevice dev; | |
46 | VGACommonState vga; | |
803ff052 | 47 | uint32_t flags; |
d46b40fc | 48 | qemu_edid_info edid_info; |
803ff052 | 49 | MemoryRegion mmio; |
d46b40fc GH |
50 | MemoryRegion mrs[4]; |
51 | uint8_t edid[256]; | |
47d37dd9 JQ |
52 | } PCIVGAState; |
53 | ||
176c324f GA |
54 | #define TYPE_PCI_VGA "pci-vga" |
55 | #define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA) | |
56 | ||
a4f9631c JQ |
57 | static const VMStateDescription vmstate_vga_pci = { |
58 | .name = "vga", | |
59 | .version_id = 2, | |
60 | .minimum_version_id = 2, | |
d49805ae | 61 | .fields = (VMStateField[]) { |
a4f9631c JQ |
62 | VMSTATE_PCI_DEVICE(dev, PCIVGAState), |
63 | VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState), | |
64 | VMSTATE_END_OF_LIST() | |
47d37dd9 | 65 | } |
a4f9631c | 66 | }; |
47d37dd9 | 67 | |
a8170e5e | 68 | static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr, |
803ff052 GH |
69 | unsigned size) |
70 | { | |
cf45ec6a | 71 | VGACommonState *s = ptr; |
803ff052 GH |
72 | uint64_t ret = 0; |
73 | ||
74 | switch (size) { | |
75 | case 1: | |
cf45ec6a | 76 | ret = vga_ioport_read(s, addr + 0x3c0); |
803ff052 GH |
77 | break; |
78 | case 2: | |
cf45ec6a GH |
79 | ret = vga_ioport_read(s, addr + 0x3c0); |
80 | ret |= vga_ioport_read(s, addr + 0x3c1) << 8; | |
803ff052 GH |
81 | break; |
82 | } | |
83 | return ret; | |
84 | } | |
85 | ||
a8170e5e | 86 | static void pci_vga_ioport_write(void *ptr, hwaddr addr, |
803ff052 GH |
87 | uint64_t val, unsigned size) |
88 | { | |
cf45ec6a | 89 | VGACommonState *s = ptr; |
c96c53b5 | 90 | |
803ff052 GH |
91 | switch (size) { |
92 | case 1: | |
cf45ec6a | 93 | vga_ioport_write(s, addr + 0x3c0, val); |
803ff052 GH |
94 | break; |
95 | case 2: | |
96 | /* | |
97 | * Update bytes in little endian order. Allows to update | |
98 | * indexed registers with a single word write because the | |
99 | * index byte is updated first. | |
100 | */ | |
cf45ec6a GH |
101 | vga_ioport_write(s, addr + 0x3c0, val & 0xff); |
102 | vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff); | |
803ff052 GH |
103 | break; |
104 | } | |
105 | } | |
106 | ||
107 | static const MemoryRegionOps pci_vga_ioport_ops = { | |
108 | .read = pci_vga_ioport_read, | |
109 | .write = pci_vga_ioport_write, | |
110 | .valid.min_access_size = 1, | |
111 | .valid.max_access_size = 4, | |
112 | .impl.min_access_size = 1, | |
113 | .impl.max_access_size = 2, | |
114 | .endianness = DEVICE_LITTLE_ENDIAN, | |
115 | }; | |
116 | ||
a8170e5e | 117 | static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr, |
803ff052 GH |
118 | unsigned size) |
119 | { | |
cf45ec6a | 120 | VGACommonState *s = ptr; |
803ff052 GH |
121 | int index = addr >> 1; |
122 | ||
cf45ec6a GH |
123 | vbe_ioport_write_index(s, 0, index); |
124 | return vbe_ioport_read_data(s, 0); | |
803ff052 GH |
125 | } |
126 | ||
a8170e5e | 127 | static void pci_vga_bochs_write(void *ptr, hwaddr addr, |
803ff052 GH |
128 | uint64_t val, unsigned size) |
129 | { | |
cf45ec6a | 130 | VGACommonState *s = ptr; |
803ff052 GH |
131 | int index = addr >> 1; |
132 | ||
cf45ec6a GH |
133 | vbe_ioport_write_index(s, 0, index); |
134 | vbe_ioport_write_data(s, 0, val); | |
803ff052 GH |
135 | } |
136 | ||
137 | static const MemoryRegionOps pci_vga_bochs_ops = { | |
138 | .read = pci_vga_bochs_read, | |
139 | .write = pci_vga_bochs_write, | |
140 | .valid.min_access_size = 1, | |
141 | .valid.max_access_size = 4, | |
142 | .impl.min_access_size = 2, | |
143 | .impl.max_access_size = 2, | |
144 | .endianness = DEVICE_LITTLE_ENDIAN, | |
145 | }; | |
146 | ||
b5682aa4 GH |
147 | static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size) |
148 | { | |
cf45ec6a | 149 | VGACommonState *s = ptr; |
b5682aa4 GH |
150 | |
151 | switch (addr) { | |
152 | case PCI_VGA_QEXT_REG_SIZE: | |
153 | return PCI_VGA_QEXT_SIZE; | |
154 | case PCI_VGA_QEXT_REG_BYTEORDER: | |
cf45ec6a | 155 | return s->big_endian_fb ? |
b5682aa4 GH |
156 | PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN; |
157 | default: | |
158 | return 0; | |
159 | } | |
160 | } | |
161 | ||
162 | static void pci_vga_qext_write(void *ptr, hwaddr addr, | |
163 | uint64_t val, unsigned size) | |
164 | { | |
cf45ec6a | 165 | VGACommonState *s = ptr; |
b5682aa4 GH |
166 | |
167 | switch (addr) { | |
168 | case PCI_VGA_QEXT_REG_BYTEORDER: | |
169 | if (val == PCI_VGA_QEXT_BIG_ENDIAN) { | |
cf45ec6a | 170 | s->big_endian_fb = true; |
b5682aa4 GH |
171 | } |
172 | if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) { | |
cf45ec6a | 173 | s->big_endian_fb = false; |
b5682aa4 GH |
174 | } |
175 | break; | |
176 | } | |
177 | } | |
178 | ||
3c2784fc DG |
179 | static bool vga_get_big_endian_fb(Object *obj, Error **errp) |
180 | { | |
176c324f | 181 | PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj)); |
3c2784fc DG |
182 | |
183 | return d->vga.big_endian_fb; | |
184 | } | |
185 | ||
186 | static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp) | |
187 | { | |
176c324f | 188 | PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj)); |
3c2784fc DG |
189 | |
190 | d->vga.big_endian_fb = value; | |
191 | } | |
192 | ||
b5682aa4 GH |
193 | static const MemoryRegionOps pci_vga_qext_ops = { |
194 | .read = pci_vga_qext_read, | |
195 | .write = pci_vga_qext_write, | |
196 | .valid.min_access_size = 4, | |
197 | .valid.max_access_size = 4, | |
198 | .endianness = DEVICE_LITTLE_ENDIAN, | |
199 | }; | |
200 | ||
c5d4dac8 | 201 | void pci_std_vga_mmio_region_init(VGACommonState *s, |
93abfc88 | 202 | Object *owner, |
c5d4dac8 GH |
203 | MemoryRegion *parent, |
204 | MemoryRegion *subs, | |
d46b40fc | 205 | bool qext, bool edid) |
220869e1 | 206 | { |
d46b40fc GH |
207 | PCIVGAState *d = container_of(s, PCIVGAState, vga); |
208 | ||
93abfc88 | 209 | memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s, |
220869e1 GH |
210 | "vga ioports remapped", PCI_VGA_IOPORT_SIZE); |
211 | memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET, | |
212 | &subs[0]); | |
213 | ||
93abfc88 | 214 | memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s, |
220869e1 GH |
215 | "bochs dispi interface", PCI_VGA_BOCHS_SIZE); |
216 | memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET, | |
217 | &subs[1]); | |
218 | ||
219 | if (qext) { | |
93abfc88 | 220 | memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s, |
220869e1 GH |
221 | "qemu extended regs", PCI_VGA_QEXT_SIZE); |
222 | memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET, | |
223 | &subs[2]); | |
224 | } | |
d46b40fc GH |
225 | |
226 | if (edid) { | |
227 | qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info); | |
228 | qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid)); | |
229 | memory_region_add_subregion(parent, 0, &subs[3]); | |
230 | } | |
220869e1 GH |
231 | } |
232 | ||
9af21dbe | 233 | static void pci_std_vga_realize(PCIDevice *dev, Error **errp) |
47d37dd9 | 234 | { |
176c324f | 235 | PCIVGAState *d = PCI_VGA(dev); |
0d0302e2 | 236 | VGACommonState *s = &d->vga; |
220869e1 | 237 | bool qext = false; |
d46b40fc | 238 | bool edid = false; |
47d37dd9 | 239 | |
0d0302e2 | 240 | /* vga + console init */ |
1fcfdc43 | 241 | vga_common_init(s, OBJECT(dev)); |
712f0cc7 PB |
242 | vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev), |
243 | true); | |
47d37dd9 | 244 | |
5643706a | 245 | s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); |
47d37dd9 | 246 | |
0d0302e2 GH |
247 | /* XXX: VGA_RAM_SIZE must be a power of two */ |
248 | pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); | |
47d37dd9 | 249 | |
803ff052 GH |
250 | /* mmio bar for vga register access */ |
251 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) { | |
f872c762 GH |
252 | memory_region_init_io(&d->mmio, OBJECT(dev), &unassigned_io_ops, NULL, |
253 | "vga.mmio", PCI_VGA_MMIO_SIZE); | |
b5682aa4 GH |
254 | |
255 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { | |
220869e1 | 256 | qext = true; |
b5682aa4 GH |
257 | pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); |
258 | } | |
d46b40fc GH |
259 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) { |
260 | edid = true; | |
261 | } | |
262 | pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, | |
263 | qext, edid); | |
b5682aa4 | 264 | |
803ff052 GH |
265 | pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); |
266 | } | |
47d37dd9 JQ |
267 | } |
268 | ||
3c2784fc DG |
269 | static void pci_std_vga_init(Object *obj) |
270 | { | |
271 | /* Expose framebuffer byteorder via QOM */ | |
272 | object_property_add_bool(obj, "big-endian-framebuffer", | |
d2623129 | 273 | vga_get_big_endian_fb, vga_set_big_endian_fb); |
3c2784fc DG |
274 | } |
275 | ||
9af21dbe | 276 | static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp) |
63e3e24d | 277 | { |
176c324f | 278 | PCIVGAState *d = PCI_VGA(dev); |
63e3e24d | 279 | VGACommonState *s = &d->vga; |
220869e1 | 280 | bool qext = false; |
d46b40fc | 281 | bool edid = false; |
63e3e24d GH |
282 | |
283 | /* vga + console init */ | |
1fcfdc43 | 284 | vga_common_init(s, OBJECT(dev)); |
63e3e24d GH |
285 | s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); |
286 | ||
287 | /* mmio bar */ | |
f872c762 GH |
288 | memory_region_init_io(&d->mmio, OBJECT(dev), &unassigned_io_ops, NULL, |
289 | "vga.mmio", PCI_VGA_MMIO_SIZE); | |
63e3e24d | 290 | |
b5682aa4 | 291 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { |
220869e1 | 292 | qext = true; |
b5682aa4 GH |
293 | pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); |
294 | } | |
d46b40fc GH |
295 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) { |
296 | edid = true; | |
297 | } | |
298 | pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid); | |
b5682aa4 | 299 | |
63e3e24d GH |
300 | pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); |
301 | pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); | |
3c2784fc | 302 | } |
63e3e24d | 303 | |
fc70514c GH |
304 | static void pci_secondary_vga_exit(PCIDevice *dev) |
305 | { | |
306 | PCIVGAState *d = PCI_VGA(dev); | |
307 | VGACommonState *s = &d->vga; | |
308 | ||
309 | graphic_console_close(s->con); | |
0ab90e61 RN |
310 | memory_region_del_subregion(&d->mmio, &d->mrs[0]); |
311 | memory_region_del_subregion(&d->mmio, &d->mrs[1]); | |
312 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) { | |
313 | memory_region_del_subregion(&d->mmio, &d->mrs[2]); | |
314 | } | |
315 | if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) { | |
316 | memory_region_del_subregion(&d->mmio, &d->mrs[3]); | |
317 | } | |
fc70514c GH |
318 | } |
319 | ||
3c2784fc DG |
320 | static void pci_secondary_vga_init(Object *obj) |
321 | { | |
322 | /* Expose framebuffer byteorder via QOM */ | |
323 | object_property_add_bool(obj, "big-endian-framebuffer", | |
d2623129 | 324 | vga_get_big_endian_fb, vga_set_big_endian_fb); |
63e3e24d GH |
325 | } |
326 | ||
327 | static void pci_secondary_vga_reset(DeviceState *dev) | |
328 | { | |
176c324f | 329 | PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev)); |
63e3e24d GH |
330 | vga_common_reset(&d->vga); |
331 | } | |
332 | ||
4a1e244e | 333 | static Property vga_pci_properties[] = { |
9e56edcf | 334 | DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), |
803ff052 | 335 | DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true), |
b5682aa4 GH |
336 | DEFINE_PROP_BIT("qemu-extended-regs", |
337 | PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), | |
d46b40fc | 338 | DEFINE_PROP_BIT("edid", |
0a719662 | 339 | PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true), |
d46b40fc | 340 | DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info), |
1fcfdc43 | 341 | DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false), |
4a1e244e GH |
342 | DEFINE_PROP_END_OF_LIST(), |
343 | }; | |
344 | ||
63e3e24d GH |
345 | static Property secondary_pci_properties[] = { |
346 | DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16), | |
b5682aa4 GH |
347 | DEFINE_PROP_BIT("qemu-extended-regs", |
348 | PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true), | |
d46b40fc | 349 | DEFINE_PROP_BIT("edid", |
0a719662 | 350 | PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true), |
d46b40fc | 351 | DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info), |
63e3e24d GH |
352 | DEFINE_PROP_END_OF_LIST(), |
353 | }; | |
354 | ||
176c324f GA |
355 | static void vga_pci_class_init(ObjectClass *klass, void *data) |
356 | { | |
357 | DeviceClass *dc = DEVICE_CLASS(klass); | |
358 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
359 | ||
360 | k->vendor_id = PCI_VENDOR_ID_QEMU; | |
361 | k->device_id = PCI_DEVICE_ID_QEMU_VGA; | |
362 | dc->vmsd = &vmstate_vga_pci; | |
363 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
364 | } | |
365 | ||
366 | static const TypeInfo vga_pci_type_info = { | |
367 | .name = TYPE_PCI_VGA, | |
368 | .parent = TYPE_PCI_DEVICE, | |
369 | .instance_size = sizeof(PCIVGAState), | |
370 | .abstract = true, | |
371 | .class_init = vga_pci_class_init, | |
fd3b02c8 EH |
372 | .interfaces = (InterfaceInfo[]) { |
373 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
374 | { }, | |
375 | }, | |
176c324f GA |
376 | }; |
377 | ||
40021f08 AL |
378 | static void vga_class_init(ObjectClass *klass, void *data) |
379 | { | |
39bffca2 | 380 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
381 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
382 | ||
9af21dbe | 383 | k->realize = pci_std_vga_realize; |
40021f08 | 384 | k->romfile = "vgabios-stdvga.bin"; |
40021f08 | 385 | k->class_id = PCI_CLASS_DISPLAY_VGA; |
4f67d30b | 386 | device_class_set_props(dc, vga_pci_properties); |
2897ae02 | 387 | dc->hotpluggable = false; |
40021f08 | 388 | } |
32902772 | 389 | |
63e3e24d GH |
390 | static void secondary_class_init(ObjectClass *klass, void *data) |
391 | { | |
392 | DeviceClass *dc = DEVICE_CLASS(klass); | |
393 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
394 | ||
9af21dbe | 395 | k->realize = pci_secondary_vga_realize; |
fc70514c | 396 | k->exit = pci_secondary_vga_exit; |
63e3e24d | 397 | k->class_id = PCI_CLASS_DISPLAY_OTHER; |
4f67d30b | 398 | device_class_set_props(dc, secondary_pci_properties); |
63e3e24d GH |
399 | dc->reset = pci_secondary_vga_reset; |
400 | } | |
401 | ||
8c43a6f0 | 402 | static const TypeInfo vga_info = { |
39bffca2 | 403 | .name = "VGA", |
176c324f | 404 | .parent = TYPE_PCI_VGA, |
3c2784fc | 405 | .instance_init = pci_std_vga_init, |
39bffca2 | 406 | .class_init = vga_class_init, |
47d37dd9 JQ |
407 | }; |
408 | ||
63e3e24d GH |
409 | static const TypeInfo secondary_info = { |
410 | .name = "secondary-vga", | |
176c324f | 411 | .parent = TYPE_PCI_VGA, |
3c2784fc | 412 | .instance_init = pci_secondary_vga_init, |
63e3e24d GH |
413 | .class_init = secondary_class_init, |
414 | }; | |
415 | ||
83f7d43a | 416 | static void vga_register_types(void) |
47d37dd9 | 417 | { |
176c324f | 418 | type_register_static(&vga_pci_type_info); |
39bffca2 | 419 | type_register_static(&vga_info); |
63e3e24d | 420 | type_register_static(&secondary_info); |
47d37dd9 | 421 | } |
83f7d43a AF |
422 | |
423 | type_init(vga_register_types) |