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1/*
2 * QEMU internal VGA defines.
5fafdf24 3 *
798b0c25 4 * Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24 5 *
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
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24#ifndef HW_VGA_INT_H
25#define HW_VGA_INT_H 1
11b6b345 26
a9c94277 27#include "hw/hw.h"
022c62cb 28#include "exec/memory.h"
11b6b345 29
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30#define ST01_V_RETRACE 0x08
31#define ST01_DISP_ENABLE 0x01
32
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33#define VBE_DISPI_MAX_XRES 16000
34#define VBE_DISPI_MAX_YRES 12000
8454df8b 35#define VBE_DISPI_MAX_BPP 32
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36
37#define VBE_DISPI_INDEX_ID 0x0
38#define VBE_DISPI_INDEX_XRES 0x1
39#define VBE_DISPI_INDEX_YRES 0x2
40#define VBE_DISPI_INDEX_BPP 0x3
41#define VBE_DISPI_INDEX_ENABLE 0x4
42#define VBE_DISPI_INDEX_BANK 0x5
43#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
44#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
45#define VBE_DISPI_INDEX_X_OFFSET 0x8
46#define VBE_DISPI_INDEX_Y_OFFSET 0x9
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GH
47#define VBE_DISPI_INDEX_NB 0xa /* size of vbe_regs[] */
48#define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa /* read-only, not in vbe_regs */
3b46e624 49
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50#define VBE_DISPI_ID0 0xB0C0
51#define VBE_DISPI_ID1 0xB0C1
52#define VBE_DISPI_ID2 0xB0C2
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53#define VBE_DISPI_ID3 0xB0C3
54#define VBE_DISPI_ID4 0xB0C4
af92284b 55#define VBE_DISPI_ID5 0xB0C5
3b46e624 56
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57#define VBE_DISPI_DISABLED 0x00
58#define VBE_DISPI_ENABLED 0x01
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59#define VBE_DISPI_GETCAPS 0x02
60#define VBE_DISPI_8BIT_DAC 0x20
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61#define VBE_DISPI_LFB_ENABLED 0x40
62#define VBE_DISPI_NOCLEARMEM 0x80
3b46e624 63
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64#define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
65
798b0c25 66#define CH_ATTR_SIZE (160 * 100)
8454df8b 67#define VGA_MAX_HEIGHT 2048
4e3e9d0b 68
cb5a7aa8 69struct vga_precise_retrace {
70 int64_t ticks_per_char;
71 int64_t total_chars;
72 int htotal;
73 int hstart;
74 int hend;
75 int vstart;
76 int vend;
77 int freq;
78};
79
80union vga_retrace {
81 struct vga_precise_retrace precise;
82};
83
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84struct VGACommonState;
85typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
86typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);
87
88typedef struct VGACommonState {
80763888 89 MemoryRegion *legacy_address_space;
4e12cd94 90 uint8_t *vram_ptr;
b1950430 91 MemoryRegion vram;
8294a64d 92 MemoryRegion vram_vbe;
a19cbfb3 93 uint32_t vram_size;
4a1e244e 94 uint32_t vram_size_mb; /* property */
54a85d46 95 uint32_t vbe_size;
4e12cd94 96 uint32_t latch;
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97 bool has_chain4_alias;
98 MemoryRegion chain4_alias;
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99 uint8_t sr_index;
100 uint8_t sr[256];
94ef4f33 101 uint8_t sr_vbe[256];
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102 uint8_t gr_index;
103 uint8_t gr[256];
104 uint8_t ar_index;
105 uint8_t ar[21];
106 int ar_flip_flop;
107 uint8_t cr_index;
108 uint8_t cr[256]; /* CRT registers */
109 uint8_t msr; /* Misc Output Register */
110 uint8_t fcr; /* Feature Control Register */
111 uint8_t st00; /* status 0 */
112 uint8_t st01; /* status 1 */
113 uint8_t dac_state;
114 uint8_t dac_sub_index;
115 uint8_t dac_read_index;
116 uint8_t dac_write_index;
117 uint8_t dac_cache[3]; /* used when writing */
118 int dac_8bit;
119 uint8_t palette[768];
120 int32_t bank_offset;
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121 int (*get_bpp)(struct VGACommonState *s);
122 void (*get_offsets)(struct VGACommonState *s,
123 uint32_t *pline_offset,
124 uint32_t *pstart_addr,
125 uint32_t *pline_compare);
126 void (*get_resolution)(struct VGACommonState *s,
127 int *pwidth,
128 int *pheight);
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129 PortioList vga_port_list;
130 PortioList vbe_port_list;
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131 /* bochs vbe state */
132 uint16_t vbe_index;
133 uint16_t vbe_regs[VBE_DISPI_INDEX_NB];
134 uint32_t vbe_start_addr;
135 uint32_t vbe_line_offset;
136 uint32_t vbe_bank_mask;
137 int vbe_mapped;
4e12cd94 138 /* display refresh support */
c78f7137 139 QemuConsole *con;
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140 uint32_t font_offsets[2];
141 int graphic_mode;
142 uint8_t shift_control;
143 uint8_t double_scan;
144 uint32_t line_offset;
145 uint32_t line_compare;
146 uint32_t start_addr;
147 uint32_t plane_updated;
148 uint32_t last_line_offset;
149 uint8_t last_cw, last_ch;
150 uint32_t last_width, last_height; /* in chars or pixels */
151 uint32_t last_scr_width, last_scr_height; /* in pixels */
152 uint32_t last_depth; /* in bits */
c3b10605 153 bool last_byteswap;
55080993 154 bool force_shadow;
4e12cd94 155 uint8_t cursor_start, cursor_end;
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156 bool cursor_visible_phase;
157 int64_t cursor_blink_time;
4e12cd94 158 uint32_t cursor_offset;
380cd056 159 const GraphicHwOps *hw_ops;
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160 bool full_update_text;
161 bool full_update_gfx;
2c7d8736 162 bool big_endian_fb;
c3b10605 163 bool default_endian_fb;
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164 /* hardware mouse cursor support */
165 uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
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166 uint32_t hw_cursor_x;
167 uint32_t hw_cursor_y;
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168 void (*cursor_invalidate)(struct VGACommonState *s);
169 void (*cursor_draw_line)(struct VGACommonState *s, uint8_t *d, int y);
170 /* tell for each page if it has been updated since the last time */
171 uint32_t last_palette[256];
172 uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
173 /* retrace */
174 vga_retrace_fn retrace;
175 vga_update_retrace_info_fn update_retrace_info;
cb5a7aa8 176 union vga_retrace retrace_info;
2a3138ab 177 uint8_t is_vbe_vmstate;
4e12cd94 178} VGACommonState;
4e3e9d0b 179
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180static inline int c6_to_8(int v)
181{
182 int b;
183 v &= 0x3f;
184 b = v & 1;
185 return (v << 2) | (b << 1) | b;
186}
187
e2bbfc8e 188void vga_common_init(VGACommonState *s, Object *obj, bool global_vmstate);
712f0cc7 189void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
0a039dc7 190 MemoryRegion *address_space_io, bool init_vga_ports);
c84b28ee 191MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
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192 const MemoryRegionPortio **vga_ports,
193 const MemoryRegionPortio **vbe_ports);
03a3e7ba 194void vga_common_reset(VGACommonState *s);
2bec46dc 195
b51d7b2e 196void vga_sync_dirty_bitmap(VGACommonState *s);
a4a2f59c 197void vga_dirty_log_start(VGACommonState *s);
b5cc6e32 198void vga_dirty_log_stop(VGACommonState *s);
2bec46dc 199
11b6b345 200extern const VMStateDescription vmstate_vga_common;
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201uint32_t vga_ioport_read(void *opaque, uint32_t addr);
202void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
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203uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr);
204void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val);
a4a2f59c 205void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
a8aa669b 206
25a18cbd 207int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
803ff052 208
83118327 209void vga_init_vbe(VGACommonState *s, Object *obj, MemoryRegion *address_space);
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210uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr);
211void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val);
212void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val);
25a18cbd 213
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214extern const uint8_t sr_mask[8];
215extern const uint8_t gr_mask[16];
fbe1b595 216
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217#define VGABIOS_FILENAME "vgabios.bin"
218#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
fbe1b595 219
b1950430 220extern const MemoryRegionOps vga_mem_ops;
cb9c377f 221
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222/* vga-pci.c */
223void pci_std_vga_mmio_region_init(VGACommonState *s,
224 MemoryRegion *parent,
225 MemoryRegion *subs,
226 bool qext);
227
cb9c377f 228#endif