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1/*
2 * Virtio GPU Device
3 *
4 * Copyright Red Hat, Inc. 2013-2014
5 *
6 * Authors:
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 */
13
9b8bfe21 14#include "qemu/osdep.h"
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15#include "qemu-common.h"
16#include "qemu/iov.h"
17#include "trace.h"
18#include "hw/virtio/virtio.h"
19#include "hw/virtio/virtio-gpu.h"
d0f0c865 20#include "qapi/error.h"
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21
22#ifdef CONFIG_VIRGL
23
a9c94277 24#include <virglrenderer.h>
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25
26static struct virgl_renderer_callbacks virtio_gpu_3d_cbs;
27
28static void virgl_cmd_create_resource_2d(VirtIOGPU *g,
29 struct virtio_gpu_ctrl_command *cmd)
30{
31 struct virtio_gpu_resource_create_2d c2d;
32 struct virgl_renderer_resource_create_args args;
33
34 VIRTIO_GPU_FILL_CMD(c2d);
35 trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format,
36 c2d.width, c2d.height);
37
38 args.handle = c2d.resource_id;
39 args.target = 2;
40 args.format = c2d.format;
41 args.bind = (1 << 1);
42 args.width = c2d.width;
43 args.height = c2d.height;
44 args.depth = 1;
45 args.array_size = 1;
46 args.last_level = 0;
47 args.nr_samples = 0;
48 args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
49 virgl_renderer_resource_create(&args, NULL, 0);
50}
51
52static void virgl_cmd_create_resource_3d(VirtIOGPU *g,
53 struct virtio_gpu_ctrl_command *cmd)
54{
55 struct virtio_gpu_resource_create_3d c3d;
56 struct virgl_renderer_resource_create_args args;
57
58 VIRTIO_GPU_FILL_CMD(c3d);
59 trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format,
60 c3d.width, c3d.height, c3d.depth);
61
62 args.handle = c3d.resource_id;
63 args.target = c3d.target;
64 args.format = c3d.format;
65 args.bind = c3d.bind;
66 args.width = c3d.width;
67 args.height = c3d.height;
68 args.depth = c3d.depth;
69 args.array_size = c3d.array_size;
70 args.last_level = c3d.last_level;
71 args.nr_samples = c3d.nr_samples;
72 args.flags = c3d.flags;
73 virgl_renderer_resource_create(&args, NULL, 0);
74}
75
76static void virgl_cmd_resource_unref(VirtIOGPU *g,
77 struct virtio_gpu_ctrl_command *cmd)
78{
79 struct virtio_gpu_resource_unref unref;
80
81 VIRTIO_GPU_FILL_CMD(unref);
82 trace_virtio_gpu_cmd_res_unref(unref.resource_id);
83
84 virgl_renderer_resource_unref(unref.resource_id);
85}
86
87static void virgl_cmd_context_create(VirtIOGPU *g,
88 struct virtio_gpu_ctrl_command *cmd)
89{
90 struct virtio_gpu_ctx_create cc;
91
92 VIRTIO_GPU_FILL_CMD(cc);
93 trace_virtio_gpu_cmd_ctx_create(cc.hdr.ctx_id,
94 cc.debug_name);
95
96 virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen,
97 cc.debug_name);
98}
99
100static void virgl_cmd_context_destroy(VirtIOGPU *g,
101 struct virtio_gpu_ctrl_command *cmd)
102{
103 struct virtio_gpu_ctx_destroy cd;
104
105 VIRTIO_GPU_FILL_CMD(cd);
106 trace_virtio_gpu_cmd_ctx_destroy(cd.hdr.ctx_id);
107
108 virgl_renderer_context_destroy(cd.hdr.ctx_id);
109}
110
111static void virtio_gpu_rect_update(VirtIOGPU *g, int idx, int x, int y,
112 int width, int height)
113{
114 if (!g->scanout[idx].con) {
115 return;
116 }
117
118 dpy_gl_update(g->scanout[idx].con, x, y, width, height);
119}
120
121static void virgl_cmd_resource_flush(VirtIOGPU *g,
122 struct virtio_gpu_ctrl_command *cmd)
123{
124 struct virtio_gpu_resource_flush rf;
125 int i;
126
127 VIRTIO_GPU_FILL_CMD(rf);
128 trace_virtio_gpu_cmd_res_flush(rf.resource_id,
129 rf.r.width, rf.r.height, rf.r.x, rf.r.y);
130
2fe76055 131 for (i = 0; i < g->conf.max_outputs; i++) {
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132 if (g->scanout[i].resource_id != rf.resource_id) {
133 continue;
134 }
135 virtio_gpu_rect_update(g, i, rf.r.x, rf.r.y, rf.r.width, rf.r.height);
136 }
137}
138
139static void virgl_cmd_set_scanout(VirtIOGPU *g,
140 struct virtio_gpu_ctrl_command *cmd)
141{
142 struct virtio_gpu_set_scanout ss;
143 struct virgl_renderer_resource_info info;
144 int ret;
145
146 VIRTIO_GPU_FILL_CMD(ss);
147 trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id,
148 ss.r.width, ss.r.height, ss.r.x, ss.r.y);
149
2fe76055 150 if (ss.scanout_id >= g->conf.max_outputs) {
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151 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
152 __func__, ss.scanout_id);
153 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
154 return;
155 }
156 g->enable = 1;
157
158 memset(&info, 0, sizeof(info));
159
160 if (ss.resource_id && ss.r.width && ss.r.height) {
161 ret = virgl_renderer_resource_get_info(ss.resource_id, &info);
162 if (ret == -1) {
163 qemu_log_mask(LOG_GUEST_ERROR,
164 "%s: illegal resource specified %d\n",
165 __func__, ss.resource_id);
166 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
167 return;
168 }
169 qemu_console_resize(g->scanout[ss.scanout_id].con,
170 ss.r.width, ss.r.height);
171 virgl_renderer_force_ctx_0();
172 dpy_gl_scanout(g->scanout[ss.scanout_id].con, info.tex_id,
173 info.flags & 1 /* FIXME: Y_0_TOP */,
9d8256eb 174 info.width, info.height,
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175 ss.r.x, ss.r.y, ss.r.width, ss.r.height);
176 } else {
177 if (ss.scanout_id != 0) {
178 dpy_gfx_replace_surface(g->scanout[ss.scanout_id].con, NULL);
179 }
180 dpy_gl_scanout(g->scanout[ss.scanout_id].con, 0, false,
9d8256eb 181 0, 0, 0, 0, 0, 0);
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182 }
183 g->scanout[ss.scanout_id].resource_id = ss.resource_id;
184}
185
186static void virgl_cmd_submit_3d(VirtIOGPU *g,
187 struct virtio_gpu_ctrl_command *cmd)
188{
189 struct virtio_gpu_cmd_submit cs;
190 void *buf;
191 size_t s;
192
193 VIRTIO_GPU_FILL_CMD(cs);
194 trace_virtio_gpu_cmd_ctx_submit(cs.hdr.ctx_id, cs.size);
195
196 buf = g_malloc(cs.size);
197 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
198 sizeof(cs), buf, cs.size);
199 if (s != cs.size) {
200 qemu_log_mask(LOG_GUEST_ERROR, "%s: size mismatch (%zd/%d)",
201 __func__, s, cs.size);
202 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
8d94c1ca 203 goto out;
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204 }
205
206 if (virtio_gpu_stats_enabled(g->conf)) {
207 g->stats.req_3d++;
208 g->stats.bytes_3d += cs.size;
209 }
210
211 virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4);
212
8d94c1ca 213out:
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214 g_free(buf);
215}
216
217static void virgl_cmd_transfer_to_host_2d(VirtIOGPU *g,
218 struct virtio_gpu_ctrl_command *cmd)
219{
220 struct virtio_gpu_transfer_to_host_2d t2d;
221 struct virtio_gpu_box box;
222
223 VIRTIO_GPU_FILL_CMD(t2d);
224 trace_virtio_gpu_cmd_res_xfer_toh_2d(t2d.resource_id);
225
226 box.x = t2d.r.x;
227 box.y = t2d.r.y;
228 box.z = 0;
229 box.w = t2d.r.width;
230 box.h = t2d.r.height;
231 box.d = 1;
232
233 virgl_renderer_transfer_write_iov(t2d.resource_id,
234 0,
235 0,
236 0,
237 0,
238 (struct virgl_box *)&box,
239 t2d.offset, NULL, 0);
240}
241
242static void virgl_cmd_transfer_to_host_3d(VirtIOGPU *g,
243 struct virtio_gpu_ctrl_command *cmd)
244{
245 struct virtio_gpu_transfer_host_3d t3d;
246
247 VIRTIO_GPU_FILL_CMD(t3d);
248 trace_virtio_gpu_cmd_res_xfer_toh_3d(t3d.resource_id);
249
250 virgl_renderer_transfer_write_iov(t3d.resource_id,
251 t3d.hdr.ctx_id,
252 t3d.level,
253 t3d.stride,
254 t3d.layer_stride,
255 (struct virgl_box *)&t3d.box,
256 t3d.offset, NULL, 0);
257}
258
259static void
260virgl_cmd_transfer_from_host_3d(VirtIOGPU *g,
261 struct virtio_gpu_ctrl_command *cmd)
262{
263 struct virtio_gpu_transfer_host_3d tf3d;
264
265 VIRTIO_GPU_FILL_CMD(tf3d);
266 trace_virtio_gpu_cmd_res_xfer_fromh_3d(tf3d.resource_id);
267
268 virgl_renderer_transfer_read_iov(tf3d.resource_id,
269 tf3d.hdr.ctx_id,
270 tf3d.level,
271 tf3d.stride,
272 tf3d.layer_stride,
273 (struct virgl_box *)&tf3d.box,
274 tf3d.offset, NULL, 0);
275}
276
277
278static void virgl_resource_attach_backing(VirtIOGPU *g,
279 struct virtio_gpu_ctrl_command *cmd)
280{
281 struct virtio_gpu_resource_attach_backing att_rb;
282 struct iovec *res_iovs;
283 int ret;
284
285 VIRTIO_GPU_FILL_CMD(att_rb);
286 trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id);
287
0c244e50 288 ret = virtio_gpu_create_mapping_iov(&att_rb, cmd, NULL, &res_iovs);
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289 if (ret != 0) {
290 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
291 return;
292 }
293
294 virgl_renderer_resource_attach_iov(att_rb.resource_id,
295 res_iovs, att_rb.nr_entries);
296}
297
298static void virgl_resource_detach_backing(VirtIOGPU *g,
299 struct virtio_gpu_ctrl_command *cmd)
300{
301 struct virtio_gpu_resource_detach_backing detach_rb;
302 struct iovec *res_iovs = NULL;
303 int num_iovs = 0;
304
305 VIRTIO_GPU_FILL_CMD(detach_rb);
306 trace_virtio_gpu_cmd_res_back_detach(detach_rb.resource_id);
307
308 virgl_renderer_resource_detach_iov(detach_rb.resource_id,
309 &res_iovs,
310 &num_iovs);
311 if (res_iovs == NULL || num_iovs == 0) {
312 return;
313 }
314 virtio_gpu_cleanup_mapping_iov(res_iovs, num_iovs);
315}
316
317
318static void virgl_cmd_ctx_attach_resource(VirtIOGPU *g,
319 struct virtio_gpu_ctrl_command *cmd)
320{
321 struct virtio_gpu_ctx_resource att_res;
322
323 VIRTIO_GPU_FILL_CMD(att_res);
324 trace_virtio_gpu_cmd_ctx_res_attach(att_res.hdr.ctx_id,
325 att_res.resource_id);
326
327 virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id);
328}
329
330static void virgl_cmd_ctx_detach_resource(VirtIOGPU *g,
331 struct virtio_gpu_ctrl_command *cmd)
332{
333 struct virtio_gpu_ctx_resource det_res;
334
335 VIRTIO_GPU_FILL_CMD(det_res);
336 trace_virtio_gpu_cmd_ctx_res_detach(det_res.hdr.ctx_id,
337 det_res.resource_id);
338
339 virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id);
340}
341
342static void virgl_cmd_get_capset_info(VirtIOGPU *g,
343 struct virtio_gpu_ctrl_command *cmd)
344{
345 struct virtio_gpu_get_capset_info info;
346 struct virtio_gpu_resp_capset_info resp;
347
348 VIRTIO_GPU_FILL_CMD(info);
349
350 if (info.capset_index == 0) {
351 resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL;
352 virgl_renderer_get_cap_set(resp.capset_id,
353 &resp.capset_max_version,
354 &resp.capset_max_size);
355 } else {
356 resp.capset_max_version = 0;
357 resp.capset_max_size = 0;
358 }
359 resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO;
360 virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp));
361}
362
363static void virgl_cmd_get_capset(VirtIOGPU *g,
364 struct virtio_gpu_ctrl_command *cmd)
365{
366 struct virtio_gpu_get_capset gc;
367 struct virtio_gpu_resp_capset *resp;
368 uint32_t max_ver, max_size;
369 VIRTIO_GPU_FILL_CMD(gc);
370
371 virgl_renderer_get_cap_set(gc.capset_id, &max_ver,
372 &max_size);
373 resp = g_malloc(sizeof(*resp) + max_size);
374
375 resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET;
376 virgl_renderer_fill_caps(gc.capset_id,
377 gc.capset_version,
378 (void *)resp->capset_data);
379 virtio_gpu_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size);
380 g_free(resp);
381}
382
383void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
384 struct virtio_gpu_ctrl_command *cmd)
385{
386 VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr);
387
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388 cmd->waiting = g->renderer_blocked;
389 if (cmd->waiting) {
390 return;
391 }
392
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393 virgl_renderer_force_ctx_0();
394 switch (cmd->cmd_hdr.type) {
395 case VIRTIO_GPU_CMD_CTX_CREATE:
396 virgl_cmd_context_create(g, cmd);
397 break;
398 case VIRTIO_GPU_CMD_CTX_DESTROY:
399 virgl_cmd_context_destroy(g, cmd);
400 break;
401 case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
402 virgl_cmd_create_resource_2d(g, cmd);
403 break;
404 case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D:
405 virgl_cmd_create_resource_3d(g, cmd);
406 break;
407 case VIRTIO_GPU_CMD_SUBMIT_3D:
408 virgl_cmd_submit_3d(g, cmd);
409 break;
410 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
411 virgl_cmd_transfer_to_host_2d(g, cmd);
412 break;
413 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D:
414 virgl_cmd_transfer_to_host_3d(g, cmd);
415 break;
416 case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D:
417 virgl_cmd_transfer_from_host_3d(g, cmd);
418 break;
419 case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
420 virgl_resource_attach_backing(g, cmd);
421 break;
422 case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
423 virgl_resource_detach_backing(g, cmd);
424 break;
425 case VIRTIO_GPU_CMD_SET_SCANOUT:
426 virgl_cmd_set_scanout(g, cmd);
427 break;
428 case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
429 virgl_cmd_resource_flush(g, cmd);
430 break;
431 case VIRTIO_GPU_CMD_RESOURCE_UNREF:
432 virgl_cmd_resource_unref(g, cmd);
433 break;
434 case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE:
435 /* TODO add security */
436 virgl_cmd_ctx_attach_resource(g, cmd);
437 break;
438 case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE:
439 /* TODO add security */
440 virgl_cmd_ctx_detach_resource(g, cmd);
441 break;
442 case VIRTIO_GPU_CMD_GET_CAPSET_INFO:
443 virgl_cmd_get_capset_info(g, cmd);
444 break;
445 case VIRTIO_GPU_CMD_GET_CAPSET:
446 virgl_cmd_get_capset(g, cmd);
447 break;
448
449 case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
450 virtio_gpu_get_display_info(g, cmd);
451 break;
452 default:
453 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
454 break;
455 }
456
457 if (cmd->finished) {
458 return;
459 }
460 if (cmd->error) {
461 fprintf(stderr, "%s: ctrl 0x%x, error 0x%x\n", __func__,
462 cmd->cmd_hdr.type, cmd->error);
463 virtio_gpu_ctrl_response_nodata(g, cmd, cmd->error);
464 return;
465 }
466 if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) {
467 virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
468 return;
469 }
470
471 trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
472 virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
473}
474
475static void virgl_write_fence(void *opaque, uint32_t fence)
476{
477 VirtIOGPU *g = opaque;
478 struct virtio_gpu_ctrl_command *cmd, *tmp;
479
480 QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
481 /*
482 * the guest can end up emitting fences out of order
483 * so we should check all fenced cmds not just the first one.
484 */
485 if (cmd->cmd_hdr.fence_id > fence) {
486 continue;
487 }
488 trace_virtio_gpu_fence_resp(cmd->cmd_hdr.fence_id);
489 virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
490 QTAILQ_REMOVE(&g->fenceq, cmd, next);
491 g_free(cmd);
492 g->inflight--;
493 if (virtio_gpu_stats_enabled(g->conf)) {
494 fprintf(stderr, "inflight: %3d (-)\r", g->inflight);
495 }
496 }
497}
498
499static virgl_renderer_gl_context
500virgl_create_context(void *opaque, int scanout_idx,
501 struct virgl_renderer_gl_ctx_param *params)
502{
503 VirtIOGPU *g = opaque;
504 QEMUGLContext ctx;
505 QEMUGLParams qparams;
506
507 qparams.major_ver = params->major_ver;
508 qparams.minor_ver = params->minor_ver;
509
510 ctx = dpy_gl_ctx_create(g->scanout[scanout_idx].con, &qparams);
511 return (virgl_renderer_gl_context)ctx;
512}
513
514static void virgl_destroy_context(void *opaque, virgl_renderer_gl_context ctx)
515{
516 VirtIOGPU *g = opaque;
517 QEMUGLContext qctx = (QEMUGLContext)ctx;
518
519 dpy_gl_ctx_destroy(g->scanout[0].con, qctx);
520}
521
522static int virgl_make_context_current(void *opaque, int scanout_idx,
523 virgl_renderer_gl_context ctx)
524{
525 VirtIOGPU *g = opaque;
526 QEMUGLContext qctx = (QEMUGLContext)ctx;
527
528 return dpy_gl_ctx_make_current(g->scanout[scanout_idx].con, qctx);
529}
530
531static struct virgl_renderer_callbacks virtio_gpu_3d_cbs = {
532 .version = 1,
533 .write_fence = virgl_write_fence,
534 .create_gl_context = virgl_create_context,
535 .destroy_gl_context = virgl_destroy_context,
536 .make_current = virgl_make_context_current,
537};
538
539static void virtio_gpu_print_stats(void *opaque)
540{
541 VirtIOGPU *g = opaque;
542
543 if (g->stats.requests) {
544 fprintf(stderr, "stats: vq req %4d, %3d -- 3D %4d (%5d)\n",
545 g->stats.requests,
546 g->stats.max_inflight,
547 g->stats.req_3d,
548 g->stats.bytes_3d);
549 g->stats.requests = 0;
550 g->stats.max_inflight = 0;
551 g->stats.req_3d = 0;
552 g->stats.bytes_3d = 0;
553 } else {
554 fprintf(stderr, "stats: idle\r");
555 }
556 timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
557}
558
559static void virtio_gpu_fence_poll(void *opaque)
560{
561 VirtIOGPU *g = opaque;
562
563 virgl_renderer_poll();
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564 virtio_gpu_process_cmdq(g);
565 if (!QTAILQ_EMPTY(&g->cmdq) || !QTAILQ_EMPTY(&g->fenceq)) {
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566 timer_mod(g->fence_poll, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 10);
567 }
568}
569
570void virtio_gpu_virgl_fence_poll(VirtIOGPU *g)
571{
572 virtio_gpu_fence_poll(g);
573}
574
575void virtio_gpu_virgl_reset(VirtIOGPU *g)
576{
577 int i;
578
579 /* virgl_renderer_reset() ??? */
580 for (i = 0; i < g->conf.max_outputs; i++) {
581 if (i != 0) {
582 dpy_gfx_replace_surface(g->scanout[i].con, NULL);
583 }
9d8256eb 584 dpy_gl_scanout(g->scanout[i].con, 0, false, 0, 0, 0, 0, 0, 0);
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585 }
586}
587
588int virtio_gpu_virgl_init(VirtIOGPU *g)
589{
590 int ret;
591
592 ret = virgl_renderer_init(g, 0, &virtio_gpu_3d_cbs);
593 if (ret != 0) {
594 return ret;
595 }
596
597 g->fence_poll = timer_new_ms(QEMU_CLOCK_VIRTUAL,
598 virtio_gpu_fence_poll, g);
599
600 if (virtio_gpu_stats_enabled(g->conf)) {
601 g->print_stats = timer_new_ms(QEMU_CLOCK_VIRTUAL,
602 virtio_gpu_print_stats, g);
603 timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
604 }
605 return 0;
606}
607
608#endif /* CONFIG_VIRGL */