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error: Eliminate error_propagate() with Coccinelle, part 1
[mirror_qemu.git] / hw / display / virtio-vga.c
CommitLineData
9b8bfe21 1#include "qemu/osdep.h"
c5d4dac8 2#include "hw/pci/pci.h"
a27bd6c7 3#include "hw/qdev-properties.h"
7ecb381f 4#include "hw/virtio/virtio-gpu.h"
d0f0c865 5#include "qapi/error.h"
0b8fa32f 6#include "qemu/module.h"
c68082c4 7#include "virtio-vga.h"
c5d4dac8 8
c68082c4 9static void virtio_vga_base_invalidate_display(void *opaque)
c5d4dac8 10{
c68082c4
MAL
11 VirtIOVGABase *vvga = opaque;
12 VirtIOGPUBase *g = vvga->vgpu;
c5d4dac8 13
50d8e25e 14 if (g->enable) {
c68082c4 15 virtio_gpu_ops.invalidate(g);
c5d4dac8
GH
16 } else {
17 vvga->vga.hw_ops->invalidate(&vvga->vga);
18 }
19}
20
c68082c4 21static void virtio_vga_base_update_display(void *opaque)
c5d4dac8 22{
c68082c4
MAL
23 VirtIOVGABase *vvga = opaque;
24 VirtIOGPUBase *g = vvga->vgpu;
c5d4dac8 25
50d8e25e 26 if (g->enable) {
c68082c4 27 virtio_gpu_ops.gfx_update(g);
c5d4dac8
GH
28 } else {
29 vvga->vga.hw_ops->gfx_update(&vvga->vga);
30 }
31}
32
c68082c4 33static void virtio_vga_base_text_update(void *opaque, console_ch_t *chardata)
c5d4dac8 34{
c68082c4
MAL
35 VirtIOVGABase *vvga = opaque;
36 VirtIOGPUBase *g = vvga->vgpu;
c5d4dac8 37
50d8e25e 38 if (g->enable) {
c5d4dac8 39 if (virtio_gpu_ops.text_update) {
c68082c4 40 virtio_gpu_ops.text_update(g, chardata);
c5d4dac8
GH
41 }
42 } else {
43 if (vvga->vga.hw_ops->text_update) {
44 vvga->vga.hw_ops->text_update(&vvga->vga, chardata);
45 }
46 }
47}
48
c68082c4 49static int virtio_vga_base_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info)
c5d4dac8 50{
c68082c4
MAL
51 VirtIOVGABase *vvga = opaque;
52 VirtIOGPUBase *g = vvga->vgpu;
c5d4dac8
GH
53
54 if (virtio_gpu_ops.ui_info) {
c68082c4 55 return virtio_gpu_ops.ui_info(g, idx, info);
c5d4dac8
GH
56 }
57 return -1;
58}
59
c68082c4 60static void virtio_vga_base_gl_block(void *opaque, bool block)
321c9adb 61{
c68082c4
MAL
62 VirtIOVGABase *vvga = opaque;
63 VirtIOGPUBase *g = vvga->vgpu;
321c9adb
GH
64
65 if (virtio_gpu_ops.gl_block) {
c68082c4 66 virtio_gpu_ops.gl_block(g, block);
321c9adb
GH
67 }
68}
69
c68082c4
MAL
70static const GraphicHwOps virtio_vga_base_ops = {
71 .invalidate = virtio_vga_base_invalidate_display,
72 .gfx_update = virtio_vga_base_update_display,
73 .text_update = virtio_vga_base_text_update,
74 .ui_info = virtio_vga_base_ui_info,
75 .gl_block = virtio_vga_base_gl_block,
c5d4dac8
GH
76};
77
c68082c4 78static const VMStateDescription vmstate_virtio_vga_base = {
0c244e50
GH
79 .name = "virtio-vga",
80 .version_id = 2,
81 .minimum_version_id = 2,
82 .fields = (VMStateField[]) {
83 /* no pci stuff here, saving the virtio device will handle that */
c68082c4
MAL
84 VMSTATE_STRUCT(vga, VirtIOVGABase, 0,
85 vmstate_vga_common, VGACommonState),
0c244e50
GH
86 VMSTATE_END_OF_LIST()
87 }
88};
89
c5d4dac8 90/* VGA device wrapper around PCI device around virtio GPU */
c68082c4 91static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
c5d4dac8 92{
c68082c4
MAL
93 VirtIOVGABase *vvga = VIRTIO_VGA_BASE(vpci_dev);
94 VirtIOGPUBase *g = vvga->vgpu;
c5d4dac8
GH
95 VGACommonState *vga = &vvga->vga;
96 uint32_t offset;
e1888295 97 int i;
c5d4dac8
GH
98
99 /* init vga compat bits */
100 vga->vram_size_mb = 8;
1fcfdc43 101 vga_common_init(vga, OBJECT(vpci_dev));
c5d4dac8
GH
102 vga_init(vga, OBJECT(vpci_dev), pci_address_space(&vpci_dev->pci_dev),
103 pci_address_space_io(&vpci_dev->pci_dev), true);
104 pci_register_bar(&vpci_dev->pci_dev, 0,
105 PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram);
106
107 /*
108 * Configure virtio bar and regions
109 *
110 * We use bar #2 for the mmio regions, to be compatible with stdvga.
111 * virtio regions are moved to the end of bar #2, to make room for
112 * the stdvga mmio registers at the start of bar #2.
113 */
7a25126d
CF
114 vpci_dev->modern_mem_bar_idx = 2;
115 vpci_dev->msix_bar_idx = 4;
15138b5e 116 vpci_dev->modern_io_bar_idx = 5;
c2843e93
GH
117
118 if (!(vpci_dev->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ)) {
119 /*
120 * with page-per-vq=off there is no padding space we can use
121 * for the stdvga registers. Make the common and isr regions
122 * smaller then.
123 */
124 vpci_dev->common.size /= 2;
125 vpci_dev->isr.size /= 2;
126 }
127
c5d4dac8
GH
128 offset = memory_region_size(&vpci_dev->modern_bar);
129 offset -= vpci_dev->notify.size;
130 vpci_dev->notify.offset = offset;
131 offset -= vpci_dev->device.size;
132 vpci_dev->device.offset = offset;
133 offset -= vpci_dev->isr.size;
134 vpci_dev->isr.offset = offset;
135 offset -= vpci_dev->common.size;
136 vpci_dev->common.offset = offset;
137
138 /* init virtio bits */
dd56040d 139 virtio_pci_force_virtio_1(vpci_dev);
668f62ec 140 if (!qdev_realize(DEVICE(g), BUS(&vpci_dev->bus), errp)) {
d0f0c865
MAL
141 return;
142 }
c5d4dac8
GH
143
144 /* add stdvga mmio regions */
93abfc88 145 pci_std_vga_mmio_region_init(vga, OBJECT(vvga), &vpci_dev->modern_bar,
d46b40fc 146 vvga->vga_mrs, true, false);
c5d4dac8
GH
147
148 vga->con = g->scanout[0].con;
c68082c4 149 graphic_console_set_hwops(vga->con, &virtio_vga_base_ops, vvga);
e1888295
GH
150
151 for (i = 0; i < g->conf.max_outputs; i++) {
5325cc34
MA
152 object_property_set_link(OBJECT(g->scanout[i].con), "device",
153 OBJECT(vpci_dev), &error_abort);
e1888295 154 }
c5d4dac8
GH
155}
156
c68082c4 157static void virtio_vga_base_reset(DeviceState *dev)
c5d4dac8 158{
c68082c4
MAL
159 VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(dev);
160 VirtIOVGABase *vvga = VIRTIO_VGA_BASE(dev);
c5d4dac8 161
43e4dbe2 162 /* reset virtio-gpu */
3912e66a 163 klass->parent_reset(dev);
43e4dbe2
GH
164
165 /* reset vga */
166 vga_common_reset(&vvga->vga);
c5d4dac8
GH
167 vga_dirty_log_start(&vvga->vga);
168}
169
c68082c4 170static Property virtio_vga_base_properties[] = {
c5d4dac8
GH
171 DEFINE_VIRTIO_GPU_PCI_PROPERTIES(VirtIOPCIProxy),
172 DEFINE_PROP_END_OF_LIST(),
173};
174
c68082c4 175static void virtio_vga_base_class_init(ObjectClass *klass, void *data)
c5d4dac8
GH
176{
177 DeviceClass *dc = DEVICE_CLASS(klass);
178 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
c68082c4 179 VirtIOVGABaseClass *v = VIRTIO_VGA_BASE_CLASS(klass);
c5d4dac8
GH
180 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
181
182 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
4f67d30b 183 device_class_set_props(dc, virtio_vga_base_properties);
c68082c4 184 dc->vmsd = &vmstate_virtio_vga_base;
c5d4dac8 185 dc->hotpluggable = false;
c68082c4 186 device_class_set_parent_reset(dc, virtio_vga_base_reset,
3912e66a 187 &v->parent_reset);
c5d4dac8 188
c68082c4 189 k->realize = virtio_vga_base_realize;
c5d4dac8
GH
190 pcidev_k->romfile = "vgabios-virtio.bin";
191 pcidev_k->class_id = PCI_CLASS_DISPLAY_VGA;
192}
193
c68082c4
MAL
194static TypeInfo virtio_vga_base_info = {
195 .name = TYPE_VIRTIO_VGA_BASE,
196 .parent = TYPE_VIRTIO_PCI,
197 .instance_size = sizeof(struct VirtIOVGABase),
198 .class_size = sizeof(struct VirtIOVGABaseClass),
199 .class_init = virtio_vga_base_class_init,
200 .abstract = true,
201};
202
203#define TYPE_VIRTIO_VGA "virtio-vga"
204
205#define VIRTIO_VGA(obj) \
206 OBJECT_CHECK(VirtIOVGA, (obj), TYPE_VIRTIO_VGA)
207
208typedef struct VirtIOVGA {
209 VirtIOVGABase parent_obj;
210
211 VirtIOGPU vdev;
212} VirtIOVGA;
213
c5d4dac8
GH
214static void virtio_vga_inst_initfn(Object *obj)
215{
216 VirtIOVGA *dev = VIRTIO_VGA(obj);
b3409a31
GH
217
218 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
219 TYPE_VIRTIO_GPU);
c68082c4 220 VIRTIO_VGA_BASE(dev)->vgpu = VIRTIO_GPU_BASE(&dev->vdev);
c5d4dac8
GH
221}
222
c68082c4 223
a4ee4c8b
EH
224static VirtioPCIDeviceTypeInfo virtio_vga_info = {
225 .generic_name = TYPE_VIRTIO_VGA,
c68082c4 226 .parent = TYPE_VIRTIO_VGA_BASE,
c5d4dac8
GH
227 .instance_size = sizeof(struct VirtIOVGA),
228 .instance_init = virtio_vga_inst_initfn,
c5d4dac8
GH
229};
230
231static void virtio_vga_register_types(void)
232{
c68082c4 233 type_register_static(&virtio_vga_base_info);
a4ee4c8b 234 virtio_pci_types_register(&virtio_vga_info);
c5d4dac8
GH
235}
236
237type_init(virtio_vga_register_types)