[mirror_qemu.git] / hw / eccmemctl.c

/*
 * QEMU Sparc Sun4m ECC memory controller emulation
 *
 * Copyright (c) 2007 Robert Reif
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "trace.h"

/* There are 3 versions of this chip used in SMP sun4m systems:
 * MCC (version 0, implementation 0) SS-600MP
 * EMC (version 0, implementation 1) SS-10
 * SMC (version 0, implementation 2) SS-10SX and SS-20
 *
 * Chipset docs:
 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
 */

#define ECC_MCC        0x00000000
#define ECC_EMC        0x10000000
#define ECC_SMC        0x20000000

/* Register indexes */
#define ECC_MER        0               /* Memory Enable Register */
#define ECC_MDR        1               /* Memory Delay Register */
#define ECC_MFSR       2               /* Memory Fault Status Register */
#define ECC_VCR        3               /* Video Configuration Register */
#define ECC_MFAR0      4               /* Memory Fault Address Register 0 */
#define ECC_MFAR1      5               /* Memory Fault Address Register 1 */
#define ECC_DR         6               /* Diagnostic Register */
#define ECC_ECR0       7               /* Event Count Register 0 */
#define ECC_ECR1       8               /* Event Count Register 1 */

/* ECC fault control register */
#define ECC_MER_EE     0x00000001      /* Enable ECC checking */
#define ECC_MER_EI     0x00000002      /* Enable Interrupts on
                                          correctable errors */
#define ECC_MER_MRR0   0x00000004      /* SIMM 0 */
#define ECC_MER_MRR1   0x00000008      /* SIMM 1 */
#define ECC_MER_MRR2   0x00000010      /* SIMM 2 */
#define ECC_MER_MRR3   0x00000020      /* SIMM 3 */
#define ECC_MER_MRR4   0x00000040      /* SIMM 4 */
#define ECC_MER_MRR5   0x00000080      /* SIMM 5 */
#define ECC_MER_MRR6   0x00000100      /* SIMM 6 */
#define ECC_MER_MRR7   0x00000200      /* SIMM 7 */
#define ECC_MER_REU    0x00000100      /* Memory Refresh Enable (600MP) */
#define ECC_MER_MRR    0x000003fc      /* MRR mask */
#define ECC_MER_A      0x00000400      /* Memory controller addr map select */
#define ECC_MER_DCI    0x00000800      /* Disables Coherent Invalidate ACK */
#define ECC_MER_VER    0x0f000000      /* Version */
#define ECC_MER_IMPL   0xf0000000      /* Implementation */
#define ECC_MER_MASK_0 0x00000103      /* Version 0 (MCC) mask */
#define ECC_MER_MASK_1 0x00000bff      /* Version 1 (EMC) mask */
#define ECC_MER_MASK_2 0x00000bff      /* Version 2 (SMC) mask */

/* ECC memory delay register */
#define ECC_MDR_RRI    0x000003ff      /* Refresh Request Interval */
#define ECC_MDR_MI     0x00001c00      /* MIH Delay */
#define ECC_MDR_CI     0x0000e000      /* Coherent Invalidate Delay */
#define ECC_MDR_MDL    0x001f0000      /* MBus Master arbitration delay */
#define ECC_MDR_MDH    0x03e00000      /* MBus Master arbitration delay */
#define ECC_MDR_GAD    0x7c000000      /* Graphics Arbitration Delay */
#define ECC_MDR_RSC    0x80000000      /* Refresh load control */
#define ECC_MDR_MASK   0x7fffffff

/* ECC fault status register */
#define ECC_MFSR_CE    0x00000001      /* Correctable error */
#define ECC_MFSR_BS    0x00000002      /* C2 graphics bad slot access */
#define ECC_MFSR_TO    0x00000004      /* Timeout on write */
#define ECC_MFSR_UE    0x00000008      /* Uncorrectable error */
#define ECC_MFSR_DW    0x000000f0      /* Index of double word in block */
#define ECC_MFSR_SYND  0x0000ff00      /* Syndrome for correctable error */
#define ECC_MFSR_ME    0x00010000      /* Multiple errors */
#define ECC_MFSR_C2ERR 0x00020000      /* C2 graphics error */

/* ECC fault address register 0 */
#define ECC_MFAR0_PADDR 0x0000000f     /* PA[32-35] */
#define ECC_MFAR0_TYPE  0x000000f0     /* Transaction type */
#define ECC_MFAR0_SIZE  0x00000700     /* Transaction size */
#define ECC_MFAR0_CACHE 0x00000800     /* Mapped cacheable */
#define ECC_MFAR0_LOCK  0x00001000     /* Error occurred in atomic cycle */
#define ECC_MFAR0_BMODE 0x00002000     /* Boot mode */
#define ECC_MFAR0_VADDR 0x003fc000     /* VA[12-19] (superset bits) */
#define ECC_MFAR0_S     0x08000000     /* Supervisor mode */
#define ECC_MFARO_MID   0xf0000000     /* Module ID */

/* ECC diagnostic register */
#define ECC_DR_CBX     0x00000001
#define ECC_DR_CB0     0x00000002
#define ECC_DR_CB1     0x00000004
#define ECC_DR_CB2     0x00000008
#define ECC_DR_CB4     0x00000010
#define ECC_DR_CB8     0x00000020
#define ECC_DR_CB16    0x00000040
#define ECC_DR_CB32    0x00000080
#define ECC_DR_DMODE   0x00000c00

#define ECC_NREGS      9
#define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))

#define ECC_DIAG_SIZE  4
#define ECC_DIAG_MASK  (ECC_DIAG_SIZE - 1)

typedef struct ECCState {
    SysBusDevice busdev;
    MemoryRegion iomem, iomem_diag;
    qemu_irq irq;
    uint32_t regs[ECC_NREGS];
    uint8_t diag[ECC_DIAG_SIZE];
    uint32_t version;
} ECCState;

static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val,
                          unsigned size)
{
    ECCState *s = opaque;

    switch (addr >> 2) {
    case ECC_MER:
        if (s->version == ECC_MCC)
            s->regs[ECC_MER] = (val & ECC_MER_MASK_0);
        else if (s->version == ECC_EMC)
            s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1);
        else if (s->version == ECC_SMC)
            s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2);
        trace_ecc_mem_writel_mer(val);
        break;
    case ECC_MDR:
        s->regs[ECC_MDR] =  val & ECC_MDR_MASK;
        trace_ecc_mem_writel_mdr(val);
        break;
    case ECC_MFSR:
        s->regs[ECC_MFSR] =  val;
        qemu_irq_lower(s->irq);
        trace_ecc_mem_writel_mfsr(val);
        break;
    case ECC_VCR:
        s->regs[ECC_VCR] =  val;
        trace_ecc_mem_writel_vcr(val);
        break;
    case ECC_DR:
        s->regs[ECC_DR] =  val;
        trace_ecc_mem_writel_dr(val);
        break;
    case ECC_ECR0:
        s->regs[ECC_ECR0] =  val;
        trace_ecc_mem_writel_ecr0(val);
        break;
    case ECC_ECR1:
        s->regs[ECC_ECR0] =  val;
        trace_ecc_mem_writel_ecr1(val);
        break;
    }
}

static uint64_t ecc_mem_read(void *opaque, hwaddr addr,
                             unsigned size)
{
    ECCState *s = opaque;
    uint32_t ret = 0;

    switch (addr >> 2) {
    case ECC_MER:
        ret = s->regs[ECC_MER];
        trace_ecc_mem_readl_mer(ret);
        break;
    case ECC_MDR:
        ret = s->regs[ECC_MDR];
        trace_ecc_mem_readl_mdr(ret);
        break;
    case ECC_MFSR:
        ret = s->regs[ECC_MFSR];
        trace_ecc_mem_readl_mfsr(ret);
        break;
    case ECC_VCR:
        ret = s->regs[ECC_VCR];
        trace_ecc_mem_readl_vcr(ret);
        break;
    case ECC_MFAR0:
        ret = s->regs[ECC_MFAR0];
        trace_ecc_mem_readl_mfar0(ret);
        break;
    case ECC_MFAR1:
        ret = s->regs[ECC_MFAR1];
        trace_ecc_mem_readl_mfar1(ret);
        break;
    case ECC_DR:
        ret = s->regs[ECC_DR];
        trace_ecc_mem_readl_dr(ret);
        break;
    case ECC_ECR0:
        ret = s->regs[ECC_ECR0];
        trace_ecc_mem_readl_ecr0(ret);
        break;
    case ECC_ECR1:
        ret = s->regs[ECC_ECR0];
        trace_ecc_mem_readl_ecr1(ret);
        break;
    }
    return ret;
}

static const MemoryRegionOps ecc_mem_ops = {
    .read = ecc_mem_read,
    .write = ecc_mem_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void ecc_diag_mem_write(void *opaque, hwaddr addr,
                               uint64_t val, unsigned size)
{
    ECCState *s = opaque;

    trace_ecc_diag_mem_writeb(addr, val);
    s->diag[addr & ECC_DIAG_MASK] = val;
}

static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr,
                                  unsigned size)
{
    ECCState *s = opaque;
    uint32_t ret = s->diag[(int)addr];

    trace_ecc_diag_mem_readb(addr, ret);
    return ret;
}

static const MemoryRegionOps ecc_diag_mem_ops = {
    .read = ecc_diag_mem_read,
    .write = ecc_diag_mem_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
};

static const VMStateDescription vmstate_ecc = {
    .name ="ECC",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 3,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS),
        VMSTATE_BUFFER(diag, ECCState),
        VMSTATE_UINT32(version, ECCState),
        VMSTATE_END_OF_LIST()
    }
};

static void ecc_reset(DeviceState *d)
{
    ECCState *s = container_of(d, ECCState, busdev.qdev);

    if (s->version == ECC_MCC)
        s->regs[ECC_MER] &= ECC_MER_REU;
    else
        s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR |
                             ECC_MER_DCI);
    s->regs[ECC_MDR] = 0x20;
    s->regs[ECC_MFSR] = 0;
    s->regs[ECC_VCR] = 0;
    s->regs[ECC_MFAR0] = 0x07c00000;
    s->regs[ECC_MFAR1] = 0;
    s->regs[ECC_DR] = 0;
    s->regs[ECC_ECR0] = 0;
    s->regs[ECC_ECR1] = 0;
}

static int ecc_init1(SysBusDevice *dev)
{
    ECCState *s = FROM_SYSBUS(ECCState, dev);

    sysbus_init_irq(dev, &s->irq);
    s->regs[0] = s->version;
    memory_region_init_io(&s->iomem, &ecc_mem_ops, s, "ecc", ECC_SIZE);
    sysbus_init_mmio(dev, &s->iomem);

    if (s->version == ECC_MCC) { // SS-600MP only
        memory_region_init_io(&s->iomem_diag, &ecc_diag_mem_ops, s,
                              "ecc.diag", ECC_DIAG_SIZE);
        sysbus_init_mmio(dev, &s->iomem_diag);
    }

    return 0;
}

static Property ecc_properties[] = {
    DEFINE_PROP_HEX32("version", ECCState, version, -1),
    DEFINE_PROP_END_OF_LIST(),
};

static void ecc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = ecc_init1;
    dc->reset = ecc_reset;
    dc->vmsd = &vmstate_ecc;
    dc->props = ecc_properties;
}

static TypeInfo ecc_info = {
    .name          = "eccmemctl",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(ECCState),
    .class_init    = ecc_class_init,
};


static void ecc_register_types(void)
{
    type_register_static(&ecc_info);
}

type_init(ecc_register_types)
Commit	Line	Data
7eb0c8e8 BS	1	/*
	2	* QEMU Sparc Sun4m ECC memory controller emulation
	3	*
	4	* Copyright (c) 2007 Robert Reif
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
49e66373	24
49e66373	25	#include "sysbus.h"
97bf4851	26	#include "trace.h"
7eb0c8e8 BS	27
	28	/* There are 3 versions of this chip used in SMP sun4m systems:
	29	* MCC (version 0, implementation 0) SS-600MP
	30	* EMC (version 0, implementation 1) SS-10
	31	* SMC (version 0, implementation 2) SS-10SX and SS-20
5ac574c4 BS	32	*
	33	* Chipset docs:
	34	* "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
	35	* http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
7eb0c8e8 BS	36	*/
7eb0c8e8 BS	37
0bb3602c BS	38	#define ECC_MCC 0x00000000
	39	#define ECC_EMC 0x10000000
	40	#define ECC_SMC 0x20000000
	41
8f2ad0a3 BS	42	/* Register indexes */
	43	#define ECC_MER 0 /* Memory Enable Register */
	44	#define ECC_MDR 1 /* Memory Delay Register */
	45	#define ECC_MFSR 2 /* Memory Fault Status Register */
	46	#define ECC_VCR 3 /* Video Configuration Register */
	47	#define ECC_MFAR0 4 /* Memory Fault Address Register 0 */
	48	#define ECC_MFAR1 5 /* Memory Fault Address Register 1 */
	49	#define ECC_DR 6 /* Diagnostic Register */
	50	#define ECC_ECR0 7 /* Event Count Register 0 */
	51	#define ECC_ECR1 8 /* Event Count Register 1 */
7eb0c8e8 BS	52
7eb0c8e8 BS	53	/* ECC fault control register */
dd53ded3	54	#define ECC_MER_EE 0x00000001 /* Enable ECC checking */
77f193da BS	55	#define ECC_MER_EI 0x00000002 /* Enable Interrupts on
77f193da BS	56	correctable errors */
dd53ded3 BS	57	#define ECC_MER_MRR0 0x00000004 /* SIMM 0 */
	58	#define ECC_MER_MRR1 0x00000008 /* SIMM 1 */
	59	#define ECC_MER_MRR2 0x00000010 /* SIMM 2 */
	60	#define ECC_MER_MRR3 0x00000020 /* SIMM 3 */
	61	#define ECC_MER_MRR4 0x00000040 /* SIMM 4 */
	62	#define ECC_MER_MRR5 0x00000080 /* SIMM 5 */
	63	#define ECC_MER_MRR6 0x00000100 /* SIMM 6 */
	64	#define ECC_MER_MRR7 0x00000200 /* SIMM 7 */
0bb3602c	65	#define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */
dd53ded3	66	#define ECC_MER_MRR 0x000003fc /* MRR mask */
0bb3602c	67	#define ECC_MER_A 0x00000400 /* Memory controller addr map select */
77f193da	68	#define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */
dd53ded3 BS	69	#define ECC_MER_VER 0x0f000000 /* Version */
dd53ded3 BS	70	#define ECC_MER_IMPL 0xf0000000 /* Implementation */
0bb3602c BS	71	#define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */
	72	#define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */
	73	#define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */
dd53ded3 BS	74
	75	/* ECC memory delay register */
	76	#define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */
	77	#define ECC_MDR_MI 0x00001c00 /* MIH Delay */
	78	#define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */
	79	#define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */
	80	#define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */
	81	#define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */
	82	#define ECC_MDR_RSC 0x80000000 /* Refresh load control */
	83	#define ECC_MDR_MASK 0x7fffffff
7eb0c8e8 BS	84
7eb0c8e8 BS	85	/* ECC fault status register */
dd53ded3 BS	86	#define ECC_MFSR_CE 0x00000001 /* Correctable error */
	87	#define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */
	88	#define ECC_MFSR_TO 0x00000004 /* Timeout on write */
	89	#define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */
	90	#define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */
	91	#define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */
	92	#define ECC_MFSR_ME 0x00010000 /* Multiple errors */
	93	#define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */
7eb0c8e8 BS	94
7eb0c8e8 BS	95	/* ECC fault address register 0 */
dd53ded3 BS	96	#define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */
	97	#define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */
	98	#define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */
	99	#define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */
	100	#define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */
	101	#define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */
	102	#define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */
	103	#define ECC_MFAR0_S 0x08000000 /* Supervisor mode */
	104	#define ECC_MFARO_MID 0xf0000000 /* Module ID */
7eb0c8e8 BS	105
7eb0c8e8 BS	106	/* ECC diagnostic register */
dd53ded3 BS	107	#define ECC_DR_CBX 0x00000001
	108	#define ECC_DR_CB0 0x00000002
	109	#define ECC_DR_CB1 0x00000004
	110	#define ECC_DR_CB2 0x00000008
	111	#define ECC_DR_CB4 0x00000010
	112	#define ECC_DR_CB8 0x00000020
	113	#define ECC_DR_CB16 0x00000040
	114	#define ECC_DR_CB32 0x00000080
	115	#define ECC_DR_DMODE 0x00000c00
	116
	117	#define ECC_NREGS 9
7eb0c8e8	118	#define ECC_SIZE (ECC_NREGS * sizeof(uint32_t))
dd53ded3 BS	119
	120	#define ECC_DIAG_SIZE 4
	121	#define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1)
7eb0c8e8 BS	122
7eb0c8e8 BS	123	typedef struct ECCState {
49e66373	124	SysBusDevice busdev;
7ef57cca	125	MemoryRegion iomem, iomem_diag;
e42c20b4	126	qemu_irq irq;
7eb0c8e8	127	uint32_t regs[ECC_NREGS];
dd53ded3	128	uint8_t diag[ECC_DIAG_SIZE];
0bb3602c	129	uint32_t version;
7eb0c8e8 BS	130	} ECCState;
7eb0c8e8 BS	131
a8170e5e	132	static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val,
7ef57cca	133	unsigned size)
7eb0c8e8 BS	134	{
	135	ECCState *s = opaque;
	136
e64d7d59	137	switch (addr >> 2) {
dd53ded3	138	case ECC_MER:
0bb3602c BS	139	if (s->version == ECC_MCC)
	140	s->regs[ECC_MER] = (val & ECC_MER_MASK_0);
	141	else if (s->version == ECC_EMC)
	142	s->regs[ECC_MER] = s->version \| (val & ECC_MER_MASK_1);
	143	else if (s->version == ECC_SMC)
	144	s->regs[ECC_MER] = s->version \| (val & ECC_MER_MASK_2);
97bf4851	145	trace_ecc_mem_writel_mer(val);
7eb0c8e8	146	break;
dd53ded3	147	case ECC_MDR:
8f2ad0a3	148	s->regs[ECC_MDR] = val & ECC_MDR_MASK;
97bf4851	149	trace_ecc_mem_writel_mdr(val);
7eb0c8e8	150	break;
dd53ded3	151	case ECC_MFSR:
8f2ad0a3	152	s->regs[ECC_MFSR] = val;
0bb3602c	153	qemu_irq_lower(s->irq);
97bf4851	154	trace_ecc_mem_writel_mfsr(val);
7eb0c8e8	155	break;
dd53ded3	156	case ECC_VCR:
8f2ad0a3	157	s->regs[ECC_VCR] = val;
97bf4851	158	trace_ecc_mem_writel_vcr(val);
7eb0c8e8	159	break;
dd53ded3	160	case ECC_DR:
8f2ad0a3	161	s->regs[ECC_DR] = val;
97bf4851	162	trace_ecc_mem_writel_dr(val);
dd53ded3 BS	163	break;
dd53ded3 BS	164	case ECC_ECR0:
8f2ad0a3	165	s->regs[ECC_ECR0] = val;
97bf4851	166	trace_ecc_mem_writel_ecr0(val);
7eb0c8e8	167	break;
dd53ded3	168	case ECC_ECR1:
8f2ad0a3	169	s->regs[ECC_ECR0] = val;
97bf4851	170	trace_ecc_mem_writel_ecr1(val);
7eb0c8e8 BS	171	break;
	172	}
	173	}
	174
a8170e5e	175	static uint64_t ecc_mem_read(void *opaque, hwaddr addr,
7ef57cca	176	unsigned size)
7eb0c8e8 BS	177	{
	178	ECCState *s = opaque;
	179	uint32_t ret = 0;
	180
e64d7d59	181	switch (addr >> 2) {
dd53ded3	182	case ECC_MER:
8f2ad0a3	183	ret = s->regs[ECC_MER];
97bf4851	184	trace_ecc_mem_readl_mer(ret);
7eb0c8e8	185	break;
dd53ded3	186	case ECC_MDR:
8f2ad0a3	187	ret = s->regs[ECC_MDR];
97bf4851	188	trace_ecc_mem_readl_mdr(ret);
7eb0c8e8	189	break;
dd53ded3	190	case ECC_MFSR:
8f2ad0a3	191	ret = s->regs[ECC_MFSR];
97bf4851	192	trace_ecc_mem_readl_mfsr(ret);
7eb0c8e8	193	break;
dd53ded3	194	case ECC_VCR:
8f2ad0a3	195	ret = s->regs[ECC_VCR];
97bf4851	196	trace_ecc_mem_readl_vcr(ret);
7eb0c8e8	197	break;
dd53ded3	198	case ECC_MFAR0:
8f2ad0a3	199	ret = s->regs[ECC_MFAR0];
97bf4851	200	trace_ecc_mem_readl_mfar0(ret);
7eb0c8e8	201	break;
dd53ded3	202	case ECC_MFAR1:
8f2ad0a3	203	ret = s->regs[ECC_MFAR1];
97bf4851	204	trace_ecc_mem_readl_mfar1(ret);
7eb0c8e8	205	break;
dd53ded3	206	case ECC_DR:
8f2ad0a3	207	ret = s->regs[ECC_DR];
97bf4851	208	trace_ecc_mem_readl_dr(ret);
7eb0c8e8	209	break;
dd53ded3	210	case ECC_ECR0:
8f2ad0a3	211	ret = s->regs[ECC_ECR0];
97bf4851	212	trace_ecc_mem_readl_ecr0(ret);
dd53ded3 BS	213	break;
dd53ded3 BS	214	case ECC_ECR1:
8f2ad0a3	215	ret = s->regs[ECC_ECR0];
97bf4851	216	trace_ecc_mem_readl_ecr1(ret);
7eb0c8e8 BS	217	break;
	218	}
	219	return ret;
	220	}
	221
7ef57cca AK	222	static const MemoryRegionOps ecc_mem_ops = {
	223	.read = ecc_mem_read,
	224	.write = ecc_mem_write,
	225	.endianness = DEVICE_NATIVE_ENDIAN,
	226	.valid = {
	227	.min_access_size = 4,
	228	.max_access_size = 4,
	229	},
7eb0c8e8 BS	230	};
7eb0c8e8 BS	231
a8170e5e	232	static void ecc_diag_mem_write(void *opaque, hwaddr addr,
7ef57cca	233	uint64_t val, unsigned size)
dd53ded3 BS	234	{
	235	ECCState *s = opaque;
	236
97bf4851	237	trace_ecc_diag_mem_writeb(addr, val);
dd53ded3 BS	238	s->diag[addr & ECC_DIAG_MASK] = val;
	239	}
	240
a8170e5e	241	static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr,
7ef57cca	242	unsigned size)
dd53ded3 BS	243	{
dd53ded3 BS	244	ECCState *s = opaque;
e64d7d59 BS	245	uint32_t ret = s->diag[(int)addr];
e64d7d59 BS	246
97bf4851	247	trace_ecc_diag_mem_readb(addr, ret);
dd53ded3 BS	248	return ret;
	249	}
	250
7ef57cca AK	251	static const MemoryRegionOps ecc_diag_mem_ops = {
	252	.read = ecc_diag_mem_read,
	253	.write = ecc_diag_mem_write,
	254	.endianness = DEVICE_NATIVE_ENDIAN,
	255	.valid = {
	256	.min_access_size = 1,
	257	.max_access_size = 1,
	258	},
dd53ded3 BS	259	};
dd53ded3 BS	260
c21011a9 BS	261	static const VMStateDescription vmstate_ecc = {
	262	.name ="ECC",
	263	.version_id = 3,
	264	.minimum_version_id = 3,
	265	.minimum_version_id_old = 3,
	266	.fields = (VMStateField []) {
	267	VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS),
	268	VMSTATE_BUFFER(diag, ECCState),
	269	VMSTATE_UINT32(version, ECCState),
	270	VMSTATE_END_OF_LIST()
	271	}
	272	};
7eb0c8e8	273
0284dc54	274	static void ecc_reset(DeviceState *d)
7eb0c8e8	275	{
0284dc54	276	ECCState *s = container_of(d, ECCState, busdev.qdev);
7eb0c8e8	277
0bb3602c BS	278	if (s->version == ECC_MCC)
	279	s->regs[ECC_MER] &= ECC_MER_REU;
	280	else
	281	s->regs[ECC_MER] &= (ECC_MER_VER \| ECC_MER_IMPL \| ECC_MER_MRR \|
	282	ECC_MER_DCI);
dd53ded3 BS	283	s->regs[ECC_MDR] = 0x20;
	284	s->regs[ECC_MFSR] = 0;
	285	s->regs[ECC_VCR] = 0;
	286	s->regs[ECC_MFAR0] = 0x07c00000;
	287	s->regs[ECC_MFAR1] = 0;
	288	s->regs[ECC_DR] = 0;
	289	s->regs[ECC_ECR0] = 0;
	290	s->regs[ECC_ECR1] = 0;
7eb0c8e8 BS	291	}
7eb0c8e8 BS	292
81a322d4	293	static int ecc_init1(SysBusDevice *dev)
7eb0c8e8	294	{
49e66373	295	ECCState *s = FROM_SYSBUS(ECCState, dev);
7eb0c8e8	296
49e66373	297	sysbus_init_irq(dev, &s->irq);
49e66373	298	s->regs[0] = s->version;
7ef57cca	299	memory_region_init_io(&s->iomem, &ecc_mem_ops, s, "ecc", ECC_SIZE);
750ecd44	300	sysbus_init_mmio(dev, &s->iomem);
49e66373 BS	301
49e66373 BS	302	if (s->version == ECC_MCC) { // SS-600MP only
7ef57cca AK	303	memory_region_init_io(&s->iomem_diag, &ecc_diag_mem_ops, s,
7ef57cca AK	304	"ecc.diag", ECC_DIAG_SIZE);
750ecd44	305	sysbus_init_mmio(dev, &s->iomem_diag);
dd53ded3	306	}
0284dc54	307
81a322d4	308	return 0;
7eb0c8e8	309	}
49e66373	310
999e12bb AL	311	static Property ecc_properties[] = {
	312	DEFINE_PROP_HEX32("version", ECCState, version, -1),
	313	DEFINE_PROP_END_OF_LIST(),
	314	};
	315
	316	static void ecc_class_init(ObjectClass klass, void data)
	317	{
39bffca2	318	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	319	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	320
	321	k->init = ecc_init1;
39bffca2 AL	322	dc->reset = ecc_reset;
	323	dc->vmsd = &vmstate_ecc;
	324	dc->props = ecc_properties;
999e12bb AL	325	}
999e12bb AL	326
39bffca2 AL	327	static TypeInfo ecc_info = {
	328	.name = "eccmemctl",
	329	.parent = TYPE_SYS_BUS_DEVICE,
	330	.instance_size = sizeof(ECCState),
	331	.class_init = ecc_class_init,
ee6847d1 GH	332	};
	333
	334
83f7d43a	335	static void ecc_register_types(void)
49e66373	336	{
39bffca2	337	type_register_static(&ecc_info);
49e66373 BS	338	}
49e66373 BS	339
83f7d43a	340	type_init(ecc_register_types)