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1da12ec4 LT |
1 | /* |
2 | * QEMU emulation of an Intel IOMMU (VT-d) | |
3 | * (DMA Remapping device) | |
4 | * | |
5 | * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> | |
6 | * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | ||
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | ||
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include "hw/sysbus.h" | |
23 | #include "exec/address-spaces.h" | |
24 | #include "intel_iommu_internal.h" | |
25 | ||
26 | /*#define DEBUG_INTEL_IOMMU*/ | |
27 | #ifdef DEBUG_INTEL_IOMMU | |
28 | enum { | |
29 | DEBUG_GENERAL, DEBUG_CSR, DEBUG_INV, DEBUG_MMU, DEBUG_FLOG, | |
30 | }; | |
31 | #define VTD_DBGBIT(x) (1 << DEBUG_##x) | |
32 | static int vtd_dbgflags = VTD_DBGBIT(GENERAL) | VTD_DBGBIT(CSR); | |
33 | ||
34 | #define VTD_DPRINTF(what, fmt, ...) do { \ | |
35 | if (vtd_dbgflags & VTD_DBGBIT(what)) { \ | |
36 | fprintf(stderr, "(vtd)%s: " fmt "\n", __func__, \ | |
37 | ## __VA_ARGS__); } \ | |
38 | } while (0) | |
39 | #else | |
40 | #define VTD_DPRINTF(what, fmt, ...) do {} while (0) | |
41 | #endif | |
42 | ||
43 | static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val, | |
44 | uint64_t wmask, uint64_t w1cmask) | |
45 | { | |
46 | stq_le_p(&s->csr[addr], val); | |
47 | stq_le_p(&s->wmask[addr], wmask); | |
48 | stq_le_p(&s->w1cmask[addr], w1cmask); | |
49 | } | |
50 | ||
51 | static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask) | |
52 | { | |
53 | stq_le_p(&s->womask[addr], mask); | |
54 | } | |
55 | ||
56 | static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val, | |
57 | uint32_t wmask, uint32_t w1cmask) | |
58 | { | |
59 | stl_le_p(&s->csr[addr], val); | |
60 | stl_le_p(&s->wmask[addr], wmask); | |
61 | stl_le_p(&s->w1cmask[addr], w1cmask); | |
62 | } | |
63 | ||
64 | static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask) | |
65 | { | |
66 | stl_le_p(&s->womask[addr], mask); | |
67 | } | |
68 | ||
69 | /* "External" get/set operations */ | |
70 | static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val) | |
71 | { | |
72 | uint64_t oldval = ldq_le_p(&s->csr[addr]); | |
73 | uint64_t wmask = ldq_le_p(&s->wmask[addr]); | |
74 | uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]); | |
75 | stq_le_p(&s->csr[addr], | |
76 | ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val)); | |
77 | } | |
78 | ||
79 | static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val) | |
80 | { | |
81 | uint32_t oldval = ldl_le_p(&s->csr[addr]); | |
82 | uint32_t wmask = ldl_le_p(&s->wmask[addr]); | |
83 | uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]); | |
84 | stl_le_p(&s->csr[addr], | |
85 | ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val)); | |
86 | } | |
87 | ||
88 | static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr) | |
89 | { | |
90 | uint64_t val = ldq_le_p(&s->csr[addr]); | |
91 | uint64_t womask = ldq_le_p(&s->womask[addr]); | |
92 | return val & ~womask; | |
93 | } | |
94 | ||
95 | static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr) | |
96 | { | |
97 | uint32_t val = ldl_le_p(&s->csr[addr]); | |
98 | uint32_t womask = ldl_le_p(&s->womask[addr]); | |
99 | return val & ~womask; | |
100 | } | |
101 | ||
102 | /* "Internal" get/set operations */ | |
103 | static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr) | |
104 | { | |
105 | return ldq_le_p(&s->csr[addr]); | |
106 | } | |
107 | ||
108 | static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr) | |
109 | { | |
110 | return ldl_le_p(&s->csr[addr]); | |
111 | } | |
112 | ||
113 | static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val) | |
114 | { | |
115 | stq_le_p(&s->csr[addr], val); | |
116 | } | |
117 | ||
118 | static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr, | |
119 | uint32_t clear, uint32_t mask) | |
120 | { | |
121 | uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask; | |
122 | stl_le_p(&s->csr[addr], new_val); | |
123 | return new_val; | |
124 | } | |
125 | ||
126 | static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr, | |
127 | uint64_t clear, uint64_t mask) | |
128 | { | |
129 | uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask; | |
130 | stq_le_p(&s->csr[addr], new_val); | |
131 | return new_val; | |
132 | } | |
133 | ||
134 | /* Given the reg addr of both the message data and address, generate an | |
135 | * interrupt via MSI. | |
136 | */ | |
137 | static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg, | |
138 | hwaddr mesg_data_reg) | |
139 | { | |
140 | hwaddr addr; | |
141 | uint32_t data; | |
142 | ||
143 | assert(mesg_data_reg < DMAR_REG_SIZE); | |
144 | assert(mesg_addr_reg < DMAR_REG_SIZE); | |
145 | ||
146 | addr = vtd_get_long_raw(s, mesg_addr_reg); | |
147 | data = vtd_get_long_raw(s, mesg_data_reg); | |
148 | ||
149 | VTD_DPRINTF(FLOG, "msi: addr 0x%"PRIx64 " data 0x%"PRIx32, addr, data); | |
150 | stl_le_phys(&address_space_memory, addr, data); | |
151 | } | |
152 | ||
153 | /* Generate a fault event to software via MSI if conditions are met. | |
154 | * Notice that the value of FSTS_REG being passed to it should be the one | |
155 | * before any update. | |
156 | */ | |
157 | static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts) | |
158 | { | |
159 | if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO || | |
160 | pre_fsts & VTD_FSTS_IQE) { | |
161 | VTD_DPRINTF(FLOG, "there are previous interrupt conditions " | |
162 | "to be serviced by software, fault event is not generated " | |
163 | "(FSTS_REG 0x%"PRIx32 ")", pre_fsts); | |
164 | return; | |
165 | } | |
166 | vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP); | |
167 | if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) { | |
168 | VTD_DPRINTF(FLOG, "Interrupt Mask set, fault event is not generated"); | |
169 | } else { | |
170 | vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG); | |
171 | vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0); | |
172 | } | |
173 | } | |
174 | ||
175 | /* Check if the Fault (F) field of the Fault Recording Register referenced by | |
176 | * @index is Set. | |
177 | */ | |
178 | static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index) | |
179 | { | |
180 | /* Each reg is 128-bit */ | |
181 | hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4); | |
182 | addr += 8; /* Access the high 64-bit half */ | |
183 | ||
184 | assert(index < DMAR_FRCD_REG_NR); | |
185 | ||
186 | return vtd_get_quad_raw(s, addr) & VTD_FRCD_F; | |
187 | } | |
188 | ||
189 | /* Update the PPF field of Fault Status Register. | |
190 | * Should be called whenever change the F field of any fault recording | |
191 | * registers. | |
192 | */ | |
193 | static void vtd_update_fsts_ppf(IntelIOMMUState *s) | |
194 | { | |
195 | uint32_t i; | |
196 | uint32_t ppf_mask = 0; | |
197 | ||
198 | for (i = 0; i < DMAR_FRCD_REG_NR; i++) { | |
199 | if (vtd_is_frcd_set(s, i)) { | |
200 | ppf_mask = VTD_FSTS_PPF; | |
201 | break; | |
202 | } | |
203 | } | |
204 | vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask); | |
205 | VTD_DPRINTF(FLOG, "set PPF of FSTS_REG to %d", ppf_mask ? 1 : 0); | |
206 | } | |
207 | ||
208 | static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index) | |
209 | { | |
210 | /* Each reg is 128-bit */ | |
211 | hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4); | |
212 | addr += 8; /* Access the high 64-bit half */ | |
213 | ||
214 | assert(index < DMAR_FRCD_REG_NR); | |
215 | ||
216 | vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F); | |
217 | vtd_update_fsts_ppf(s); | |
218 | } | |
219 | ||
220 | /* Must not update F field now, should be done later */ | |
221 | static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index, | |
222 | uint16_t source_id, hwaddr addr, | |
223 | VTDFaultReason fault, bool is_write) | |
224 | { | |
225 | uint64_t hi = 0, lo; | |
226 | hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4); | |
227 | ||
228 | assert(index < DMAR_FRCD_REG_NR); | |
229 | ||
230 | lo = VTD_FRCD_FI(addr); | |
231 | hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault); | |
232 | if (!is_write) { | |
233 | hi |= VTD_FRCD_T; | |
234 | } | |
235 | vtd_set_quad_raw(s, frcd_reg_addr, lo); | |
236 | vtd_set_quad_raw(s, frcd_reg_addr + 8, hi); | |
237 | VTD_DPRINTF(FLOG, "record to FRCD_REG #%"PRIu16 ": hi 0x%"PRIx64 | |
238 | ", lo 0x%"PRIx64, index, hi, lo); | |
239 | } | |
240 | ||
241 | /* Try to collapse multiple pending faults from the same requester */ | |
242 | static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id) | |
243 | { | |
244 | uint32_t i; | |
245 | uint64_t frcd_reg; | |
246 | hwaddr addr = DMAR_FRCD_REG_OFFSET + 8; /* The high 64-bit half */ | |
247 | ||
248 | for (i = 0; i < DMAR_FRCD_REG_NR; i++) { | |
249 | frcd_reg = vtd_get_quad_raw(s, addr); | |
250 | VTD_DPRINTF(FLOG, "frcd_reg #%d 0x%"PRIx64, i, frcd_reg); | |
251 | if ((frcd_reg & VTD_FRCD_F) && | |
252 | ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) { | |
253 | return true; | |
254 | } | |
255 | addr += 16; /* 128-bit for each */ | |
256 | } | |
257 | return false; | |
258 | } | |
259 | ||
260 | /* Log and report an DMAR (address translation) fault to software */ | |
261 | static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id, | |
262 | hwaddr addr, VTDFaultReason fault, | |
263 | bool is_write) | |
264 | { | |
265 | uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG); | |
266 | ||
267 | assert(fault < VTD_FR_MAX); | |
268 | ||
269 | if (fault == VTD_FR_RESERVED_ERR) { | |
270 | /* This is not a normal fault reason case. Drop it. */ | |
271 | return; | |
272 | } | |
273 | VTD_DPRINTF(FLOG, "sid 0x%"PRIx16 ", fault %d, addr 0x%"PRIx64 | |
274 | ", is_write %d", source_id, fault, addr, is_write); | |
275 | if (fsts_reg & VTD_FSTS_PFO) { | |
276 | VTD_DPRINTF(FLOG, "new fault is not recorded due to " | |
277 | "Primary Fault Overflow"); | |
278 | return; | |
279 | } | |
280 | if (vtd_try_collapse_fault(s, source_id)) { | |
281 | VTD_DPRINTF(FLOG, "new fault is not recorded due to " | |
282 | "compression of faults"); | |
283 | return; | |
284 | } | |
285 | if (vtd_is_frcd_set(s, s->next_frcd_reg)) { | |
286 | VTD_DPRINTF(FLOG, "Primary Fault Overflow and " | |
287 | "new fault is not recorded, set PFO field"); | |
288 | vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO); | |
289 | return; | |
290 | } | |
291 | ||
292 | vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write); | |
293 | ||
294 | if (fsts_reg & VTD_FSTS_PPF) { | |
295 | VTD_DPRINTF(FLOG, "there are pending faults already, " | |
296 | "fault event is not generated"); | |
297 | vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); | |
298 | s->next_frcd_reg++; | |
299 | if (s->next_frcd_reg == DMAR_FRCD_REG_NR) { | |
300 | s->next_frcd_reg = 0; | |
301 | } | |
302 | } else { | |
303 | vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK, | |
304 | VTD_FSTS_FRI(s->next_frcd_reg)); | |
305 | vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); /* Will set PPF */ | |
306 | s->next_frcd_reg++; | |
307 | if (s->next_frcd_reg == DMAR_FRCD_REG_NR) { | |
308 | s->next_frcd_reg = 0; | |
309 | } | |
310 | /* This case actually cause the PPF to be Set. | |
311 | * So generate fault event (interrupt). | |
312 | */ | |
313 | vtd_generate_fault_event(s, fsts_reg); | |
314 | } | |
315 | } | |
316 | ||
ed7b8fbc LT |
317 | /* Handle Invalidation Queue Errors of queued invalidation interface error |
318 | * conditions. | |
319 | */ | |
320 | static void vtd_handle_inv_queue_error(IntelIOMMUState *s) | |
321 | { | |
322 | uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG); | |
323 | ||
324 | vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE); | |
325 | vtd_generate_fault_event(s, fsts_reg); | |
326 | } | |
327 | ||
328 | /* Set the IWC field and try to generate an invalidation completion interrupt */ | |
329 | static void vtd_generate_completion_event(IntelIOMMUState *s) | |
330 | { | |
331 | VTD_DPRINTF(INV, "completes an invalidation wait command with " | |
332 | "Interrupt Flag"); | |
333 | if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) { | |
334 | VTD_DPRINTF(INV, "there is a previous interrupt condition to be " | |
335 | "serviced by software, " | |
336 | "new invalidation event is not generated"); | |
337 | return; | |
338 | } | |
339 | vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC); | |
340 | vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP); | |
341 | if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) { | |
342 | VTD_DPRINTF(INV, "IM filed in IECTL_REG is set, new invalidation " | |
343 | "event is not generated"); | |
344 | return; | |
345 | } else { | |
346 | /* Generate the interrupt event */ | |
347 | vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG); | |
348 | vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0); | |
349 | } | |
350 | } | |
351 | ||
1da12ec4 LT |
352 | static inline bool vtd_root_entry_present(VTDRootEntry *root) |
353 | { | |
354 | return root->val & VTD_ROOT_ENTRY_P; | |
355 | } | |
356 | ||
357 | static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index, | |
358 | VTDRootEntry *re) | |
359 | { | |
360 | dma_addr_t addr; | |
361 | ||
362 | addr = s->root + index * sizeof(*re); | |
363 | if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) { | |
364 | VTD_DPRINTF(GENERAL, "error: fail to access root-entry at 0x%"PRIx64 | |
365 | " + %"PRIu8, s->root, index); | |
366 | re->val = 0; | |
367 | return -VTD_FR_ROOT_TABLE_INV; | |
368 | } | |
369 | re->val = le64_to_cpu(re->val); | |
370 | return 0; | |
371 | } | |
372 | ||
373 | static inline bool vtd_context_entry_present(VTDContextEntry *context) | |
374 | { | |
375 | return context->lo & VTD_CONTEXT_ENTRY_P; | |
376 | } | |
377 | ||
378 | static int vtd_get_context_entry_from_root(VTDRootEntry *root, uint8_t index, | |
379 | VTDContextEntry *ce) | |
380 | { | |
381 | dma_addr_t addr; | |
382 | ||
383 | if (!vtd_root_entry_present(root)) { | |
384 | VTD_DPRINTF(GENERAL, "error: root-entry is not present"); | |
385 | return -VTD_FR_ROOT_ENTRY_P; | |
386 | } | |
387 | addr = (root->val & VTD_ROOT_ENTRY_CTP) + index * sizeof(*ce); | |
388 | if (dma_memory_read(&address_space_memory, addr, ce, sizeof(*ce))) { | |
389 | VTD_DPRINTF(GENERAL, "error: fail to access context-entry at 0x%"PRIx64 | |
390 | " + %"PRIu8, | |
391 | (uint64_t)(root->val & VTD_ROOT_ENTRY_CTP), index); | |
392 | return -VTD_FR_CONTEXT_TABLE_INV; | |
393 | } | |
394 | ce->lo = le64_to_cpu(ce->lo); | |
395 | ce->hi = le64_to_cpu(ce->hi); | |
396 | return 0; | |
397 | } | |
398 | ||
399 | static inline dma_addr_t vtd_get_slpt_base_from_context(VTDContextEntry *ce) | |
400 | { | |
401 | return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR; | |
402 | } | |
403 | ||
404 | /* The shift of an addr for a certain level of paging structure */ | |
405 | static inline uint32_t vtd_slpt_level_shift(uint32_t level) | |
406 | { | |
407 | return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS; | |
408 | } | |
409 | ||
410 | static inline uint64_t vtd_get_slpte_addr(uint64_t slpte) | |
411 | { | |
412 | return slpte & VTD_SL_PT_BASE_ADDR_MASK; | |
413 | } | |
414 | ||
415 | /* Whether the pte indicates the address of the page frame */ | |
416 | static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level) | |
417 | { | |
418 | return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK); | |
419 | } | |
420 | ||
421 | /* Get the content of a spte located in @base_addr[@index] */ | |
422 | static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index) | |
423 | { | |
424 | uint64_t slpte; | |
425 | ||
426 | assert(index < VTD_SL_PT_ENTRY_NR); | |
427 | ||
428 | if (dma_memory_read(&address_space_memory, | |
429 | base_addr + index * sizeof(slpte), &slpte, | |
430 | sizeof(slpte))) { | |
431 | slpte = (uint64_t)-1; | |
432 | return slpte; | |
433 | } | |
434 | slpte = le64_to_cpu(slpte); | |
435 | return slpte; | |
436 | } | |
437 | ||
438 | /* Given a gpa and the level of paging structure, return the offset of current | |
439 | * level. | |
440 | */ | |
441 | static inline uint32_t vtd_gpa_level_offset(uint64_t gpa, uint32_t level) | |
442 | { | |
443 | return (gpa >> vtd_slpt_level_shift(level)) & | |
444 | ((1ULL << VTD_SL_LEVEL_BITS) - 1); | |
445 | } | |
446 | ||
447 | /* Check Capability Register to see if the @level of page-table is supported */ | |
448 | static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level) | |
449 | { | |
450 | return VTD_CAP_SAGAW_MASK & s->cap & | |
451 | (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT)); | |
452 | } | |
453 | ||
454 | /* Get the page-table level that hardware should use for the second-level | |
455 | * page-table walk from the Address Width field of context-entry. | |
456 | */ | |
457 | static inline uint32_t vtd_get_level_from_context_entry(VTDContextEntry *ce) | |
458 | { | |
459 | return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW); | |
460 | } | |
461 | ||
462 | static inline uint32_t vtd_get_agaw_from_context_entry(VTDContextEntry *ce) | |
463 | { | |
464 | return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9; | |
465 | } | |
466 | ||
467 | static const uint64_t vtd_paging_entry_rsvd_field[] = { | |
468 | [0] = ~0ULL, | |
469 | /* For not large page */ | |
470 | [1] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM), | |
471 | [2] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM), | |
472 | [3] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM), | |
473 | [4] = 0x880ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM), | |
474 | /* For large page */ | |
475 | [5] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM), | |
476 | [6] = 0x1ff800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM), | |
477 | [7] = 0x3ffff800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM), | |
478 | [8] = 0x880ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM), | |
479 | }; | |
480 | ||
481 | static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level) | |
482 | { | |
483 | if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) { | |
484 | /* Maybe large page */ | |
485 | return slpte & vtd_paging_entry_rsvd_field[level + 4]; | |
486 | } else { | |
487 | return slpte & vtd_paging_entry_rsvd_field[level]; | |
488 | } | |
489 | } | |
490 | ||
491 | /* Given the @gpa, get relevant @slptep. @slpte_level will be the last level | |
492 | * of the translation, can be used for deciding the size of large page. | |
493 | */ | |
494 | static int vtd_gpa_to_slpte(VTDContextEntry *ce, uint64_t gpa, bool is_write, | |
495 | uint64_t *slptep, uint32_t *slpte_level, | |
496 | bool *reads, bool *writes) | |
497 | { | |
498 | dma_addr_t addr = vtd_get_slpt_base_from_context(ce); | |
499 | uint32_t level = vtd_get_level_from_context_entry(ce); | |
500 | uint32_t offset; | |
501 | uint64_t slpte; | |
502 | uint32_t ce_agaw = vtd_get_agaw_from_context_entry(ce); | |
503 | uint64_t access_right_check; | |
504 | ||
505 | /* Check if @gpa is above 2^X-1, where X is the minimum of MGAW in CAP_REG | |
506 | * and AW in context-entry. | |
507 | */ | |
508 | if (gpa & ~((1ULL << MIN(ce_agaw, VTD_MGAW)) - 1)) { | |
509 | VTD_DPRINTF(GENERAL, "error: gpa 0x%"PRIx64 " exceeds limits", gpa); | |
510 | return -VTD_FR_ADDR_BEYOND_MGAW; | |
511 | } | |
512 | ||
513 | /* FIXME: what is the Atomics request here? */ | |
514 | access_right_check = is_write ? VTD_SL_W : VTD_SL_R; | |
515 | ||
516 | while (true) { | |
517 | offset = vtd_gpa_level_offset(gpa, level); | |
518 | slpte = vtd_get_slpte(addr, offset); | |
519 | ||
520 | if (slpte == (uint64_t)-1) { | |
521 | VTD_DPRINTF(GENERAL, "error: fail to access second-level paging " | |
522 | "entry at level %"PRIu32 " for gpa 0x%"PRIx64, | |
523 | level, gpa); | |
524 | if (level == vtd_get_level_from_context_entry(ce)) { | |
525 | /* Invalid programming of context-entry */ | |
526 | return -VTD_FR_CONTEXT_ENTRY_INV; | |
527 | } else { | |
528 | return -VTD_FR_PAGING_ENTRY_INV; | |
529 | } | |
530 | } | |
531 | *reads = (*reads) && (slpte & VTD_SL_R); | |
532 | *writes = (*writes) && (slpte & VTD_SL_W); | |
533 | if (!(slpte & access_right_check)) { | |
534 | VTD_DPRINTF(GENERAL, "error: lack of %s permission for " | |
535 | "gpa 0x%"PRIx64 " slpte 0x%"PRIx64, | |
536 | (is_write ? "write" : "read"), gpa, slpte); | |
537 | return is_write ? -VTD_FR_WRITE : -VTD_FR_READ; | |
538 | } | |
539 | if (vtd_slpte_nonzero_rsvd(slpte, level)) { | |
540 | VTD_DPRINTF(GENERAL, "error: non-zero reserved field in second " | |
541 | "level paging entry level %"PRIu32 " slpte 0x%"PRIx64, | |
542 | level, slpte); | |
543 | return -VTD_FR_PAGING_ENTRY_RSVD; | |
544 | } | |
545 | ||
546 | if (vtd_is_last_slpte(slpte, level)) { | |
547 | *slptep = slpte; | |
548 | *slpte_level = level; | |
549 | return 0; | |
550 | } | |
551 | addr = vtd_get_slpte_addr(slpte); | |
552 | level--; | |
553 | } | |
554 | } | |
555 | ||
556 | /* Map a device to its corresponding domain (context-entry) */ | |
557 | static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, | |
558 | uint8_t devfn, VTDContextEntry *ce) | |
559 | { | |
560 | VTDRootEntry re; | |
561 | int ret_fr; | |
562 | ||
563 | ret_fr = vtd_get_root_entry(s, bus_num, &re); | |
564 | if (ret_fr) { | |
565 | return ret_fr; | |
566 | } | |
567 | ||
568 | if (!vtd_root_entry_present(&re)) { | |
569 | VTD_DPRINTF(GENERAL, "error: root-entry #%"PRIu8 " is not present", | |
570 | bus_num); | |
571 | return -VTD_FR_ROOT_ENTRY_P; | |
572 | } else if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD)) { | |
573 | VTD_DPRINTF(GENERAL, "error: non-zero reserved field in root-entry " | |
574 | "hi 0x%"PRIx64 " lo 0x%"PRIx64, re.rsvd, re.val); | |
575 | return -VTD_FR_ROOT_ENTRY_RSVD; | |
576 | } | |
577 | ||
578 | ret_fr = vtd_get_context_entry_from_root(&re, devfn, ce); | |
579 | if (ret_fr) { | |
580 | return ret_fr; | |
581 | } | |
582 | ||
583 | if (!vtd_context_entry_present(ce)) { | |
584 | VTD_DPRINTF(GENERAL, | |
585 | "error: context-entry #%"PRIu8 "(bus #%"PRIu8 ") " | |
586 | "is not present", devfn, bus_num); | |
587 | return -VTD_FR_CONTEXT_ENTRY_P; | |
588 | } else if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) || | |
589 | (ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO)) { | |
590 | VTD_DPRINTF(GENERAL, | |
591 | "error: non-zero reserved field in context-entry " | |
592 | "hi 0x%"PRIx64 " lo 0x%"PRIx64, ce->hi, ce->lo); | |
593 | return -VTD_FR_CONTEXT_ENTRY_RSVD; | |
594 | } | |
595 | /* Check if the programming of context-entry is valid */ | |
596 | if (!vtd_is_level_supported(s, vtd_get_level_from_context_entry(ce))) { | |
597 | VTD_DPRINTF(GENERAL, "error: unsupported Address Width value in " | |
598 | "context-entry hi 0x%"PRIx64 " lo 0x%"PRIx64, | |
599 | ce->hi, ce->lo); | |
600 | return -VTD_FR_CONTEXT_ENTRY_INV; | |
601 | } else if (ce->lo & VTD_CONTEXT_ENTRY_TT) { | |
602 | VTD_DPRINTF(GENERAL, "error: unsupported Translation Type in " | |
603 | "context-entry hi 0x%"PRIx64 " lo 0x%"PRIx64, | |
604 | ce->hi, ce->lo); | |
605 | return -VTD_FR_CONTEXT_ENTRY_INV; | |
606 | } | |
607 | return 0; | |
608 | } | |
609 | ||
610 | static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn) | |
611 | { | |
612 | return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL); | |
613 | } | |
614 | ||
615 | static const bool vtd_qualified_faults[] = { | |
616 | [VTD_FR_RESERVED] = false, | |
617 | [VTD_FR_ROOT_ENTRY_P] = false, | |
618 | [VTD_FR_CONTEXT_ENTRY_P] = true, | |
619 | [VTD_FR_CONTEXT_ENTRY_INV] = true, | |
620 | [VTD_FR_ADDR_BEYOND_MGAW] = true, | |
621 | [VTD_FR_WRITE] = true, | |
622 | [VTD_FR_READ] = true, | |
623 | [VTD_FR_PAGING_ENTRY_INV] = true, | |
624 | [VTD_FR_ROOT_TABLE_INV] = false, | |
625 | [VTD_FR_CONTEXT_TABLE_INV] = false, | |
626 | [VTD_FR_ROOT_ENTRY_RSVD] = false, | |
627 | [VTD_FR_PAGING_ENTRY_RSVD] = true, | |
628 | [VTD_FR_CONTEXT_ENTRY_TT] = true, | |
629 | [VTD_FR_RESERVED_ERR] = false, | |
630 | [VTD_FR_MAX] = false, | |
631 | }; | |
632 | ||
633 | /* To see if a fault condition is "qualified", which is reported to software | |
634 | * only if the FPD field in the context-entry used to process the faulting | |
635 | * request is 0. | |
636 | */ | |
637 | static inline bool vtd_is_qualified_fault(VTDFaultReason fault) | |
638 | { | |
639 | return vtd_qualified_faults[fault]; | |
640 | } | |
641 | ||
642 | static inline bool vtd_is_interrupt_addr(hwaddr addr) | |
643 | { | |
644 | return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST; | |
645 | } | |
646 | ||
647 | /* Map dev to context-entry then do a paging-structures walk to do a iommu | |
648 | * translation. | |
649 | * @bus_num: The bus number | |
650 | * @devfn: The devfn, which is the combined of device and function number | |
651 | * @is_write: The access is a write operation | |
652 | * @entry: IOMMUTLBEntry that contain the addr to be translated and result | |
653 | */ | |
654 | static void vtd_do_iommu_translate(IntelIOMMUState *s, uint8_t bus_num, | |
655 | uint8_t devfn, hwaddr addr, bool is_write, | |
656 | IOMMUTLBEntry *entry) | |
657 | { | |
658 | VTDContextEntry ce; | |
659 | uint64_t slpte; | |
660 | uint32_t level; | |
661 | uint16_t source_id = vtd_make_source_id(bus_num, devfn); | |
662 | int ret_fr; | |
663 | bool is_fpd_set = false; | |
664 | bool reads = true; | |
665 | bool writes = true; | |
666 | ||
667 | /* Check if the request is in interrupt address range */ | |
668 | if (vtd_is_interrupt_addr(addr)) { | |
669 | if (is_write) { | |
670 | /* FIXME: since we don't know the length of the access here, we | |
671 | * treat Non-DWORD length write requests without PASID as | |
672 | * interrupt requests, too. Withoud interrupt remapping support, | |
673 | * we just use 1:1 mapping. | |
674 | */ | |
675 | VTD_DPRINTF(MMU, "write request to interrupt address " | |
676 | "gpa 0x%"PRIx64, addr); | |
677 | entry->iova = addr & VTD_PAGE_MASK_4K; | |
678 | entry->translated_addr = addr & VTD_PAGE_MASK_4K; | |
679 | entry->addr_mask = ~VTD_PAGE_MASK_4K; | |
680 | entry->perm = IOMMU_WO; | |
681 | return; | |
682 | } else { | |
683 | VTD_DPRINTF(GENERAL, "error: read request from interrupt address " | |
684 | "gpa 0x%"PRIx64, addr); | |
685 | vtd_report_dmar_fault(s, source_id, addr, VTD_FR_READ, is_write); | |
686 | return; | |
687 | } | |
688 | } | |
689 | ||
690 | ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce); | |
691 | is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD; | |
692 | if (ret_fr) { | |
693 | ret_fr = -ret_fr; | |
694 | if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) { | |
695 | VTD_DPRINTF(FLOG, "fault processing is disabled for DMA requests " | |
696 | "through this context-entry (with FPD Set)"); | |
697 | } else { | |
698 | vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write); | |
699 | } | |
700 | return; | |
701 | } | |
702 | ||
703 | ret_fr = vtd_gpa_to_slpte(&ce, addr, is_write, &slpte, &level, | |
704 | &reads, &writes); | |
705 | if (ret_fr) { | |
706 | ret_fr = -ret_fr; | |
707 | if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) { | |
708 | VTD_DPRINTF(FLOG, "fault processing is disabled for DMA requests " | |
709 | "through this context-entry (with FPD Set)"); | |
710 | } else { | |
711 | vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write); | |
712 | } | |
713 | return; | |
714 | } | |
715 | ||
716 | entry->iova = addr & VTD_PAGE_MASK_4K; | |
717 | entry->translated_addr = vtd_get_slpte_addr(slpte) & VTD_PAGE_MASK_4K; | |
718 | entry->addr_mask = ~VTD_PAGE_MASK_4K; | |
719 | entry->perm = (writes ? 2 : 0) + (reads ? 1 : 0); | |
720 | } | |
721 | ||
722 | static void vtd_root_table_setup(IntelIOMMUState *s) | |
723 | { | |
724 | s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG); | |
725 | s->root_extended = s->root & VTD_RTADDR_RTT; | |
726 | s->root &= VTD_RTADDR_ADDR_MASK; | |
727 | ||
728 | VTD_DPRINTF(CSR, "root_table addr 0x%"PRIx64 " %s", s->root, | |
729 | (s->root_extended ? "(extended)" : "")); | |
730 | } | |
731 | ||
732 | /* Context-cache invalidation | |
733 | * Returns the Context Actual Invalidation Granularity. | |
734 | * @val: the content of the CCMD_REG | |
735 | */ | |
736 | static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val) | |
737 | { | |
738 | uint64_t caig; | |
739 | uint64_t type = val & VTD_CCMD_CIRG_MASK; | |
740 | ||
741 | switch (type) { | |
742 | case VTD_CCMD_GLOBAL_INVL: | |
743 | VTD_DPRINTF(INV, "Global invalidation request"); | |
744 | caig = VTD_CCMD_GLOBAL_INVL_A; | |
745 | break; | |
746 | ||
747 | case VTD_CCMD_DOMAIN_INVL: | |
748 | VTD_DPRINTF(INV, "Domain-selective invalidation request"); | |
749 | caig = VTD_CCMD_DOMAIN_INVL_A; | |
750 | break; | |
751 | ||
752 | case VTD_CCMD_DEVICE_INVL: | |
753 | VTD_DPRINTF(INV, "Domain-selective invalidation request"); | |
754 | caig = VTD_CCMD_DEVICE_INVL_A; | |
755 | break; | |
756 | ||
757 | default: | |
758 | VTD_DPRINTF(GENERAL, | |
759 | "error: wrong context-cache invalidation granularity"); | |
760 | caig = 0; | |
761 | } | |
762 | return caig; | |
763 | } | |
764 | ||
765 | /* Flush IOTLB | |
766 | * Returns the IOTLB Actual Invalidation Granularity. | |
767 | * @val: the content of the IOTLB_REG | |
768 | */ | |
769 | static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val) | |
770 | { | |
771 | uint64_t iaig; | |
772 | uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK; | |
773 | ||
774 | switch (type) { | |
775 | case VTD_TLB_GLOBAL_FLUSH: | |
776 | VTD_DPRINTF(INV, "Global IOTLB flush"); | |
777 | iaig = VTD_TLB_GLOBAL_FLUSH_A; | |
778 | break; | |
779 | ||
780 | case VTD_TLB_DSI_FLUSH: | |
781 | VTD_DPRINTF(INV, "Domain-selective IOTLB flush"); | |
782 | iaig = VTD_TLB_DSI_FLUSH_A; | |
783 | break; | |
784 | ||
785 | case VTD_TLB_PSI_FLUSH: | |
786 | VTD_DPRINTF(INV, "Page-selective-within-domain IOTLB flush"); | |
787 | iaig = VTD_TLB_PSI_FLUSH_A; | |
788 | break; | |
789 | ||
790 | default: | |
791 | VTD_DPRINTF(GENERAL, "error: wrong iotlb flush granularity"); | |
792 | iaig = 0; | |
793 | } | |
794 | return iaig; | |
795 | } | |
796 | ||
ed7b8fbc LT |
797 | static inline bool vtd_queued_inv_enable_check(IntelIOMMUState *s) |
798 | { | |
799 | return s->iq_tail == 0; | |
800 | } | |
801 | ||
802 | static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s) | |
803 | { | |
804 | return s->qi_enabled && (s->iq_tail == s->iq_head) && | |
805 | (s->iq_last_desc_type == VTD_INV_DESC_WAIT); | |
806 | } | |
807 | ||
808 | static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en) | |
809 | { | |
810 | uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG); | |
811 | ||
812 | VTD_DPRINTF(INV, "Queued Invalidation Enable %s", (en ? "on" : "off")); | |
813 | if (en) { | |
814 | if (vtd_queued_inv_enable_check(s)) { | |
815 | s->iq = iqa_val & VTD_IQA_IQA_MASK; | |
816 | /* 2^(x+8) entries */ | |
817 | s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8); | |
818 | s->qi_enabled = true; | |
819 | VTD_DPRINTF(INV, "DMAR_IQA_REG 0x%"PRIx64, iqa_val); | |
820 | VTD_DPRINTF(INV, "Invalidation Queue addr 0x%"PRIx64 " size %d", | |
821 | s->iq, s->iq_size); | |
822 | /* Ok - report back to driver */ | |
823 | vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES); | |
824 | } else { | |
825 | VTD_DPRINTF(GENERAL, "error: can't enable Queued Invalidation: " | |
826 | "tail %"PRIu16, s->iq_tail); | |
827 | } | |
828 | } else { | |
829 | if (vtd_queued_inv_disable_check(s)) { | |
830 | /* disable Queued Invalidation */ | |
831 | vtd_set_quad_raw(s, DMAR_IQH_REG, 0); | |
832 | s->iq_head = 0; | |
833 | s->qi_enabled = false; | |
834 | /* Ok - report back to driver */ | |
835 | vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0); | |
836 | } else { | |
837 | VTD_DPRINTF(GENERAL, "error: can't disable Queued Invalidation: " | |
838 | "head %"PRIu16 ", tail %"PRIu16 | |
839 | ", last_descriptor %"PRIu8, | |
840 | s->iq_head, s->iq_tail, s->iq_last_desc_type); | |
841 | } | |
842 | } | |
843 | } | |
844 | ||
1da12ec4 LT |
845 | /* Set Root Table Pointer */ |
846 | static void vtd_handle_gcmd_srtp(IntelIOMMUState *s) | |
847 | { | |
848 | VTD_DPRINTF(CSR, "set Root Table Pointer"); | |
849 | ||
850 | vtd_root_table_setup(s); | |
851 | /* Ok - report back to driver */ | |
852 | vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS); | |
853 | } | |
854 | ||
855 | /* Handle Translation Enable/Disable */ | |
856 | static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en) | |
857 | { | |
858 | VTD_DPRINTF(CSR, "Translation Enable %s", (en ? "on" : "off")); | |
859 | ||
860 | if (en) { | |
861 | s->dmar_enabled = true; | |
862 | /* Ok - report back to driver */ | |
863 | vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES); | |
864 | } else { | |
865 | s->dmar_enabled = false; | |
866 | ||
867 | /* Clear the index of Fault Recording Register */ | |
868 | s->next_frcd_reg = 0; | |
869 | /* Ok - report back to driver */ | |
870 | vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0); | |
871 | } | |
872 | } | |
873 | ||
874 | /* Handle write to Global Command Register */ | |
875 | static void vtd_handle_gcmd_write(IntelIOMMUState *s) | |
876 | { | |
877 | uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG); | |
878 | uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG); | |
879 | uint32_t changed = status ^ val; | |
880 | ||
881 | VTD_DPRINTF(CSR, "value 0x%"PRIx32 " status 0x%"PRIx32, val, status); | |
882 | if (changed & VTD_GCMD_TE) { | |
883 | /* Translation enable/disable */ | |
884 | vtd_handle_gcmd_te(s, val & VTD_GCMD_TE); | |
885 | } | |
886 | if (val & VTD_GCMD_SRTP) { | |
887 | /* Set/update the root-table pointer */ | |
888 | vtd_handle_gcmd_srtp(s); | |
889 | } | |
ed7b8fbc LT |
890 | if (changed & VTD_GCMD_QIE) { |
891 | /* Queued Invalidation Enable */ | |
892 | vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE); | |
893 | } | |
1da12ec4 LT |
894 | } |
895 | ||
896 | /* Handle write to Context Command Register */ | |
897 | static void vtd_handle_ccmd_write(IntelIOMMUState *s) | |
898 | { | |
899 | uint64_t ret; | |
900 | uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG); | |
901 | ||
902 | /* Context-cache invalidation request */ | |
903 | if (val & VTD_CCMD_ICC) { | |
ed7b8fbc LT |
904 | if (s->qi_enabled) { |
905 | VTD_DPRINTF(GENERAL, "error: Queued Invalidation enabled, " | |
906 | "should not use register-based invalidation"); | |
907 | return; | |
908 | } | |
1da12ec4 LT |
909 | ret = vtd_context_cache_invalidate(s, val); |
910 | /* Invalidation completed. Change something to show */ | |
911 | vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL); | |
912 | ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK, | |
913 | ret); | |
914 | VTD_DPRINTF(INV, "CCMD_REG write-back val: 0x%"PRIx64, ret); | |
915 | } | |
916 | } | |
917 | ||
918 | /* Handle write to IOTLB Invalidation Register */ | |
919 | static void vtd_handle_iotlb_write(IntelIOMMUState *s) | |
920 | { | |
921 | uint64_t ret; | |
922 | uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG); | |
923 | ||
924 | /* IOTLB invalidation request */ | |
925 | if (val & VTD_TLB_IVT) { | |
ed7b8fbc LT |
926 | if (s->qi_enabled) { |
927 | VTD_DPRINTF(GENERAL, "error: Queued Invalidation enabled, " | |
928 | "should not use register-based invalidation"); | |
929 | return; | |
930 | } | |
1da12ec4 LT |
931 | ret = vtd_iotlb_flush(s, val); |
932 | /* Invalidation completed. Change something to show */ | |
933 | vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL); | |
934 | ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, | |
935 | VTD_TLB_FLUSH_GRANU_MASK_A, ret); | |
936 | VTD_DPRINTF(INV, "IOTLB_REG write-back val: 0x%"PRIx64, ret); | |
937 | } | |
938 | } | |
939 | ||
ed7b8fbc LT |
940 | /* Fetch an Invalidation Descriptor from the Invalidation Queue */ |
941 | static bool vtd_get_inv_desc(dma_addr_t base_addr, uint32_t offset, | |
942 | VTDInvDesc *inv_desc) | |
943 | { | |
944 | dma_addr_t addr = base_addr + offset * sizeof(*inv_desc); | |
945 | if (dma_memory_read(&address_space_memory, addr, inv_desc, | |
946 | sizeof(*inv_desc))) { | |
947 | VTD_DPRINTF(GENERAL, "error: fail to fetch Invalidation Descriptor " | |
948 | "base_addr 0x%"PRIx64 " offset %"PRIu32, base_addr, offset); | |
949 | inv_desc->lo = 0; | |
950 | inv_desc->hi = 0; | |
951 | ||
952 | return false; | |
953 | } | |
954 | inv_desc->lo = le64_to_cpu(inv_desc->lo); | |
955 | inv_desc->hi = le64_to_cpu(inv_desc->hi); | |
956 | return true; | |
957 | } | |
958 | ||
959 | static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) | |
960 | { | |
961 | if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) || | |
962 | (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) { | |
963 | VTD_DPRINTF(GENERAL, "error: non-zero reserved field in Invalidation " | |
964 | "Wait Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64, | |
965 | inv_desc->hi, inv_desc->lo); | |
966 | return false; | |
967 | } | |
968 | if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) { | |
969 | /* Status Write */ | |
970 | uint32_t status_data = (uint32_t)(inv_desc->lo >> | |
971 | VTD_INV_DESC_WAIT_DATA_SHIFT); | |
972 | ||
973 | assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF)); | |
974 | ||
975 | /* FIXME: need to be masked with HAW? */ | |
976 | dma_addr_t status_addr = inv_desc->hi; | |
977 | VTD_DPRINTF(INV, "status data 0x%x, status addr 0x%"PRIx64, | |
978 | status_data, status_addr); | |
979 | status_data = cpu_to_le32(status_data); | |
980 | if (dma_memory_write(&address_space_memory, status_addr, &status_data, | |
981 | sizeof(status_data))) { | |
982 | VTD_DPRINTF(GENERAL, "error: fail to perform a coherent write"); | |
983 | return false; | |
984 | } | |
985 | } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) { | |
986 | /* Interrupt flag */ | |
987 | VTD_DPRINTF(INV, "Invalidation Wait Descriptor interrupt completion"); | |
988 | vtd_generate_completion_event(s); | |
989 | } else { | |
990 | VTD_DPRINTF(GENERAL, "error: invalid Invalidation Wait Descriptor: " | |
991 | "hi 0x%"PRIx64 " lo 0x%"PRIx64, inv_desc->hi, inv_desc->lo); | |
992 | return false; | |
993 | } | |
994 | return true; | |
995 | } | |
996 | ||
997 | static bool vtd_process_inv_desc(IntelIOMMUState *s) | |
998 | { | |
999 | VTDInvDesc inv_desc; | |
1000 | uint8_t desc_type; | |
1001 | ||
1002 | VTD_DPRINTF(INV, "iq head %"PRIu16, s->iq_head); | |
1003 | if (!vtd_get_inv_desc(s->iq, s->iq_head, &inv_desc)) { | |
1004 | s->iq_last_desc_type = VTD_INV_DESC_NONE; | |
1005 | return false; | |
1006 | } | |
1007 | desc_type = inv_desc.lo & VTD_INV_DESC_TYPE; | |
1008 | /* FIXME: should update at first or at last? */ | |
1009 | s->iq_last_desc_type = desc_type; | |
1010 | ||
1011 | switch (desc_type) { | |
1012 | case VTD_INV_DESC_CC: | |
1013 | VTD_DPRINTF(INV, "Context-cache Invalidate Descriptor hi 0x%"PRIx64 | |
1014 | " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo); | |
1015 | break; | |
1016 | ||
1017 | case VTD_INV_DESC_IOTLB: | |
1018 | VTD_DPRINTF(INV, "IOTLB Invalidate Descriptor hi 0x%"PRIx64 | |
1019 | " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo); | |
1020 | break; | |
1021 | ||
1022 | case VTD_INV_DESC_WAIT: | |
1023 | VTD_DPRINTF(INV, "Invalidation Wait Descriptor hi 0x%"PRIx64 | |
1024 | " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo); | |
1025 | if (!vtd_process_wait_desc(s, &inv_desc)) { | |
1026 | return false; | |
1027 | } | |
1028 | break; | |
1029 | ||
1030 | default: | |
1031 | VTD_DPRINTF(GENERAL, "error: unkonw Invalidation Descriptor type " | |
1032 | "hi 0x%"PRIx64 " lo 0x%"PRIx64 " type %"PRIu8, | |
1033 | inv_desc.hi, inv_desc.lo, desc_type); | |
1034 | return false; | |
1035 | } | |
1036 | s->iq_head++; | |
1037 | if (s->iq_head == s->iq_size) { | |
1038 | s->iq_head = 0; | |
1039 | } | |
1040 | return true; | |
1041 | } | |
1042 | ||
1043 | /* Try to fetch and process more Invalidation Descriptors */ | |
1044 | static void vtd_fetch_inv_desc(IntelIOMMUState *s) | |
1045 | { | |
1046 | VTD_DPRINTF(INV, "fetch Invalidation Descriptors"); | |
1047 | if (s->iq_tail >= s->iq_size) { | |
1048 | /* Detects an invalid Tail pointer */ | |
1049 | VTD_DPRINTF(GENERAL, "error: iq_tail is %"PRIu16 | |
1050 | " while iq_size is %"PRIu16, s->iq_tail, s->iq_size); | |
1051 | vtd_handle_inv_queue_error(s); | |
1052 | return; | |
1053 | } | |
1054 | while (s->iq_head != s->iq_tail) { | |
1055 | if (!vtd_process_inv_desc(s)) { | |
1056 | /* Invalidation Queue Errors */ | |
1057 | vtd_handle_inv_queue_error(s); | |
1058 | break; | |
1059 | } | |
1060 | /* Must update the IQH_REG in time */ | |
1061 | vtd_set_quad_raw(s, DMAR_IQH_REG, | |
1062 | (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) & | |
1063 | VTD_IQH_QH_MASK); | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | /* Handle write to Invalidation Queue Tail Register */ | |
1068 | static void vtd_handle_iqt_write(IntelIOMMUState *s) | |
1069 | { | |
1070 | uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG); | |
1071 | ||
1072 | s->iq_tail = VTD_IQT_QT(val); | |
1073 | VTD_DPRINTF(INV, "set iq tail %"PRIu16, s->iq_tail); | |
1074 | if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) { | |
1075 | /* Process Invalidation Queue here */ | |
1076 | vtd_fetch_inv_desc(s); | |
1077 | } | |
1078 | } | |
1079 | ||
1da12ec4 LT |
1080 | static void vtd_handle_fsts_write(IntelIOMMUState *s) |
1081 | { | |
1082 | uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG); | |
1083 | uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG); | |
1084 | uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE; | |
1085 | ||
1086 | if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) { | |
1087 | vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0); | |
1088 | VTD_DPRINTF(FLOG, "all pending interrupt conditions serviced, clear " | |
1089 | "IP field of FECTL_REG"); | |
1090 | } | |
ed7b8fbc LT |
1091 | /* FIXME: when IQE is Clear, should we try to fetch some Invalidation |
1092 | * Descriptors if there are any when Queued Invalidation is enabled? | |
1093 | */ | |
1da12ec4 LT |
1094 | } |
1095 | ||
1096 | static void vtd_handle_fectl_write(IntelIOMMUState *s) | |
1097 | { | |
1098 | uint32_t fectl_reg; | |
1099 | /* FIXME: when software clears the IM field, check the IP field. But do we | |
1100 | * need to compare the old value and the new value to conclude that | |
1101 | * software clears the IM field? Or just check if the IM field is zero? | |
1102 | */ | |
1103 | fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG); | |
1104 | if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) { | |
1105 | vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG); | |
1106 | vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0); | |
1107 | VTD_DPRINTF(FLOG, "IM field is cleared, generate " | |
1108 | "fault event interrupt"); | |
1109 | } | |
1110 | } | |
1111 | ||
ed7b8fbc LT |
1112 | static void vtd_handle_ics_write(IntelIOMMUState *s) |
1113 | { | |
1114 | uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG); | |
1115 | uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG); | |
1116 | ||
1117 | if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) { | |
1118 | vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0); | |
1119 | VTD_DPRINTF(INV, "pending completion interrupt condition serviced, " | |
1120 | "clear IP field of IECTL_REG"); | |
1121 | } | |
1122 | } | |
1123 | ||
1124 | static void vtd_handle_iectl_write(IntelIOMMUState *s) | |
1125 | { | |
1126 | uint32_t iectl_reg; | |
1127 | /* FIXME: when software clears the IM field, check the IP field. But do we | |
1128 | * need to compare the old value and the new value to conclude that | |
1129 | * software clears the IM field? Or just check if the IM field is zero? | |
1130 | */ | |
1131 | iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG); | |
1132 | if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) { | |
1133 | vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG); | |
1134 | vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0); | |
1135 | VTD_DPRINTF(INV, "IM field is cleared, generate " | |
1136 | "invalidation event interrupt"); | |
1137 | } | |
1138 | } | |
1139 | ||
1da12ec4 LT |
1140 | static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size) |
1141 | { | |
1142 | IntelIOMMUState *s = opaque; | |
1143 | uint64_t val; | |
1144 | ||
1145 | if (addr + size > DMAR_REG_SIZE) { | |
1146 | VTD_DPRINTF(GENERAL, "error: addr outside region: max 0x%"PRIx64 | |
1147 | ", got 0x%"PRIx64 " %d", | |
1148 | (uint64_t)DMAR_REG_SIZE, addr, size); | |
1149 | return (uint64_t)-1; | |
1150 | } | |
1151 | ||
1152 | switch (addr) { | |
1153 | /* Root Table Address Register, 64-bit */ | |
1154 | case DMAR_RTADDR_REG: | |
1155 | if (size == 4) { | |
1156 | val = s->root & ((1ULL << 32) - 1); | |
1157 | } else { | |
1158 | val = s->root; | |
1159 | } | |
1160 | break; | |
1161 | ||
1162 | case DMAR_RTADDR_REG_HI: | |
1163 | assert(size == 4); | |
1164 | val = s->root >> 32; | |
1165 | break; | |
1166 | ||
ed7b8fbc LT |
1167 | /* Invalidation Queue Address Register, 64-bit */ |
1168 | case DMAR_IQA_REG: | |
1169 | val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS); | |
1170 | if (size == 4) { | |
1171 | val = val & ((1ULL << 32) - 1); | |
1172 | } | |
1173 | break; | |
1174 | ||
1175 | case DMAR_IQA_REG_HI: | |
1176 | assert(size == 4); | |
1177 | val = s->iq >> 32; | |
1178 | break; | |
1179 | ||
1da12ec4 LT |
1180 | default: |
1181 | if (size == 4) { | |
1182 | val = vtd_get_long(s, addr); | |
1183 | } else { | |
1184 | val = vtd_get_quad(s, addr); | |
1185 | } | |
1186 | } | |
1187 | VTD_DPRINTF(CSR, "addr 0x%"PRIx64 " size %d val 0x%"PRIx64, | |
1188 | addr, size, val); | |
1189 | return val; | |
1190 | } | |
1191 | ||
1192 | static void vtd_mem_write(void *opaque, hwaddr addr, | |
1193 | uint64_t val, unsigned size) | |
1194 | { | |
1195 | IntelIOMMUState *s = opaque; | |
1196 | ||
1197 | if (addr + size > DMAR_REG_SIZE) { | |
1198 | VTD_DPRINTF(GENERAL, "error: addr outside region: max 0x%"PRIx64 | |
1199 | ", got 0x%"PRIx64 " %d", | |
1200 | (uint64_t)DMAR_REG_SIZE, addr, size); | |
1201 | return; | |
1202 | } | |
1203 | ||
1204 | switch (addr) { | |
1205 | /* Global Command Register, 32-bit */ | |
1206 | case DMAR_GCMD_REG: | |
1207 | VTD_DPRINTF(CSR, "DMAR_GCMD_REG write addr 0x%"PRIx64 | |
1208 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1209 | vtd_set_long(s, addr, val); | |
1210 | vtd_handle_gcmd_write(s); | |
1211 | break; | |
1212 | ||
1213 | /* Context Command Register, 64-bit */ | |
1214 | case DMAR_CCMD_REG: | |
1215 | VTD_DPRINTF(CSR, "DMAR_CCMD_REG write addr 0x%"PRIx64 | |
1216 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1217 | if (size == 4) { | |
1218 | vtd_set_long(s, addr, val); | |
1219 | } else { | |
1220 | vtd_set_quad(s, addr, val); | |
1221 | vtd_handle_ccmd_write(s); | |
1222 | } | |
1223 | break; | |
1224 | ||
1225 | case DMAR_CCMD_REG_HI: | |
1226 | VTD_DPRINTF(CSR, "DMAR_CCMD_REG_HI write addr 0x%"PRIx64 | |
1227 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1228 | assert(size == 4); | |
1229 | vtd_set_long(s, addr, val); | |
1230 | vtd_handle_ccmd_write(s); | |
1231 | break; | |
1232 | ||
1233 | /* IOTLB Invalidation Register, 64-bit */ | |
1234 | case DMAR_IOTLB_REG: | |
1235 | VTD_DPRINTF(INV, "DMAR_IOTLB_REG write addr 0x%"PRIx64 | |
1236 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1237 | if (size == 4) { | |
1238 | vtd_set_long(s, addr, val); | |
1239 | } else { | |
1240 | vtd_set_quad(s, addr, val); | |
1241 | vtd_handle_iotlb_write(s); | |
1242 | } | |
1243 | break; | |
1244 | ||
1245 | case DMAR_IOTLB_REG_HI: | |
1246 | VTD_DPRINTF(INV, "DMAR_IOTLB_REG_HI write addr 0x%"PRIx64 | |
1247 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1248 | assert(size == 4); | |
1249 | vtd_set_long(s, addr, val); | |
1250 | vtd_handle_iotlb_write(s); | |
1251 | break; | |
1252 | ||
1253 | /* Fault Status Register, 32-bit */ | |
1254 | case DMAR_FSTS_REG: | |
1255 | VTD_DPRINTF(FLOG, "DMAR_FSTS_REG write addr 0x%"PRIx64 | |
1256 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1257 | assert(size == 4); | |
1258 | vtd_set_long(s, addr, val); | |
1259 | vtd_handle_fsts_write(s); | |
1260 | break; | |
1261 | ||
1262 | /* Fault Event Control Register, 32-bit */ | |
1263 | case DMAR_FECTL_REG: | |
1264 | VTD_DPRINTF(FLOG, "DMAR_FECTL_REG write addr 0x%"PRIx64 | |
1265 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1266 | assert(size == 4); | |
1267 | vtd_set_long(s, addr, val); | |
1268 | vtd_handle_fectl_write(s); | |
1269 | break; | |
1270 | ||
1271 | /* Fault Event Data Register, 32-bit */ | |
1272 | case DMAR_FEDATA_REG: | |
1273 | VTD_DPRINTF(FLOG, "DMAR_FEDATA_REG write addr 0x%"PRIx64 | |
1274 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1275 | assert(size == 4); | |
1276 | vtd_set_long(s, addr, val); | |
1277 | break; | |
1278 | ||
1279 | /* Fault Event Address Register, 32-bit */ | |
1280 | case DMAR_FEADDR_REG: | |
1281 | VTD_DPRINTF(FLOG, "DMAR_FEADDR_REG write addr 0x%"PRIx64 | |
1282 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1283 | assert(size == 4); | |
1284 | vtd_set_long(s, addr, val); | |
1285 | break; | |
1286 | ||
1287 | /* Fault Event Upper Address Register, 32-bit */ | |
1288 | case DMAR_FEUADDR_REG: | |
1289 | VTD_DPRINTF(FLOG, "DMAR_FEUADDR_REG write addr 0x%"PRIx64 | |
1290 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1291 | assert(size == 4); | |
1292 | vtd_set_long(s, addr, val); | |
1293 | break; | |
1294 | ||
1295 | /* Protected Memory Enable Register, 32-bit */ | |
1296 | case DMAR_PMEN_REG: | |
1297 | VTD_DPRINTF(CSR, "DMAR_PMEN_REG write addr 0x%"PRIx64 | |
1298 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1299 | assert(size == 4); | |
1300 | vtd_set_long(s, addr, val); | |
1301 | break; | |
1302 | ||
1303 | /* Root Table Address Register, 64-bit */ | |
1304 | case DMAR_RTADDR_REG: | |
1305 | VTD_DPRINTF(CSR, "DMAR_RTADDR_REG write addr 0x%"PRIx64 | |
1306 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1307 | if (size == 4) { | |
1308 | vtd_set_long(s, addr, val); | |
1309 | } else { | |
1310 | vtd_set_quad(s, addr, val); | |
1311 | } | |
1312 | break; | |
1313 | ||
1314 | case DMAR_RTADDR_REG_HI: | |
1315 | VTD_DPRINTF(CSR, "DMAR_RTADDR_REG_HI write addr 0x%"PRIx64 | |
1316 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1317 | assert(size == 4); | |
1318 | vtd_set_long(s, addr, val); | |
1319 | break; | |
1320 | ||
ed7b8fbc LT |
1321 | /* Invalidation Queue Tail Register, 64-bit */ |
1322 | case DMAR_IQT_REG: | |
1323 | VTD_DPRINTF(INV, "DMAR_IQT_REG write addr 0x%"PRIx64 | |
1324 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1325 | if (size == 4) { | |
1326 | vtd_set_long(s, addr, val); | |
1327 | } else { | |
1328 | vtd_set_quad(s, addr, val); | |
1329 | } | |
1330 | vtd_handle_iqt_write(s); | |
1331 | break; | |
1332 | ||
1333 | case DMAR_IQT_REG_HI: | |
1334 | VTD_DPRINTF(INV, "DMAR_IQT_REG_HI write addr 0x%"PRIx64 | |
1335 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1336 | assert(size == 4); | |
1337 | vtd_set_long(s, addr, val); | |
1338 | /* 19:63 of IQT_REG is RsvdZ, do nothing here */ | |
1339 | break; | |
1340 | ||
1341 | /* Invalidation Queue Address Register, 64-bit */ | |
1342 | case DMAR_IQA_REG: | |
1343 | VTD_DPRINTF(INV, "DMAR_IQA_REG write addr 0x%"PRIx64 | |
1344 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1345 | if (size == 4) { | |
1346 | vtd_set_long(s, addr, val); | |
1347 | } else { | |
1348 | vtd_set_quad(s, addr, val); | |
1349 | } | |
1350 | break; | |
1351 | ||
1352 | case DMAR_IQA_REG_HI: | |
1353 | VTD_DPRINTF(INV, "DMAR_IQA_REG_HI write addr 0x%"PRIx64 | |
1354 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1355 | assert(size == 4); | |
1356 | vtd_set_long(s, addr, val); | |
1357 | break; | |
1358 | ||
1359 | /* Invalidation Completion Status Register, 32-bit */ | |
1360 | case DMAR_ICS_REG: | |
1361 | VTD_DPRINTF(INV, "DMAR_ICS_REG write addr 0x%"PRIx64 | |
1362 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1363 | assert(size == 4); | |
1364 | vtd_set_long(s, addr, val); | |
1365 | vtd_handle_ics_write(s); | |
1366 | break; | |
1367 | ||
1368 | /* Invalidation Event Control Register, 32-bit */ | |
1369 | case DMAR_IECTL_REG: | |
1370 | VTD_DPRINTF(INV, "DMAR_IECTL_REG write addr 0x%"PRIx64 | |
1371 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1372 | assert(size == 4); | |
1373 | vtd_set_long(s, addr, val); | |
1374 | vtd_handle_iectl_write(s); | |
1375 | break; | |
1376 | ||
1377 | /* Invalidation Event Data Register, 32-bit */ | |
1378 | case DMAR_IEDATA_REG: | |
1379 | VTD_DPRINTF(INV, "DMAR_IEDATA_REG write addr 0x%"PRIx64 | |
1380 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1381 | assert(size == 4); | |
1382 | vtd_set_long(s, addr, val); | |
1383 | break; | |
1384 | ||
1385 | /* Invalidation Event Address Register, 32-bit */ | |
1386 | case DMAR_IEADDR_REG: | |
1387 | VTD_DPRINTF(INV, "DMAR_IEADDR_REG write addr 0x%"PRIx64 | |
1388 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1389 | assert(size == 4); | |
1390 | vtd_set_long(s, addr, val); | |
1391 | break; | |
1392 | ||
1393 | /* Invalidation Event Upper Address Register, 32-bit */ | |
1394 | case DMAR_IEUADDR_REG: | |
1395 | VTD_DPRINTF(INV, "DMAR_IEUADDR_REG write addr 0x%"PRIx64 | |
1396 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1397 | assert(size == 4); | |
1398 | vtd_set_long(s, addr, val); | |
1399 | break; | |
1400 | ||
1da12ec4 LT |
1401 | /* Fault Recording Registers, 128-bit */ |
1402 | case DMAR_FRCD_REG_0_0: | |
1403 | VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_0 write addr 0x%"PRIx64 | |
1404 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1405 | if (size == 4) { | |
1406 | vtd_set_long(s, addr, val); | |
1407 | } else { | |
1408 | vtd_set_quad(s, addr, val); | |
1409 | } | |
1410 | break; | |
1411 | ||
1412 | case DMAR_FRCD_REG_0_1: | |
1413 | VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_1 write addr 0x%"PRIx64 | |
1414 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1415 | assert(size == 4); | |
1416 | vtd_set_long(s, addr, val); | |
1417 | break; | |
1418 | ||
1419 | case DMAR_FRCD_REG_0_2: | |
1420 | VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_2 write addr 0x%"PRIx64 | |
1421 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1422 | if (size == 4) { | |
1423 | vtd_set_long(s, addr, val); | |
1424 | } else { | |
1425 | vtd_set_quad(s, addr, val); | |
1426 | /* May clear bit 127 (Fault), update PPF */ | |
1427 | vtd_update_fsts_ppf(s); | |
1428 | } | |
1429 | break; | |
1430 | ||
1431 | case DMAR_FRCD_REG_0_3: | |
1432 | VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_3 write addr 0x%"PRIx64 | |
1433 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1434 | assert(size == 4); | |
1435 | vtd_set_long(s, addr, val); | |
1436 | /* May clear bit 127 (Fault), update PPF */ | |
1437 | vtd_update_fsts_ppf(s); | |
1438 | break; | |
1439 | ||
1440 | default: | |
1441 | VTD_DPRINTF(GENERAL, "error: unhandled reg write addr 0x%"PRIx64 | |
1442 | ", size %d, val 0x%"PRIx64, addr, size, val); | |
1443 | if (size == 4) { | |
1444 | vtd_set_long(s, addr, val); | |
1445 | } else { | |
1446 | vtd_set_quad(s, addr, val); | |
1447 | } | |
1448 | } | |
1449 | } | |
1450 | ||
1451 | static IOMMUTLBEntry vtd_iommu_translate(MemoryRegion *iommu, hwaddr addr, | |
1452 | bool is_write) | |
1453 | { | |
1454 | VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); | |
1455 | IntelIOMMUState *s = vtd_as->iommu_state; | |
1456 | uint8_t bus_num = vtd_as->bus_num; | |
1457 | uint8_t devfn = vtd_as->devfn; | |
1458 | IOMMUTLBEntry ret = { | |
1459 | .target_as = &address_space_memory, | |
1460 | .iova = addr, | |
1461 | .translated_addr = 0, | |
1462 | .addr_mask = ~(hwaddr)0, | |
1463 | .perm = IOMMU_NONE, | |
1464 | }; | |
1465 | ||
1466 | if (!s->dmar_enabled) { | |
1467 | /* DMAR disabled, passthrough, use 4k-page*/ | |
1468 | ret.iova = addr & VTD_PAGE_MASK_4K; | |
1469 | ret.translated_addr = addr & VTD_PAGE_MASK_4K; | |
1470 | ret.addr_mask = ~VTD_PAGE_MASK_4K; | |
1471 | ret.perm = IOMMU_RW; | |
1472 | return ret; | |
1473 | } | |
1474 | ||
1475 | vtd_do_iommu_translate(s, bus_num, devfn, addr, is_write, &ret); | |
1476 | ||
1477 | VTD_DPRINTF(MMU, | |
1478 | "bus %"PRIu8 " slot %"PRIu8 " func %"PRIu8 " devfn %"PRIu8 | |
1479 | " gpa 0x%"PRIx64 " hpa 0x%"PRIx64, bus_num, | |
1480 | VTD_PCI_SLOT(devfn), VTD_PCI_FUNC(devfn), devfn, addr, | |
1481 | ret.translated_addr); | |
1482 | return ret; | |
1483 | } | |
1484 | ||
1485 | static const VMStateDescription vtd_vmstate = { | |
1486 | .name = "iommu-intel", | |
1487 | .unmigratable = 1, | |
1488 | }; | |
1489 | ||
1490 | static const MemoryRegionOps vtd_mem_ops = { | |
1491 | .read = vtd_mem_read, | |
1492 | .write = vtd_mem_write, | |
1493 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1494 | .impl = { | |
1495 | .min_access_size = 4, | |
1496 | .max_access_size = 8, | |
1497 | }, | |
1498 | .valid = { | |
1499 | .min_access_size = 4, | |
1500 | .max_access_size = 8, | |
1501 | }, | |
1502 | }; | |
1503 | ||
1504 | static Property vtd_properties[] = { | |
1505 | DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0), | |
1506 | DEFINE_PROP_END_OF_LIST(), | |
1507 | }; | |
1508 | ||
1509 | /* Do the initialization. It will also be called when reset, so pay | |
1510 | * attention when adding new initialization stuff. | |
1511 | */ | |
1512 | static void vtd_init(IntelIOMMUState *s) | |
1513 | { | |
1514 | memset(s->csr, 0, DMAR_REG_SIZE); | |
1515 | memset(s->wmask, 0, DMAR_REG_SIZE); | |
1516 | memset(s->w1cmask, 0, DMAR_REG_SIZE); | |
1517 | memset(s->womask, 0, DMAR_REG_SIZE); | |
1518 | ||
1519 | s->iommu_ops.translate = vtd_iommu_translate; | |
1520 | s->root = 0; | |
1521 | s->root_extended = false; | |
1522 | s->dmar_enabled = false; | |
1523 | s->iq_head = 0; | |
1524 | s->iq_tail = 0; | |
1525 | s->iq = 0; | |
1526 | s->iq_size = 0; | |
1527 | s->qi_enabled = false; | |
1528 | s->iq_last_desc_type = VTD_INV_DESC_NONE; | |
1529 | s->next_frcd_reg = 0; | |
1530 | s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_CAP_MGAW | | |
1531 | VTD_CAP_SAGAW; | |
ed7b8fbc | 1532 | s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO; |
1da12ec4 LT |
1533 | |
1534 | /* Define registers with default values and bit semantics */ | |
1535 | vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0); | |
1536 | vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0); | |
1537 | vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0); | |
1538 | vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0); | |
1539 | vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL); | |
1540 | vtd_define_long(s, DMAR_GSTS_REG, 0, 0, 0); | |
1541 | vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffff000ULL, 0); | |
1542 | vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0); | |
1543 | vtd_define_quad_wo(s, DMAR_CCMD_REG, 0x3ffff0000ULL); | |
1544 | ||
1545 | /* Advanced Fault Logging not supported */ | |
1546 | vtd_define_long(s, DMAR_FSTS_REG, 0, 0, 0x11UL); | |
1547 | vtd_define_long(s, DMAR_FECTL_REG, 0x80000000UL, 0x80000000UL, 0); | |
1548 | vtd_define_long(s, DMAR_FEDATA_REG, 0, 0x0000ffffUL, 0); | |
1549 | vtd_define_long(s, DMAR_FEADDR_REG, 0, 0xfffffffcUL, 0); | |
1550 | ||
1551 | /* Treated as RsvdZ when EIM in ECAP_REG is not supported | |
1552 | * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0); | |
1553 | */ | |
1554 | vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0, 0); | |
1555 | ||
1556 | /* Treated as RO for implementations that PLMR and PHMR fields reported | |
1557 | * as Clear in the CAP_REG. | |
1558 | * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0); | |
1559 | */ | |
1560 | vtd_define_long(s, DMAR_PMEN_REG, 0, 0, 0); | |
1561 | ||
ed7b8fbc LT |
1562 | vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0); |
1563 | vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0); | |
1564 | vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff007ULL, 0); | |
1565 | vtd_define_long(s, DMAR_ICS_REG, 0, 0, 0x1UL); | |
1566 | vtd_define_long(s, DMAR_IECTL_REG, 0x80000000UL, 0x80000000UL, 0); | |
1567 | vtd_define_long(s, DMAR_IEDATA_REG, 0, 0xffffffffUL, 0); | |
1568 | vtd_define_long(s, DMAR_IEADDR_REG, 0, 0xfffffffcUL, 0); | |
1569 | /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */ | |
1570 | vtd_define_long(s, DMAR_IEUADDR_REG, 0, 0, 0); | |
1571 | ||
1da12ec4 LT |
1572 | /* IOTLB registers */ |
1573 | vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0); | |
1574 | vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0); | |
1575 | vtd_define_quad_wo(s, DMAR_IVA_REG, 0xfffffffffffff07fULL); | |
1576 | ||
1577 | /* Fault Recording Registers, 128-bit */ | |
1578 | vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0); | |
1579 | vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL); | |
1580 | } | |
1581 | ||
1582 | /* Should not reset address_spaces when reset because devices will still use | |
1583 | * the address space they got at first (won't ask the bus again). | |
1584 | */ | |
1585 | static void vtd_reset(DeviceState *dev) | |
1586 | { | |
1587 | IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev); | |
1588 | ||
1589 | VTD_DPRINTF(GENERAL, ""); | |
1590 | vtd_init(s); | |
1591 | } | |
1592 | ||
1593 | static void vtd_realize(DeviceState *dev, Error **errp) | |
1594 | { | |
1595 | IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev); | |
1596 | ||
1597 | VTD_DPRINTF(GENERAL, ""); | |
1598 | memset(s->address_spaces, 0, sizeof(s->address_spaces)); | |
1599 | memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s, | |
1600 | "intel_iommu", DMAR_REG_SIZE); | |
1601 | sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem); | |
1602 | vtd_init(s); | |
1603 | } | |
1604 | ||
1605 | static void vtd_class_init(ObjectClass *klass, void *data) | |
1606 | { | |
1607 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1608 | ||
1609 | dc->reset = vtd_reset; | |
1610 | dc->realize = vtd_realize; | |
1611 | dc->vmsd = &vtd_vmstate; | |
1612 | dc->props = vtd_properties; | |
1613 | } | |
1614 | ||
1615 | static const TypeInfo vtd_info = { | |
1616 | .name = TYPE_INTEL_IOMMU_DEVICE, | |
1617 | .parent = TYPE_SYS_BUS_DEVICE, | |
1618 | .instance_size = sizeof(IntelIOMMUState), | |
1619 | .class_init = vtd_class_init, | |
1620 | }; | |
1621 | ||
1622 | static void vtd_register_types(void) | |
1623 | { | |
1624 | VTD_DPRINTF(GENERAL, ""); | |
1625 | type_register_static(&vtd_info); | |
1626 | } | |
1627 | ||
1628 | type_init(vtd_register_types) |