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1/*
2 * KVM in-kernel PIC (i8259) support
3 *
4 * Copyright (c) 2011 Siemens AG
5 *
6 * Authors:
7 * Jan Kiszka <jan.kiszka@siemens.com>
8 *
9 * This work is licensed under the terms of the GNU GPL version 2.
10 * See the COPYING file in the top-level directory.
11 */
0b8fa32f 12
b6a0aa05 13#include "qemu/osdep.h"
0d09e41a 14#include "hw/isa/i8259_internal.h"
852c27e2 15#include "hw/intc/i8259.h"
0b8fa32f 16#include "qemu/module.h"
0d09e41a 17#include "hw/i386/apic_internal.h"
64552b6b 18#include "hw/irq.h"
9c17d615 19#include "sysemu/kvm.h"
10b61882 20
49fdb0c1 21#define TYPE_KVM_I8259 "kvm-i8259"
d2628b7d
AF
22#define KVM_PIC_CLASS(class) \
23 OBJECT_CLASS_CHECK(KVMPICClass, (class), TYPE_KVM_I8259)
24#define KVM_PIC_GET_CLASS(obj) \
25 OBJECT_GET_CLASS(KVMPICClass, (obj), TYPE_KVM_I8259)
26
27/**
28 * KVMPICClass:
29 * @parent_realize: The parent's realizefn.
30 */
31typedef struct KVMPICClass {
32 PICCommonClass parent_class;
33
34 DeviceRealize parent_realize;
35} KVMPICClass;
49fdb0c1 36
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37static void kvm_pic_get(PICCommonState *s)
38{
39 struct kvm_irqchip chip;
40 struct kvm_pic_state *kpic;
41 int ret;
42
43 chip.chip_id = s->master ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC_SLAVE;
44 ret = kvm_vm_ioctl(kvm_state, KVM_GET_IRQCHIP, &chip);
45 if (ret < 0) {
46 fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(ret));
47 abort();
48 }
49
50 kpic = &chip.chip.pic;
51
52 s->last_irr = kpic->last_irr;
53 s->irr = kpic->irr;
54 s->imr = kpic->imr;
55 s->isr = kpic->isr;
56 s->priority_add = kpic->priority_add;
57 s->irq_base = kpic->irq_base;
58 s->read_reg_select = kpic->read_reg_select;
59 s->poll = kpic->poll;
60 s->special_mask = kpic->special_mask;
61 s->init_state = kpic->init_state;
62 s->auto_eoi = kpic->auto_eoi;
63 s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
64 s->special_fully_nested_mode = kpic->special_fully_nested_mode;
65 s->init4 = kpic->init4;
66 s->elcr = kpic->elcr;
67 s->elcr_mask = kpic->elcr_mask;
68}
69
70static void kvm_pic_put(PICCommonState *s)
71{
72 struct kvm_irqchip chip;
73 struct kvm_pic_state *kpic;
74 int ret;
75
76 chip.chip_id = s->master ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC_SLAVE;
77
78 kpic = &chip.chip.pic;
79
80 kpic->last_irr = s->last_irr;
81 kpic->irr = s->irr;
82 kpic->imr = s->imr;
83 kpic->isr = s->isr;
84 kpic->priority_add = s->priority_add;
85 kpic->irq_base = s->irq_base;
86 kpic->read_reg_select = s->read_reg_select;
87 kpic->poll = s->poll;
88 kpic->special_mask = s->special_mask;
89 kpic->init_state = s->init_state;
90 kpic->auto_eoi = s->auto_eoi;
91 kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
92 kpic->special_fully_nested_mode = s->special_fully_nested_mode;
93 kpic->init4 = s->init4;
94 kpic->elcr = s->elcr;
95 kpic->elcr_mask = s->elcr_mask;
96
97 ret = kvm_vm_ioctl(kvm_state, KVM_SET_IRQCHIP, &chip);
98 if (ret < 0) {
89284736 99 fprintf(stderr, "KVM_SET_IRQCHIP failed: %s\n", strerror(ret));
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100 abort();
101 }
102}
103
104static void kvm_pic_reset(DeviceState *dev)
105{
29bb5317 106 PICCommonState *s = PIC_COMMON(dev);
10b61882 107
10b61882 108 s->elcr = 0;
aa24822b 109 pic_reset_common(s);
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110
111 kvm_pic_put(s);
112}
113
114static void kvm_pic_set_irq(void *opaque, int irq, int level)
115{
116 int delivered;
117
e267d164 118 pic_stat_update_irq(irq, level);
3889c3fa 119 delivered = kvm_set_irq(kvm_state, irq, level);
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120 apic_report_irq_delivered(delivered);
121}
122
d2628b7d 123static void kvm_pic_realize(DeviceState *dev, Error **errp)
10b61882 124{
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125 PICCommonState *s = PIC_COMMON(dev);
126 KVMPICClass *kpc = KVM_PIC_GET_CLASS(dev);
127
257a7430
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128 memory_region_init_io(&s->base_io, OBJECT(dev), NULL, NULL, "kvm-pic", 2);
129 memory_region_init_io(&s->elcr_io, OBJECT(dev), NULL, NULL, "kvm-elcr", 1);
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130
131 kpc->parent_realize(dev, errp);
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132}
133
134qemu_irq *kvm_i8259_init(ISABus *bus)
135{
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136 i8259_init_chip(TYPE_KVM_I8259, bus, true);
137 i8259_init_chip(TYPE_KVM_I8259, bus, false);
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138
139 return qemu_allocate_irqs(kvm_pic_set_irq, NULL, ISA_NUM_IRQS);
140}
141
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142static void kvm_i8259_class_init(ObjectClass *klass, void *data)
143{
d2628b7d 144 KVMPICClass *kpc = KVM_PIC_CLASS(klass);
8f04ee08 145 PICCommonClass *k = PIC_COMMON_CLASS(klass);
39bffca2 146 DeviceClass *dc = DEVICE_CLASS(klass);
8f04ee08 147
39bffca2 148 dc->reset = kvm_pic_reset;
bf853881 149 device_class_set_parent_realize(dc, kvm_pic_realize, &kpc->parent_realize);
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150 k->pre_save = kvm_pic_get;
151 k->post_load = kvm_pic_put;
152}
153
8c43a6f0 154static const TypeInfo kvm_i8259_info = {
49fdb0c1 155 .name = TYPE_KVM_I8259,
39bffca2 156 .parent = TYPE_PIC_COMMON,
4cafe606 157 .instance_size = sizeof(PICCommonState),
8f04ee08 158 .class_init = kvm_i8259_class_init,
d2628b7d 159 .class_size = sizeof(KVMPICClass),
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160};
161
83f7d43a 162static void kvm_pic_register_types(void)
10b61882 163{
39bffca2 164 type_register_static(&kvm_i8259_info);
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165}
166
83f7d43a 167type_init(kvm_pic_register_types)