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610626af AL |
1 | /* |
2 | * ioapic.c IOAPIC emulation logic | |
3 | * | |
4 | * Copyright (c) 2004-2005 Fabrice Bellard | |
5 | * | |
6 | * Split the ioapic logic from apic.c | |
7 | * Xiantao Zhang <xiantao.zhang@intel.com> | |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
610626af AL |
21 | */ |
22 | ||
b6a0aa05 | 23 | #include "qemu/osdep.h" |
11ab69d6 | 24 | #include "qapi/error.h" |
6bde8fd6 | 25 | #include "monitor/monitor.h" |
d613f8cc | 26 | #include "hw/i386/apic.h" |
0d09e41a PB |
27 | #include "hw/i386/ioapic.h" |
28 | #include "hw/i386/ioapic_internal.h" | |
852c27e2 PB |
29 | #include "hw/i386/x86.h" |
30 | #include "hw/intc/i8259.h" | |
455e17a1 | 31 | #include "hw/pci/msi.h" |
a27bd6c7 | 32 | #include "hw/qdev-properties.h" |
15eafc2e | 33 | #include "sysemu/kvm.h" |
46517dd4 | 34 | #include "sysemu/sysemu.h" |
cb135f59 | 35 | #include "hw/i386/apic-msidef.h" |
e3d9c925 | 36 | #include "hw/i386/x86-iommu.h" |
e5074b38 | 37 | #include "trace.h" |
610626af | 38 | |
15eafc2e PB |
39 | #define APIC_DELIVERY_MODE_SHIFT 8 |
40 | #define APIC_POLARITY_SHIFT 14 | |
41 | #define APIC_TRIG_MODE_SHIFT 15 | |
42 | ||
244ac3af | 43 | static IOAPICCommonState *ioapics[MAX_IOAPICS]; |
0280b571 | 44 | |
db0f8888 XZ |
45 | /* global variable from ioapic_common.c */ |
46 | extern int ioapic_no; | |
47 | ||
c15fa0be PX |
48 | struct ioapic_entry_info { |
49 | /* fields parsed from IOAPIC entries */ | |
50 | uint8_t masked; | |
51 | uint8_t trig_mode; | |
52 | uint16_t dest_idx; | |
53 | uint8_t dest_mode; | |
54 | uint8_t delivery_mode; | |
55 | uint8_t vector; | |
56 | ||
57 | /* MSI message generated from above parsed fields */ | |
58 | uint32_t addr; | |
59 | uint32_t data; | |
60 | }; | |
61 | ||
62 | static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info) | |
63 | { | |
64 | memset(info, 0, sizeof(*info)); | |
65 | info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1; | |
66 | info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1; | |
67 | /* | |
68 | * By default, this would be dest_id[8] + reserved[8]. When IR | |
69 | * is enabled, this would be interrupt_index[15] + | |
70 | * interrupt_format[1]. This field never means anything, but | |
71 | * only used to generate corresponding MSI. | |
72 | */ | |
73 | info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff; | |
74 | info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; | |
75 | info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \ | |
76 | & IOAPIC_DM_MASK; | |
77 | if (info->delivery_mode == IOAPIC_DM_EXTINT) { | |
78 | info->vector = pic_read_irq(isa_pic); | |
79 | } else { | |
80 | info->vector = entry & IOAPIC_VECTOR_MASK; | |
81 | } | |
82 | ||
83 | info->addr = APIC_DEFAULT_ADDRESS | \ | |
84 | (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \ | |
85 | (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT); | |
86 | info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \ | |
87 | (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \ | |
88 | (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT); | |
89 | } | |
90 | ||
244ac3af | 91 | static void ioapic_service(IOAPICCommonState *s) |
610626af | 92 | { |
f0bb276b | 93 | AddressSpace *ioapic_as = X86_MACHINE(qdev_get_machine())->ioapic_as; |
c15fa0be | 94 | struct ioapic_entry_info info; |
610626af | 95 | uint8_t i; |
610626af AL |
96 | uint32_t mask; |
97 | uint64_t entry; | |
610626af AL |
98 | |
99 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
100 | mask = 1 << i; | |
101 | if (s->irr & mask) { | |
15eafc2e PB |
102 | int coalesce = 0; |
103 | ||
610626af | 104 | entry = s->ioredtbl[i]; |
c15fa0be PX |
105 | ioapic_entry_parse(entry, &info); |
106 | if (!info.masked) { | |
107 | if (info.trig_mode == IOAPIC_TRIGGER_EDGE) { | |
610626af | 108 | s->irr &= ~mask; |
0280b571 | 109 | } else { |
15eafc2e | 110 | coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR; |
e5074b38 | 111 | trace_ioapic_set_remote_irr(i); |
0280b571 JK |
112 | s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR; |
113 | } | |
c15fa0be | 114 | |
f99b86b9 PX |
115 | if (coalesce) { |
116 | /* We are level triggered interrupts, and the | |
117 | * guest should be still working on previous one, | |
118 | * so skip it. */ | |
119 | continue; | |
120 | } | |
121 | ||
15eafc2e PB |
122 | #ifdef CONFIG_KVM |
123 | if (kvm_irqchip_is_split()) { | |
c15fa0be | 124 | if (info.trig_mode == IOAPIC_TRIGGER_EDGE) { |
15eafc2e PB |
125 | kvm_set_irq(kvm_state, i, 1); |
126 | kvm_set_irq(kvm_state, i, 0); | |
127 | } else { | |
f99b86b9 | 128 | kvm_set_irq(kvm_state, i, 1); |
15eafc2e PB |
129 | } |
130 | continue; | |
131 | } | |
15eafc2e | 132 | #endif |
f99b86b9 | 133 | |
cb135f59 PX |
134 | /* No matter whether IR is enabled, we translate |
135 | * the IOAPIC message into a MSI one, and its | |
136 | * address space will decide whether we need a | |
137 | * translation. */ | |
c15fa0be | 138 | stl_le_phys(ioapic_as, info.addr, info.data); |
610626af AL |
139 | } |
140 | } | |
141 | } | |
142 | } | |
143 | ||
958a01da VK |
144 | #define SUCCESSIVE_IRQ_MAX_COUNT 10000 |
145 | ||
146 | static void delayed_ioapic_service_cb(void *opaque) | |
147 | { | |
148 | IOAPICCommonState *s = opaque; | |
149 | ||
150 | ioapic_service(s); | |
151 | } | |
152 | ||
7d0500c4 | 153 | static void ioapic_set_irq(void *opaque, int vector, int level) |
610626af | 154 | { |
244ac3af | 155 | IOAPICCommonState *s = opaque; |
610626af AL |
156 | |
157 | /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps | |
158 | * to GSI 2. GSI maps to ioapic 1-1. This is not | |
159 | * the cleanest way of doing it but it should work. */ | |
160 | ||
a2e6ffab | 161 | trace_ioapic_set_irq(vector, level); |
cce5405e | 162 | ioapic_stat_update_irq(s, vector, level); |
1f5e71a8 | 163 | if (vector == 0) { |
610626af | 164 | vector = 2; |
1f5e71a8 | 165 | } |
960a479f | 166 | if (vector < IOAPIC_NUM_PINS) { |
610626af AL |
167 | uint32_t mask = 1 << vector; |
168 | uint64_t entry = s->ioredtbl[vector]; | |
169 | ||
1f5e71a8 JK |
170 | if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) == |
171 | IOAPIC_TRIGGER_LEVEL) { | |
610626af AL |
172 | /* level triggered */ |
173 | if (level) { | |
174 | s->irr |= mask; | |
c5955a56 PB |
175 | if (!(entry & IOAPIC_LVT_REMOTE_IRR)) { |
176 | ioapic_service(s); | |
177 | } | |
610626af AL |
178 | } else { |
179 | s->irr &= ~mask; | |
180 | } | |
181 | } else { | |
47f7be39 JK |
182 | /* According to the 82093AA manual, we must ignore edge requests |
183 | * if the input pin is masked. */ | |
184 | if (level && !(entry & IOAPIC_LVT_MASKED)) { | |
610626af AL |
185 | s->irr |= mask; |
186 | ioapic_service(s); | |
187 | } | |
188 | } | |
189 | } | |
190 | } | |
191 | ||
15eafc2e PB |
192 | static void ioapic_update_kvm_routes(IOAPICCommonState *s) |
193 | { | |
194 | #ifdef CONFIG_KVM | |
195 | int i; | |
196 | ||
197 | if (kvm_irqchip_is_split()) { | |
198 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
15eafc2e | 199 | MSIMessage msg; |
c15fa0be PX |
200 | struct ioapic_entry_info info; |
201 | ioapic_entry_parse(s->ioredtbl[i], &info); | |
be1927c9 JK |
202 | if (!info.masked) { |
203 | msg.address = info.addr; | |
204 | msg.data = info.data; | |
205 | kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL); | |
206 | } | |
15eafc2e PB |
207 | } |
208 | kvm_irqchip_commit_routes(kvm_state); | |
209 | } | |
210 | #endif | |
211 | } | |
212 | ||
e3d9c925 PX |
213 | #ifdef CONFIG_KVM |
214 | static void ioapic_iec_notifier(void *private, bool global, | |
215 | uint32_t index, uint32_t mask) | |
216 | { | |
217 | IOAPICCommonState *s = (IOAPICCommonState *)private; | |
218 | /* For simplicity, we just update all the routes */ | |
219 | ioapic_update_kvm_routes(s); | |
220 | } | |
221 | #endif | |
222 | ||
0280b571 JK |
223 | void ioapic_eoi_broadcast(int vector) |
224 | { | |
244ac3af | 225 | IOAPICCommonState *s; |
0280b571 JK |
226 | uint64_t entry; |
227 | int i, n; | |
228 | ||
e5074b38 PX |
229 | trace_ioapic_eoi_broadcast(vector); |
230 | ||
0280b571 JK |
231 | for (i = 0; i < MAX_IOAPICS; i++) { |
232 | s = ioapics[i]; | |
233 | if (!s) { | |
234 | continue; | |
235 | } | |
236 | for (n = 0; n < IOAPIC_NUM_PINS; n++) { | |
237 | entry = s->ioredtbl[n]; | |
958a01da VK |
238 | |
239 | if ((entry & IOAPIC_VECTOR_MASK) != vector || | |
240 | ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) != IOAPIC_TRIGGER_LEVEL) { | |
241 | continue; | |
242 | } | |
243 | ||
244 | if (!(entry & IOAPIC_LVT_REMOTE_IRR)) { | |
245 | continue; | |
246 | } | |
247 | ||
248 | trace_ioapic_clear_remote_irr(n, vector); | |
249 | s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR; | |
250 | ||
251 | if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) { | |
03f990a5 LQ |
252 | ++s->irq_eoi[n]; |
253 | if (s->irq_eoi[n] >= SUCCESSIVE_IRQ_MAX_COUNT) { | |
958a01da VK |
254 | /* |
255 | * Real hardware does not deliver the interrupt immediately | |
256 | * during eoi broadcast, and this lets a buggy guest make | |
257 | * slow progress even if it does not correctly handle a | |
258 | * level-triggered interrupt. Emulate this behavior if we | |
259 | * detect an interrupt storm. | |
260 | */ | |
03f990a5 | 261 | s->irq_eoi[n] = 0; |
958a01da VK |
262 | timer_mod_anticipate(s->delayed_ioapic_service_timer, |
263 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
264 | NANOSECONDS_PER_SECOND / 100); | |
03f990a5 | 265 | trace_ioapic_eoi_delayed_reassert(n); |
958a01da | 266 | } else { |
0280b571 JK |
267 | ioapic_service(s); |
268 | } | |
958a01da | 269 | } else { |
03f990a5 | 270 | s->irq_eoi[n] = 0; |
0280b571 JK |
271 | } |
272 | } | |
273 | } | |
274 | } | |
275 | ||
4d5bf5f6 | 276 | static uint64_t |
a8170e5e | 277 | ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size) |
610626af | 278 | { |
244ac3af | 279 | IOAPICCommonState *s = opaque; |
610626af AL |
280 | int index; |
281 | uint32_t val = 0; | |
282 | ||
e5074b38 PX |
283 | addr &= 0xff; |
284 | ||
285 | switch (addr) { | |
1f5e71a8 | 286 | case IOAPIC_IOREGSEL: |
610626af | 287 | val = s->ioregsel; |
1f5e71a8 JK |
288 | break; |
289 | case IOAPIC_IOWIN: | |
1a440963 JK |
290 | if (size != 4) { |
291 | break; | |
292 | } | |
610626af | 293 | switch (s->ioregsel) { |
1f5e71a8 | 294 | case IOAPIC_REG_ID: |
2f5a3b12 | 295 | case IOAPIC_REG_ARB: |
1f5e71a8 JK |
296 | val = s->id << IOAPIC_ID_SHIFT; |
297 | break; | |
298 | case IOAPIC_REG_VER: | |
20fd4b7b | 299 | val = s->version | |
1f5e71a8 JK |
300 | ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT); |
301 | break; | |
1f5e71a8 JK |
302 | default: |
303 | index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; | |
304 | if (index >= 0 && index < IOAPIC_NUM_PINS) { | |
305 | if (s->ioregsel & 1) { | |
306 | val = s->ioredtbl[index] >> 32; | |
307 | } else { | |
308 | val = s->ioredtbl[index] & 0xffffffff; | |
610626af | 309 | } |
1f5e71a8 | 310 | } |
610626af | 311 | } |
1f5e71a8 | 312 | break; |
610626af | 313 | } |
e5074b38 | 314 | |
a2e6ffab | 315 | trace_ioapic_mem_read(addr, s->ioregsel, size, val); |
e5074b38 | 316 | |
610626af AL |
317 | return val; |
318 | } | |
319 | ||
ed1263c3 PX |
320 | /* |
321 | * This is to satisfy the hack in Linux kernel. One hack of it is to | |
322 | * simulate clearing the Remote IRR bit of IOAPIC entry using the | |
323 | * following: | |
324 | * | |
325 | * "For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
326 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
327 | * mode to edge and then back to level, with RTE being masked during | |
328 | * this." | |
329 | * | |
330 | * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701) | |
331 | * | |
332 | * This is based on the assumption that, Remote IRR bit will be | |
333 | * cleared by IOAPIC hardware when configured as edge-triggered | |
334 | * interrupts. | |
335 | * | |
336 | * Without this, level-triggered interrupts in IR mode might fail to | |
337 | * work correctly. | |
338 | */ | |
339 | static inline void | |
340 | ioapic_fix_edge_remote_irr(uint64_t *entry) | |
341 | { | |
342 | if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) { | |
343 | /* Edge-triggered interrupts, make sure remote IRR is zero */ | |
344 | *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR); | |
345 | } | |
346 | } | |
347 | ||
1f5e71a8 | 348 | static void |
a8170e5e | 349 | ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, |
4d5bf5f6 | 350 | unsigned int size) |
610626af | 351 | { |
244ac3af | 352 | IOAPICCommonState *s = opaque; |
610626af AL |
353 | int index; |
354 | ||
e5074b38 | 355 | addr &= 0xff; |
a2e6ffab | 356 | trace_ioapic_mem_write(addr, s->ioregsel, size, val); |
e5074b38 PX |
357 | |
358 | switch (addr) { | |
1f5e71a8 | 359 | case IOAPIC_IOREGSEL: |
610626af | 360 | s->ioregsel = val; |
1f5e71a8 JK |
361 | break; |
362 | case IOAPIC_IOWIN: | |
1a440963 JK |
363 | if (size != 4) { |
364 | break; | |
365 | } | |
610626af | 366 | switch (s->ioregsel) { |
1f5e71a8 JK |
367 | case IOAPIC_REG_ID: |
368 | s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK; | |
369 | break; | |
370 | case IOAPIC_REG_VER: | |
371 | case IOAPIC_REG_ARB: | |
372 | break; | |
373 | default: | |
374 | index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; | |
375 | if (index >= 0 && index < IOAPIC_NUM_PINS) { | |
479c2a1c | 376 | uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS; |
1f5e71a8 JK |
377 | if (s->ioregsel & 1) { |
378 | s->ioredtbl[index] &= 0xffffffff; | |
379 | s->ioredtbl[index] |= (uint64_t)val << 32; | |
380 | } else { | |
381 | s->ioredtbl[index] &= ~0xffffffffULL; | |
382 | s->ioredtbl[index] |= val; | |
610626af | 383 | } |
479c2a1c PX |
384 | /* restore RO bits */ |
385 | s->ioredtbl[index] &= IOAPIC_RW_BITS; | |
386 | s->ioredtbl[index] |= ro_bits; | |
d15d3d57 | 387 | s->irq_eoi[index] = 0; |
ed1263c3 | 388 | ioapic_fix_edge_remote_irr(&s->ioredtbl[index]); |
1f5e71a8 JK |
389 | ioapic_service(s); |
390 | } | |
610626af | 391 | } |
1f5e71a8 | 392 | break; |
20fd4b7b PX |
393 | case IOAPIC_EOI: |
394 | /* Explicit EOI is only supported for IOAPIC version 0x20 */ | |
395 | if (size != 4 || s->version != 0x20) { | |
396 | break; | |
397 | } | |
398 | ioapic_eoi_broadcast(val); | |
399 | break; | |
610626af | 400 | } |
15eafc2e PB |
401 | |
402 | ioapic_update_kvm_routes(s); | |
610626af AL |
403 | } |
404 | ||
4d5bf5f6 JK |
405 | static const MemoryRegionOps ioapic_io_ops = { |
406 | .read = ioapic_mem_read, | |
407 | .write = ioapic_mem_write, | |
408 | .endianness = DEVICE_NATIVE_ENDIAN, | |
610626af AL |
409 | }; |
410 | ||
e3d9c925 PX |
411 | static void ioapic_machine_done_notify(Notifier *notifier, void *data) |
412 | { | |
413 | #ifdef CONFIG_KVM | |
414 | IOAPICCommonState *s = container_of(notifier, IOAPICCommonState, | |
415 | machine_done); | |
416 | ||
417 | if (kvm_irqchip_is_split()) { | |
418 | X86IOMMUState *iommu = x86_iommu_get_default(); | |
419 | if (iommu) { | |
420 | /* Register this IOAPIC with IOMMU IEC notifier, so that | |
421 | * when there are IR invalidates, we can be notified to | |
422 | * update kernel IR cache. */ | |
423 | x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s); | |
424 | } | |
425 | } | |
426 | #endif | |
427 | } | |
428 | ||
8d5516be PX |
429 | #define IOAPIC_VER_DEF 0x20 |
430 | ||
db0f8888 | 431 | static void ioapic_realize(DeviceState *dev, Error **errp) |
610626af | 432 | { |
db0f8888 | 433 | IOAPICCommonState *s = IOAPIC_COMMON(dev); |
f9771858 | 434 | |
20fd4b7b | 435 | if (s->version != 0x11 && s->version != 0x20) { |
11ab69d6 MA |
436 | error_setg(errp, "IOAPIC only supports version 0x11 or 0x20 " |
437 | "(default: 0x%x).", IOAPIC_VER_DEF); | |
438 | return; | |
20fd4b7b PX |
439 | } |
440 | ||
1437c94b PB |
441 | memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s, |
442 | "ioapic", 0x1000); | |
610626af | 443 | |
958a01da VK |
444 | s->delayed_ioapic_service_timer = |
445 | timer_new_ns(QEMU_CLOCK_VIRTUAL, delayed_ioapic_service_cb, s); | |
446 | ||
f9771858 | 447 | qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS); |
0280b571 | 448 | |
db0f8888 | 449 | ioapics[ioapic_no] = s; |
e3d9c925 PX |
450 | s->machine_done.notify = ioapic_machine_done_notify; |
451 | qemu_add_machine_init_done_notifier(&s->machine_done); | |
610626af | 452 | } |
96051119 | 453 | |
958a01da VK |
454 | static void ioapic_unrealize(DeviceState *dev, Error **errp) |
455 | { | |
456 | IOAPICCommonState *s = IOAPIC_COMMON(dev); | |
457 | ||
458 | timer_del(s->delayed_ioapic_service_timer); | |
459 | timer_free(s->delayed_ioapic_service_timer); | |
460 | } | |
461 | ||
20fd4b7b | 462 | static Property ioapic_properties[] = { |
8d5516be | 463 | DEFINE_PROP_UINT8("version", IOAPICCommonState, version, IOAPIC_VER_DEF), |
20fd4b7b PX |
464 | DEFINE_PROP_END_OF_LIST(), |
465 | }; | |
466 | ||
999e12bb AL |
467 | static void ioapic_class_init(ObjectClass *klass, void *data) |
468 | { | |
469 | IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass); | |
39bffca2 | 470 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 471 | |
db0f8888 | 472 | k->realize = ioapic_realize; |
958a01da | 473 | k->unrealize = ioapic_unrealize; |
0f254b1a PX |
474 | /* |
475 | * If APIC is in kernel, we need to update the kernel cache after | |
476 | * migration, otherwise first 24 gsi routes will be invalid. | |
477 | */ | |
478 | k->post_load = ioapic_update_kvm_routes; | |
39bffca2 | 479 | dc->reset = ioapic_reset_common; |
20fd4b7b | 480 | dc->props = ioapic_properties; |
999e12bb AL |
481 | } |
482 | ||
8c43a6f0 | 483 | static const TypeInfo ioapic_info = { |
34bec7a8 | 484 | .name = TYPE_IOAPIC, |
39bffca2 AL |
485 | .parent = TYPE_IOAPIC_COMMON, |
486 | .instance_size = sizeof(IOAPICCommonState), | |
487 | .class_init = ioapic_class_init, | |
96051119 BS |
488 | }; |
489 | ||
83f7d43a | 490 | static void ioapic_register_types(void) |
96051119 | 491 | { |
39bffca2 | 492 | type_register_static(&ioapic_info); |
96051119 BS |
493 | } |
494 | ||
83f7d43a | 495 | type_init(ioapic_register_types) |