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3aa597f6 CLG |
1 | /* |
2 | * QEMU PowerPC sPAPR XIVE interrupt controller model | |
3 | * | |
4 | * Copyright (c) 2017-2018, IBM Corporation. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See the | |
7 | * COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
11 | #include "qemu/log.h" | |
0b8fa32f | 12 | #include "qemu/module.h" |
3aa597f6 CLG |
13 | #include "qapi/error.h" |
14 | #include "qemu/error-report.h" | |
15 | #include "target/ppc/cpu.h" | |
16 | #include "sysemu/cpus.h" | |
17 | #include "monitor/monitor.h" | |
6e21de4a | 18 | #include "hw/ppc/fdt.h" |
3aa597f6 | 19 | #include "hw/ppc/spapr.h" |
a28b9a5a | 20 | #include "hw/ppc/spapr_cpu_core.h" |
3aa597f6 CLG |
21 | #include "hw/ppc/spapr_xive.h" |
22 | #include "hw/ppc/xive.h" | |
23 | #include "hw/ppc/xive_regs.h" | |
24 | ||
25 | /* | |
26 | * XIVE Virtualization Controller BAR and Thread Managment BAR that we | |
27 | * use for the ESB pages and the TIMA pages | |
28 | */ | |
29 | #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull | |
30 | #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull | |
31 | ||
0cddee8d CLG |
32 | /* |
33 | * The allocation of VP blocks is a complex operation in OPAL and the | |
34 | * VP identifiers have a relation with the number of HW chips, the | |
35 | * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE | |
36 | * controller model does not have the same constraints and can use a | |
37 | * simple mapping scheme of the CPU vcpu_id | |
38 | * | |
39 | * These identifiers are never returned to the OS. | |
40 | */ | |
41 | ||
42 | #define SPAPR_XIVE_NVT_BASE 0x400 | |
43 | ||
44 | /* | |
45 | * sPAPR NVT and END indexing helpers | |
46 | */ | |
47 | static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) | |
48 | { | |
49 | return nvt_idx - SPAPR_XIVE_NVT_BASE; | |
50 | } | |
51 | ||
23bcd5eb CLG |
52 | static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, |
53 | uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) | |
54 | { | |
55 | assert(cpu); | |
56 | ||
57 | if (out_nvt_blk) { | |
58 | *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; | |
59 | } | |
60 | ||
61 | if (out_nvt_blk) { | |
62 | *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; | |
63 | } | |
64 | } | |
65 | ||
66 | static int spapr_xive_target_to_nvt(uint32_t target, | |
67 | uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) | |
68 | { | |
69 | PowerPCCPU *cpu = spapr_find_cpu(target); | |
70 | ||
71 | if (!cpu) { | |
72 | return -1; | |
73 | } | |
74 | ||
75 | spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); | |
76 | return 0; | |
77 | } | |
78 | ||
79 | /* | |
80 | * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 | |
81 | * priorities per CPU | |
82 | */ | |
0c575703 CLG |
83 | int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, |
84 | uint32_t *out_server, uint8_t *out_prio) | |
85 | { | |
86 | ||
87 | assert(end_blk == SPAPR_XIVE_BLOCK_ID); | |
88 | ||
89 | if (out_server) { | |
90 | *out_server = end_idx >> 3; | |
91 | } | |
92 | ||
93 | if (out_prio) { | |
94 | *out_prio = end_idx & 0x7; | |
95 | } | |
96 | return 0; | |
97 | } | |
98 | ||
23bcd5eb CLG |
99 | static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, |
100 | uint8_t *out_end_blk, uint32_t *out_end_idx) | |
101 | { | |
102 | assert(cpu); | |
103 | ||
104 | if (out_end_blk) { | |
105 | *out_end_blk = SPAPR_XIVE_BLOCK_ID; | |
106 | } | |
107 | ||
108 | if (out_end_idx) { | |
109 | *out_end_idx = (cpu->vcpu_id << 3) + prio; | |
110 | } | |
111 | } | |
112 | ||
113 | static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, | |
114 | uint8_t *out_end_blk, uint32_t *out_end_idx) | |
115 | { | |
116 | PowerPCCPU *cpu = spapr_find_cpu(target); | |
117 | ||
118 | if (!cpu) { | |
119 | return -1; | |
120 | } | |
121 | ||
122 | spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); | |
123 | return 0; | |
124 | } | |
125 | ||
3aa597f6 CLG |
126 | /* |
127 | * On sPAPR machines, use a simplified output for the XIVE END | |
128 | * structure dumping only the information related to the OS EQ. | |
129 | */ | |
ce2918cb | 130 | static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, |
3aa597f6 CLG |
131 | Monitor *mon) |
132 | { | |
fb2e8b51 | 133 | uint64_t qaddr_base = xive_end_qaddr(end); |
3aa597f6 CLG |
134 | uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); |
135 | uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); | |
136 | uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); | |
137 | uint32_t qentries = 1 << (qsize + 10); | |
138 | uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); | |
139 | uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); | |
140 | ||
fb2e8b51 | 141 | monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", |
0cddee8d | 142 | spapr_xive_nvt_to_target(0, nvt), |
fb2e8b51 | 143 | priority, qindex, qentries, qaddr_base, qgen); |
3aa597f6 CLG |
144 | |
145 | xive_end_queue_pic_print_info(end, 6, mon); | |
146 | monitor_printf(mon, "]"); | |
147 | } | |
148 | ||
ce2918cb | 149 | void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) |
3aa597f6 CLG |
150 | { |
151 | XiveSource *xsrc = &xive->source; | |
152 | int i; | |
153 | ||
7bfc759c CLG |
154 | if (kvm_irqchip_in_kernel()) { |
155 | Error *local_err = NULL; | |
156 | ||
157 | kvmppc_xive_synchronize_state(xive, &local_err); | |
158 | if (local_err) { | |
159 | error_report_err(local_err); | |
160 | return; | |
161 | } | |
162 | } | |
163 | ||
f81d69fc | 164 | monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); |
3aa597f6 CLG |
165 | |
166 | for (i = 0; i < xive->nr_irqs; i++) { | |
167 | uint8_t pq = xive_source_esb_get(xsrc, i); | |
168 | XiveEAS *eas = &xive->eat[i]; | |
169 | ||
170 | if (!xive_eas_is_valid(eas)) { | |
171 | continue; | |
172 | } | |
173 | ||
174 | monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, | |
175 | xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", | |
176 | pq & XIVE_ESB_VAL_P ? 'P' : '-', | |
177 | pq & XIVE_ESB_VAL_Q ? 'Q' : '-', | |
178 | xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', | |
179 | xive_eas_is_masked(eas) ? "M" : " ", | |
180 | (int) xive_get_field64(EAS_END_DATA, eas->w)); | |
181 | ||
182 | if (!xive_eas_is_masked(eas)) { | |
183 | uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); | |
184 | XiveEND *end; | |
185 | ||
186 | assert(end_idx < xive->nr_ends); | |
187 | end = &xive->endt[end_idx]; | |
188 | ||
189 | if (xive_end_is_valid(end)) { | |
190 | spapr_xive_end_pic_print_info(xive, end, mon); | |
191 | } | |
192 | } | |
193 | monitor_printf(mon, "\n"); | |
194 | } | |
195 | } | |
196 | ||
ce2918cb | 197 | void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) |
3a8eb78e CLG |
198 | { |
199 | memory_region_set_enabled(&xive->source.esb_mmio, enable); | |
200 | memory_region_set_enabled(&xive->tm_mmio, enable); | |
201 | ||
202 | /* Disable the END ESBs until a guest OS makes use of them */ | |
203 | memory_region_set_enabled(&xive->end_source.esb_mmio, false); | |
204 | } | |
205 | ||
b2e22477 CLG |
206 | /* |
207 | * When a Virtual Processor is scheduled to run on a HW thread, the | |
208 | * hypervisor pushes its identifier in the OS CAM line. Emulate the | |
209 | * same behavior under QEMU. | |
210 | */ | |
211 | void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) | |
212 | { | |
213 | uint8_t nvt_blk; | |
214 | uint32_t nvt_idx; | |
215 | uint32_t nvt_cam; | |
216 | ||
217 | spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); | |
218 | ||
219 | nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); | |
220 | memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); | |
221 | } | |
222 | ||
3aa597f6 CLG |
223 | static void spapr_xive_end_reset(XiveEND *end) |
224 | { | |
225 | memset(end, 0, sizeof(*end)); | |
226 | ||
227 | /* switch off the escalation and notification ESBs */ | |
228 | end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); | |
229 | } | |
230 | ||
231 | static void spapr_xive_reset(void *dev) | |
232 | { | |
ce2918cb | 233 | SpaprXive *xive = SPAPR_XIVE(dev); |
3aa597f6 CLG |
234 | int i; |
235 | ||
236 | /* | |
237 | * The XiveSource has its own reset handler, which mask off all | |
238 | * IRQs (!P|Q) | |
239 | */ | |
240 | ||
241 | /* Mask all valid EASs in the IRQ number space. */ | |
242 | for (i = 0; i < xive->nr_irqs; i++) { | |
243 | XiveEAS *eas = &xive->eat[i]; | |
244 | if (xive_eas_is_valid(eas)) { | |
245 | eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); | |
246 | } else { | |
247 | eas->w = 0; | |
248 | } | |
249 | } | |
250 | ||
251 | /* Clear all ENDs */ | |
252 | for (i = 0; i < xive->nr_ends; i++) { | |
253 | spapr_xive_end_reset(&xive->endt[i]); | |
254 | } | |
255 | } | |
256 | ||
257 | static void spapr_xive_instance_init(Object *obj) | |
258 | { | |
ce2918cb | 259 | SpaprXive *xive = SPAPR_XIVE(obj); |
3aa597f6 | 260 | |
f6d4dca8 TH |
261 | object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), |
262 | TYPE_XIVE_SOURCE, &error_abort, NULL); | |
3aa597f6 | 263 | |
f6d4dca8 TH |
264 | object_initialize_child(obj, "end_source", &xive->end_source, |
265 | sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, | |
266 | &error_abort, NULL); | |
38afd772 CLG |
267 | |
268 | /* Not connected to the KVM XIVE device */ | |
269 | xive->fd = -1; | |
3aa597f6 CLG |
270 | } |
271 | ||
272 | static void spapr_xive_realize(DeviceState *dev, Error **errp) | |
273 | { | |
ce2918cb | 274 | SpaprXive *xive = SPAPR_XIVE(dev); |
3aa597f6 CLG |
275 | XiveSource *xsrc = &xive->source; |
276 | XiveENDSource *end_xsrc = &xive->end_source; | |
277 | Error *local_err = NULL; | |
278 | ||
279 | if (!xive->nr_irqs) { | |
280 | error_setg(errp, "Number of interrupt needs to be greater 0"); | |
281 | return; | |
282 | } | |
283 | ||
284 | if (!xive->nr_ends) { | |
285 | error_setg(errp, "Number of interrupt needs to be greater 0"); | |
286 | return; | |
287 | } | |
288 | ||
289 | /* | |
290 | * Initialize the internal sources, for IPIs and virtual devices. | |
291 | */ | |
292 | object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", | |
293 | &error_fatal); | |
294 | object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), | |
295 | &error_fatal); | |
296 | object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); | |
297 | if (local_err) { | |
298 | error_propagate(errp, local_err); | |
299 | return; | |
300 | } | |
981b1c62 | 301 | sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); |
3aa597f6 CLG |
302 | |
303 | /* | |
304 | * Initialize the END ESB source | |
305 | */ | |
306 | object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", | |
307 | &error_fatal); | |
308 | object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), | |
309 | &error_fatal); | |
310 | object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); | |
311 | if (local_err) { | |
312 | error_propagate(errp, local_err); | |
313 | return; | |
314 | } | |
981b1c62 | 315 | sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); |
3aa597f6 CLG |
316 | |
317 | /* Set the mapping address of the END ESB pages after the source ESBs */ | |
318 | xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; | |
319 | ||
320 | /* | |
321 | * Allocate the routing tables | |
322 | */ | |
323 | xive->eat = g_new0(XiveEAS, xive->nr_irqs); | |
324 | xive->endt = g_new0(XiveEND, xive->nr_ends); | |
325 | ||
38afd772 CLG |
326 | xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, |
327 | xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); | |
328 | ||
329 | qemu_register_reset(spapr_xive_reset, dev); | |
cdd71c8e | 330 | |
3aa597f6 CLG |
331 | /* TIMA initialization */ |
332 | memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, | |
333 | "xive.tima", 4ull << TM_SHIFT); | |
981b1c62 | 334 | sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); |
3aa597f6 | 335 | |
981b1c62 CLG |
336 | /* |
337 | * Map all regions. These will be enabled or disabled at reset and | |
338 | * can also be overridden by KVM memory regions if active | |
339 | */ | |
340 | sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); | |
341 | sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); | |
342 | sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); | |
3aa597f6 CLG |
343 | } |
344 | ||
345 | static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, | |
346 | uint32_t eas_idx, XiveEAS *eas) | |
347 | { | |
ce2918cb | 348 | SpaprXive *xive = SPAPR_XIVE(xrtr); |
3aa597f6 CLG |
349 | |
350 | if (eas_idx >= xive->nr_irqs) { | |
351 | return -1; | |
352 | } | |
353 | ||
354 | *eas = xive->eat[eas_idx]; | |
355 | return 0; | |
356 | } | |
357 | ||
358 | static int spapr_xive_get_end(XiveRouter *xrtr, | |
359 | uint8_t end_blk, uint32_t end_idx, XiveEND *end) | |
360 | { | |
ce2918cb | 361 | SpaprXive *xive = SPAPR_XIVE(xrtr); |
3aa597f6 CLG |
362 | |
363 | if (end_idx >= xive->nr_ends) { | |
364 | return -1; | |
365 | } | |
366 | ||
367 | memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); | |
368 | return 0; | |
369 | } | |
370 | ||
371 | static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, | |
372 | uint32_t end_idx, XiveEND *end, | |
373 | uint8_t word_number) | |
374 | { | |
ce2918cb | 375 | SpaprXive *xive = SPAPR_XIVE(xrtr); |
3aa597f6 CLG |
376 | |
377 | if (end_idx >= xive->nr_ends) { | |
378 | return -1; | |
379 | } | |
380 | ||
381 | memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); | |
382 | return 0; | |
383 | } | |
384 | ||
0cddee8d CLG |
385 | static int spapr_xive_get_nvt(XiveRouter *xrtr, |
386 | uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) | |
387 | { | |
388 | uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); | |
389 | PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); | |
390 | ||
391 | if (!cpu) { | |
392 | /* TODO: should we assert() if we can find a NVT ? */ | |
393 | return -1; | |
394 | } | |
395 | ||
396 | /* | |
397 | * sPAPR does not maintain a NVT table. Return that the NVT is | |
398 | * valid if we have found a matching CPU | |
399 | */ | |
400 | nvt->w0 = cpu_to_be32(NVT_W0_VALID); | |
401 | return 0; | |
402 | } | |
403 | ||
404 | static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, | |
405 | uint32_t nvt_idx, XiveNVT *nvt, | |
406 | uint8_t word_number) | |
407 | { | |
408 | /* | |
409 | * We don't need to write back to the NVTs because the sPAPR | |
410 | * machine should never hit a non-scheduled NVT. It should never | |
411 | * get called. | |
412 | */ | |
413 | g_assert_not_reached(); | |
414 | } | |
415 | ||
40a5056c CLG |
416 | static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) |
417 | { | |
418 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
419 | ||
a28b9a5a | 420 | return spapr_cpu_state(cpu)->tctx; |
40a5056c CLG |
421 | } |
422 | ||
3aa597f6 CLG |
423 | static const VMStateDescription vmstate_spapr_xive_end = { |
424 | .name = TYPE_SPAPR_XIVE "/end", | |
425 | .version_id = 1, | |
426 | .minimum_version_id = 1, | |
427 | .fields = (VMStateField []) { | |
428 | VMSTATE_UINT32(w0, XiveEND), | |
429 | VMSTATE_UINT32(w1, XiveEND), | |
430 | VMSTATE_UINT32(w2, XiveEND), | |
431 | VMSTATE_UINT32(w3, XiveEND), | |
432 | VMSTATE_UINT32(w4, XiveEND), | |
433 | VMSTATE_UINT32(w5, XiveEND), | |
434 | VMSTATE_UINT32(w6, XiveEND), | |
435 | VMSTATE_UINT32(w7, XiveEND), | |
436 | VMSTATE_END_OF_LIST() | |
437 | }, | |
438 | }; | |
439 | ||
440 | static const VMStateDescription vmstate_spapr_xive_eas = { | |
441 | .name = TYPE_SPAPR_XIVE "/eas", | |
442 | .version_id = 1, | |
443 | .minimum_version_id = 1, | |
444 | .fields = (VMStateField []) { | |
445 | VMSTATE_UINT64(w, XiveEAS), | |
446 | VMSTATE_END_OF_LIST() | |
447 | }, | |
448 | }; | |
449 | ||
277dd3d7 CLG |
450 | static int vmstate_spapr_xive_pre_save(void *opaque) |
451 | { | |
452 | if (kvm_irqchip_in_kernel()) { | |
453 | return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); | |
454 | } | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
459 | /* | |
460 | * Called by the sPAPR IRQ backend 'post_load' method at the machine | |
461 | * level. | |
462 | */ | |
463 | int spapr_xive_post_load(SpaprXive *xive, int version_id) | |
464 | { | |
465 | if (kvm_irqchip_in_kernel()) { | |
466 | return kvmppc_xive_post_load(xive, version_id); | |
467 | } | |
468 | ||
469 | return 0; | |
470 | } | |
471 | ||
3aa597f6 CLG |
472 | static const VMStateDescription vmstate_spapr_xive = { |
473 | .name = TYPE_SPAPR_XIVE, | |
474 | .version_id = 1, | |
475 | .minimum_version_id = 1, | |
277dd3d7 CLG |
476 | .pre_save = vmstate_spapr_xive_pre_save, |
477 | .post_load = NULL, /* handled at the machine level */ | |
3aa597f6 | 478 | .fields = (VMStateField[]) { |
ce2918cb DG |
479 | VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), |
480 | VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, | |
3aa597f6 | 481 | vmstate_spapr_xive_eas, XiveEAS), |
ce2918cb | 482 | VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, |
3aa597f6 CLG |
483 | vmstate_spapr_xive_end, XiveEND), |
484 | VMSTATE_END_OF_LIST() | |
485 | }, | |
486 | }; | |
487 | ||
488 | static Property spapr_xive_properties[] = { | |
ce2918cb DG |
489 | DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), |
490 | DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), | |
491 | DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), | |
492 | DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), | |
3aa597f6 CLG |
493 | DEFINE_PROP_END_OF_LIST(), |
494 | }; | |
495 | ||
496 | static void spapr_xive_class_init(ObjectClass *klass, void *data) | |
497 | { | |
498 | DeviceClass *dc = DEVICE_CLASS(klass); | |
499 | XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); | |
500 | ||
501 | dc->desc = "sPAPR XIVE Interrupt Controller"; | |
502 | dc->props = spapr_xive_properties; | |
503 | dc->realize = spapr_xive_realize; | |
504 | dc->vmsd = &vmstate_spapr_xive; | |
505 | ||
506 | xrc->get_eas = spapr_xive_get_eas; | |
507 | xrc->get_end = spapr_xive_get_end; | |
508 | xrc->write_end = spapr_xive_write_end; | |
0cddee8d CLG |
509 | xrc->get_nvt = spapr_xive_get_nvt; |
510 | xrc->write_nvt = spapr_xive_write_nvt; | |
40a5056c | 511 | xrc->get_tctx = spapr_xive_get_tctx; |
3aa597f6 CLG |
512 | } |
513 | ||
514 | static const TypeInfo spapr_xive_info = { | |
515 | .name = TYPE_SPAPR_XIVE, | |
516 | .parent = TYPE_XIVE_ROUTER, | |
517 | .instance_init = spapr_xive_instance_init, | |
ce2918cb | 518 | .instance_size = sizeof(SpaprXive), |
3aa597f6 CLG |
519 | .class_init = spapr_xive_class_init, |
520 | }; | |
521 | ||
522 | static void spapr_xive_register_types(void) | |
523 | { | |
524 | type_register_static(&spapr_xive_info); | |
525 | } | |
526 | ||
527 | type_init(spapr_xive_register_types) | |
528 | ||
ce2918cb | 529 | bool spapr_xive_irq_claim(SpaprXive *xive, uint32_t lisn, bool lsi) |
3aa597f6 CLG |
530 | { |
531 | XiveSource *xsrc = &xive->source; | |
532 | ||
533 | if (lisn >= xive->nr_irqs) { | |
534 | return false; | |
535 | } | |
536 | ||
537 | xive->eat[lisn].w |= cpu_to_be64(EAS_VALID); | |
0afed8c8 GK |
538 | if (lsi) { |
539 | xive_source_irq_set_lsi(xsrc, lisn); | |
540 | } | |
38afd772 CLG |
541 | |
542 | if (kvm_irqchip_in_kernel()) { | |
543 | Error *local_err = NULL; | |
544 | ||
545 | kvmppc_xive_source_reset_one(xsrc, lisn, &local_err); | |
546 | if (local_err) { | |
547 | error_report_err(local_err); | |
548 | return false; | |
549 | } | |
550 | } | |
551 | ||
3aa597f6 CLG |
552 | return true; |
553 | } | |
554 | ||
ce2918cb | 555 | bool spapr_xive_irq_free(SpaprXive *xive, uint32_t lisn) |
3aa597f6 | 556 | { |
3aa597f6 CLG |
557 | if (lisn >= xive->nr_irqs) { |
558 | return false; | |
559 | } | |
560 | ||
561 | xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); | |
3aa597f6 CLG |
562 | return true; |
563 | } | |
564 | ||
23bcd5eb CLG |
565 | /* |
566 | * XIVE hcalls | |
567 | * | |
568 | * The terminology used by the XIVE hcalls is the following : | |
569 | * | |
570 | * TARGET vCPU number | |
571 | * EQ Event Queue assigned by OS to receive event data | |
572 | * ESB page for source interrupt management | |
573 | * LISN Logical Interrupt Source Number identifying a source in the | |
574 | * machine | |
575 | * EISN Effective Interrupt Source Number used by guest OS to | |
576 | * identify source in the guest | |
577 | * | |
578 | * The EAS, END, NVT structures are not exposed. | |
579 | */ | |
580 | ||
581 | /* | |
582 | * Linux hosts under OPAL reserve priority 7 for their own escalation | |
583 | * interrupts (DD2.X POWER9). So we only allow the guest to use | |
584 | * priorities [0..6]. | |
585 | */ | |
586 | static bool spapr_xive_priority_is_reserved(uint8_t priority) | |
587 | { | |
588 | switch (priority) { | |
589 | case 0 ... 6: | |
590 | return false; | |
591 | case 7: /* OPAL escalation queue */ | |
592 | default: | |
593 | return true; | |
594 | } | |
595 | } | |
596 | ||
597 | /* | |
598 | * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical | |
599 | * real address of the MMIO page through which the Event State Buffer | |
600 | * entry associated with the value of the "lisn" parameter is managed. | |
601 | * | |
602 | * Parameters: | |
603 | * Input | |
604 | * - R4: "flags" | |
605 | * Bits 0-63 reserved | |
606 | * - R5: "lisn" is per "interrupts", "interrupt-map", or | |
607 | * "ibm,xive-lisn-ranges" properties, or as returned by the | |
608 | * ibm,query-interrupt-source-number RTAS call, or as returned | |
609 | * by the H_ALLOCATE_VAS_WINDOW hcall | |
610 | * | |
611 | * Output | |
612 | * - R4: "flags" | |
613 | * Bits 0-59: Reserved | |
614 | * Bit 60: H_INT_ESB must be used for Event State Buffer | |
615 | * management | |
616 | * Bit 61: 1 == LSI 0 == MSI | |
617 | * Bit 62: the full function page supports trigger | |
618 | * Bit 63: Store EOI Supported | |
619 | * - R5: Logical Real address of full function Event State Buffer | |
620 | * management page, -1 if H_INT_ESB hcall flag is set to 1. | |
621 | * - R6: Logical Real Address of trigger only Event State Buffer | |
622 | * management page or -1. | |
623 | * - R7: Power of 2 page size for the ESB management pages returned in | |
624 | * R5 and R6. | |
625 | */ | |
626 | ||
627 | #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ | |
628 | #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ | |
629 | #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management | |
630 | on same page */ | |
631 | #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ | |
632 | ||
633 | static target_ulong h_int_get_source_info(PowerPCCPU *cpu, | |
ce2918cb | 634 | SpaprMachineState *spapr, |
23bcd5eb CLG |
635 | target_ulong opcode, |
636 | target_ulong *args) | |
637 | { | |
ce2918cb | 638 | SpaprXive *xive = spapr->xive; |
23bcd5eb CLG |
639 | XiveSource *xsrc = &xive->source; |
640 | target_ulong flags = args[0]; | |
641 | target_ulong lisn = args[1]; | |
642 | ||
643 | if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { | |
644 | return H_FUNCTION; | |
645 | } | |
646 | ||
647 | if (flags) { | |
648 | return H_PARAMETER; | |
649 | } | |
650 | ||
651 | if (lisn >= xive->nr_irqs) { | |
652 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", | |
653 | lisn); | |
654 | return H_P2; | |
655 | } | |
656 | ||
657 | if (!xive_eas_is_valid(&xive->eat[lisn])) { | |
658 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", | |
659 | lisn); | |
660 | return H_P2; | |
661 | } | |
662 | ||
663 | /* | |
664 | * All sources are emulated under the main XIVE object and share | |
665 | * the same characteristics. | |
666 | */ | |
667 | args[0] = 0; | |
668 | if (!xive_source_esb_has_2page(xsrc)) { | |
669 | args[0] |= SPAPR_XIVE_SRC_TRIGGER; | |
670 | } | |
671 | if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { | |
672 | args[0] |= SPAPR_XIVE_SRC_STORE_EOI; | |
673 | } | |
674 | ||
675 | /* | |
676 | * Force the use of the H_INT_ESB hcall in case of an LSI | |
677 | * interrupt. This is necessary under KVM to re-trigger the | |
678 | * interrupt if the level is still asserted | |
679 | */ | |
680 | if (xive_source_irq_is_lsi(xsrc, lisn)) { | |
681 | args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; | |
682 | } | |
683 | ||
684 | if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { | |
685 | args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); | |
686 | } else { | |
687 | args[1] = -1; | |
688 | } | |
689 | ||
690 | if (xive_source_esb_has_2page(xsrc) && | |
691 | !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { | |
692 | args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); | |
693 | } else { | |
694 | args[2] = -1; | |
695 | } | |
696 | ||
697 | if (xive_source_esb_has_2page(xsrc)) { | |
698 | args[3] = xsrc->esb_shift - 1; | |
699 | } else { | |
700 | args[3] = xsrc->esb_shift; | |
701 | } | |
702 | ||
703 | return H_SUCCESS; | |
704 | } | |
705 | ||
706 | /* | |
707 | * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical | |
708 | * Interrupt Source to a target. The Logical Interrupt Source is | |
709 | * designated with the "lisn" parameter and the target is designated | |
710 | * with the "target" and "priority" parameters. Upon return from the | |
711 | * hcall(), no additional interrupts will be directed to the old EQ. | |
712 | * | |
713 | * Parameters: | |
714 | * Input: | |
715 | * - R4: "flags" | |
716 | * Bits 0-61: Reserved | |
717 | * Bit 62: set the "eisn" in the EAS | |
718 | * Bit 63: masks the interrupt source in the hardware interrupt | |
719 | * control structure. An interrupt masked by this mechanism will | |
720 | * be dropped, but it's source state bits will still be | |
721 | * set. There is no race-free way of unmasking and restoring the | |
722 | * source. Thus this should only be used in interrupts that are | |
723 | * also masked at the source, and only in cases where the | |
724 | * interrupt is not meant to be used for a large amount of time | |
725 | * because no valid target exists for it for example | |
726 | * - R5: "lisn" is per "interrupts", "interrupt-map", or | |
727 | * "ibm,xive-lisn-ranges" properties, or as returned by the | |
728 | * ibm,query-interrupt-source-number RTAS call, or as returned by | |
729 | * the H_ALLOCATE_VAS_WINDOW hcall | |
730 | * - R6: "target" is per "ibm,ppc-interrupt-server#s" or | |
731 | * "ibm,ppc-interrupt-gserver#s" | |
732 | * - R7: "priority" is a valid priority not in | |
733 | * "ibm,plat-res-int-priorities" | |
734 | * - R8: "eisn" is the guest EISN associated with the "lisn" | |
735 | * | |
736 | * Output: | |
737 | * - None | |
738 | */ | |
739 | ||
740 | #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) | |
741 | #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) | |
742 | ||
743 | static target_ulong h_int_set_source_config(PowerPCCPU *cpu, | |
ce2918cb | 744 | SpaprMachineState *spapr, |
23bcd5eb CLG |
745 | target_ulong opcode, |
746 | target_ulong *args) | |
747 | { | |
ce2918cb | 748 | SpaprXive *xive = spapr->xive; |
23bcd5eb CLG |
749 | XiveEAS eas, new_eas; |
750 | target_ulong flags = args[0]; | |
751 | target_ulong lisn = args[1]; | |
752 | target_ulong target = args[2]; | |
753 | target_ulong priority = args[3]; | |
754 | target_ulong eisn = args[4]; | |
755 | uint8_t end_blk; | |
756 | uint32_t end_idx; | |
757 | ||
758 | if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { | |
759 | return H_FUNCTION; | |
760 | } | |
761 | ||
762 | if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { | |
763 | return H_PARAMETER; | |
764 | } | |
765 | ||
766 | if (lisn >= xive->nr_irqs) { | |
767 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", | |
768 | lisn); | |
769 | return H_P2; | |
770 | } | |
771 | ||
772 | eas = xive->eat[lisn]; | |
773 | if (!xive_eas_is_valid(&eas)) { | |
774 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", | |
775 | lisn); | |
776 | return H_P2; | |
777 | } | |
778 | ||
779 | /* priority 0xff is used to reset the EAS */ | |
780 | if (priority == 0xff) { | |
781 | new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); | |
782 | goto out; | |
783 | } | |
784 | ||
785 | if (flags & SPAPR_XIVE_SRC_MASK) { | |
786 | new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); | |
787 | } else { | |
788 | new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); | |
789 | } | |
790 | ||
791 | if (spapr_xive_priority_is_reserved(priority)) { | |
792 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld | |
793 | " is reserved\n", priority); | |
794 | return H_P4; | |
795 | } | |
796 | ||
797 | /* | |
798 | * Validate that "target" is part of the list of threads allocated | |
799 | * to the partition. For that, find the END corresponding to the | |
800 | * target. | |
801 | */ | |
802 | if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { | |
803 | return H_P3; | |
804 | } | |
805 | ||
806 | new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); | |
807 | new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); | |
808 | ||
809 | if (flags & SPAPR_XIVE_SRC_SET_EISN) { | |
810 | new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); | |
811 | } | |
812 | ||
0c575703 CLG |
813 | if (kvm_irqchip_in_kernel()) { |
814 | Error *local_err = NULL; | |
815 | ||
816 | kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); | |
817 | if (local_err) { | |
818 | error_report_err(local_err); | |
819 | return H_HARDWARE; | |
820 | } | |
821 | } | |
822 | ||
23bcd5eb CLG |
823 | out: |
824 | xive->eat[lisn] = new_eas; | |
825 | return H_SUCCESS; | |
826 | } | |
827 | ||
828 | /* | |
829 | * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which | |
830 | * target/priority pair is assigned to the specified Logical Interrupt | |
831 | * Source. | |
832 | * | |
833 | * Parameters: | |
834 | * Input: | |
835 | * - R4: "flags" | |
836 | * Bits 0-63 Reserved | |
837 | * - R5: "lisn" is per "interrupts", "interrupt-map", or | |
838 | * "ibm,xive-lisn-ranges" properties, or as returned by the | |
839 | * ibm,query-interrupt-source-number RTAS call, or as | |
840 | * returned by the H_ALLOCATE_VAS_WINDOW hcall | |
841 | * | |
842 | * Output: | |
843 | * - R4: Target to which the specified Logical Interrupt Source is | |
844 | * assigned | |
845 | * - R5: Priority to which the specified Logical Interrupt Source is | |
846 | * assigned | |
847 | * - R6: EISN for the specified Logical Interrupt Source (this will be | |
848 | * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) | |
849 | */ | |
850 | static target_ulong h_int_get_source_config(PowerPCCPU *cpu, | |
ce2918cb | 851 | SpaprMachineState *spapr, |
23bcd5eb CLG |
852 | target_ulong opcode, |
853 | target_ulong *args) | |
854 | { | |
ce2918cb | 855 | SpaprXive *xive = spapr->xive; |
23bcd5eb CLG |
856 | target_ulong flags = args[0]; |
857 | target_ulong lisn = args[1]; | |
858 | XiveEAS eas; | |
859 | XiveEND *end; | |
860 | uint8_t nvt_blk; | |
861 | uint32_t end_idx, nvt_idx; | |
862 | ||
863 | if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { | |
864 | return H_FUNCTION; | |
865 | } | |
866 | ||
867 | if (flags) { | |
868 | return H_PARAMETER; | |
869 | } | |
870 | ||
871 | if (lisn >= xive->nr_irqs) { | |
872 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", | |
873 | lisn); | |
874 | return H_P2; | |
875 | } | |
876 | ||
877 | eas = xive->eat[lisn]; | |
878 | if (!xive_eas_is_valid(&eas)) { | |
879 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", | |
880 | lisn); | |
881 | return H_P2; | |
882 | } | |
883 | ||
884 | /* EAS_END_BLOCK is unused on sPAPR */ | |
885 | end_idx = xive_get_field64(EAS_END_INDEX, eas.w); | |
886 | ||
887 | assert(end_idx < xive->nr_ends); | |
888 | end = &xive->endt[end_idx]; | |
889 | ||
890 | nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); | |
891 | nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); | |
892 | args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); | |
893 | ||
894 | if (xive_eas_is_masked(&eas)) { | |
895 | args[1] = 0xff; | |
896 | } else { | |
897 | args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); | |
898 | } | |
899 | ||
900 | args[2] = xive_get_field64(EAS_END_DATA, eas.w); | |
901 | ||
902 | return H_SUCCESS; | |
903 | } | |
904 | ||
905 | /* | |
906 | * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real | |
907 | * address of the notification management page associated with the | |
908 | * specified target and priority. | |
909 | * | |
910 | * Parameters: | |
911 | * Input: | |
912 | * - R4: "flags" | |
913 | * Bits 0-63 Reserved | |
914 | * - R5: "target" is per "ibm,ppc-interrupt-server#s" or | |
915 | * "ibm,ppc-interrupt-gserver#s" | |
916 | * - R6: "priority" is a valid priority not in | |
917 | * "ibm,plat-res-int-priorities" | |
918 | * | |
919 | * Output: | |
920 | * - R4: Logical real address of notification page | |
921 | * - R5: Power of 2 page size of the notification page | |
922 | */ | |
923 | static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, | |
ce2918cb | 924 | SpaprMachineState *spapr, |
23bcd5eb CLG |
925 | target_ulong opcode, |
926 | target_ulong *args) | |
927 | { | |
ce2918cb | 928 | SpaprXive *xive = spapr->xive; |
23bcd5eb CLG |
929 | XiveENDSource *end_xsrc = &xive->end_source; |
930 | target_ulong flags = args[0]; | |
931 | target_ulong target = args[1]; | |
932 | target_ulong priority = args[2]; | |
933 | XiveEND *end; | |
934 | uint8_t end_blk; | |
935 | uint32_t end_idx; | |
936 | ||
937 | if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { | |
938 | return H_FUNCTION; | |
939 | } | |
940 | ||
941 | if (flags) { | |
942 | return H_PARAMETER; | |
943 | } | |
944 | ||
945 | /* | |
946 | * H_STATE should be returned if a H_INT_RESET is in progress. | |
947 | * This is not needed when running the emulation under QEMU | |
948 | */ | |
949 | ||
950 | if (spapr_xive_priority_is_reserved(priority)) { | |
951 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld | |
952 | " is reserved\n", priority); | |
953 | return H_P3; | |
954 | } | |
955 | ||
956 | /* | |
957 | * Validate that "target" is part of the list of threads allocated | |
958 | * to the partition. For that, find the END corresponding to the | |
959 | * target. | |
960 | */ | |
961 | if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { | |
962 | return H_P2; | |
963 | } | |
964 | ||
965 | assert(end_idx < xive->nr_ends); | |
966 | end = &xive->endt[end_idx]; | |
967 | ||
968 | args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; | |
969 | if (xive_end_is_enqueue(end)) { | |
970 | args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; | |
971 | } else { | |
972 | args[1] = 0; | |
973 | } | |
974 | ||
975 | return H_SUCCESS; | |
976 | } | |
977 | ||
978 | /* | |
979 | * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for | |
980 | * a given "target" and "priority". It is also used to set the | |
981 | * notification config associated with the EQ. An EQ size of 0 is | |
982 | * used to reset the EQ config for a given target and priority. If | |
983 | * resetting the EQ config, the END associated with the given "target" | |
984 | * and "priority" will be changed to disable queueing. | |
985 | * | |
986 | * Upon return from the hcall(), no additional interrupts will be | |
987 | * directed to the old EQ (if one was set). The old EQ (if one was | |
988 | * set) should be investigated for interrupts that occurred prior to | |
989 | * or during the hcall(). | |
990 | * | |
991 | * Parameters: | |
992 | * Input: | |
993 | * - R4: "flags" | |
994 | * Bits 0-62: Reserved | |
995 | * Bit 63: Unconditional Notify (n) per the XIVE spec | |
996 | * - R5: "target" is per "ibm,ppc-interrupt-server#s" or | |
997 | * "ibm,ppc-interrupt-gserver#s" | |
998 | * - R6: "priority" is a valid priority not in | |
999 | * "ibm,plat-res-int-priorities" | |
1000 | * - R7: "eventQueue": The logical real address of the start of the EQ | |
1001 | * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" | |
1002 | * | |
1003 | * Output: | |
1004 | * - None | |
1005 | */ | |
1006 | ||
1007 | #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) | |
1008 | ||
1009 | static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, | |
ce2918cb | 1010 | SpaprMachineState *spapr, |
23bcd5eb CLG |
1011 | target_ulong opcode, |
1012 | target_ulong *args) | |
1013 | { | |
ce2918cb | 1014 | SpaprXive *xive = spapr->xive; |
23bcd5eb CLG |
1015 | target_ulong flags = args[0]; |
1016 | target_ulong target = args[1]; | |
1017 | target_ulong priority = args[2]; | |
1018 | target_ulong qpage = args[3]; | |
1019 | target_ulong qsize = args[4]; | |
1020 | XiveEND end; | |
1021 | uint8_t end_blk, nvt_blk; | |
1022 | uint32_t end_idx, nvt_idx; | |
1023 | ||
1024 | if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { | |
1025 | return H_FUNCTION; | |
1026 | } | |
1027 | ||
1028 | if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { | |
1029 | return H_PARAMETER; | |
1030 | } | |
1031 | ||
1032 | /* | |
1033 | * H_STATE should be returned if a H_INT_RESET is in progress. | |
1034 | * This is not needed when running the emulation under QEMU | |
1035 | */ | |
1036 | ||
1037 | if (spapr_xive_priority_is_reserved(priority)) { | |
1038 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld | |
1039 | " is reserved\n", priority); | |
1040 | return H_P3; | |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * Validate that "target" is part of the list of threads allocated | |
1045 | * to the partition. For that, find the END corresponding to the | |
1046 | * target. | |
1047 | */ | |
1048 | ||
1049 | if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { | |
1050 | return H_P2; | |
1051 | } | |
1052 | ||
1053 | assert(end_idx < xive->nr_ends); | |
1054 | memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); | |
1055 | ||
1056 | switch (qsize) { | |
1057 | case 12: | |
1058 | case 16: | |
1059 | case 21: | |
1060 | case 24: | |
7f9136f9 CLG |
1061 | if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { |
1062 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx | |
1063 | " is not naturally aligned with %" HWADDR_PRIx "\n", | |
1064 | qpage, (hwaddr)1 << qsize); | |
1065 | return H_P4; | |
1066 | } | |
23bcd5eb CLG |
1067 | end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); |
1068 | end.w3 = cpu_to_be32(qpage & 0xffffffff); | |
1069 | end.w0 |= cpu_to_be32(END_W0_ENQUEUE); | |
1070 | end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); | |
1071 | break; | |
1072 | case 0: | |
1073 | /* reset queue and disable queueing */ | |
1074 | spapr_xive_end_reset(&end); | |
1075 | goto out; | |
1076 | ||
1077 | default: | |
1078 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", | |
1079 | qsize); | |
1080 | return H_P5; | |
1081 | } | |
1082 | ||
1083 | if (qsize) { | |
1084 | hwaddr plen = 1 << qsize; | |
1085 | void *eq; | |
1086 | ||
1087 | /* | |
1088 | * Validate the guest EQ. We should also check that the queue | |
1089 | * has been zeroed by the OS. | |
1090 | */ | |
1091 | eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, | |
1092 | MEMTXATTRS_UNSPECIFIED); | |
1093 | if (plen != 1 << qsize) { | |
1094 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" | |
1095 | HWADDR_PRIx "\n", qpage); | |
1096 | return H_P4; | |
1097 | } | |
1098 | address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); | |
1099 | } | |
1100 | ||
1101 | /* "target" should have been validated above */ | |
1102 | if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { | |
1103 | g_assert_not_reached(); | |
1104 | } | |
1105 | ||
1106 | /* | |
1107 | * Ensure the priority and target are correctly set (they will not | |
1108 | * be right after allocation) | |
1109 | */ | |
1110 | end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | | |
1111 | xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); | |
1112 | end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); | |
1113 | ||
1114 | if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { | |
1115 | end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); | |
1116 | } else { | |
1117 | end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); | |
1118 | } | |
1119 | ||
1120 | /* | |
1121 | * The generation bit for the END starts at 1 and The END page | |
1122 | * offset counter starts at 0. | |
1123 | */ | |
1124 | end.w1 = cpu_to_be32(END_W1_GENERATION) | | |
1125 | xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); | |
1126 | end.w0 |= cpu_to_be32(END_W0_VALID); | |
1127 | ||
1128 | /* | |
1129 | * TODO: issue syncs required to ensure all in-flight interrupts | |
1130 | * are complete on the old END | |
1131 | */ | |
1132 | ||
1133 | out: | |
0c575703 CLG |
1134 | if (kvm_irqchip_in_kernel()) { |
1135 | Error *local_err = NULL; | |
1136 | ||
1137 | kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); | |
1138 | if (local_err) { | |
1139 | error_report_err(local_err); | |
1140 | return H_HARDWARE; | |
1141 | } | |
1142 | } | |
1143 | ||
23bcd5eb CLG |
1144 | /* Update END */ |
1145 | memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); | |
1146 | return H_SUCCESS; | |
1147 | } | |
1148 | ||
1149 | /* | |
1150 | * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given | |
1151 | * target and priority. | |
1152 | * | |
1153 | * Parameters: | |
1154 | * Input: | |
1155 | * - R4: "flags" | |
1156 | * Bits 0-62: Reserved | |
1157 | * Bit 63: Debug: Return debug data | |
1158 | * - R5: "target" is per "ibm,ppc-interrupt-server#s" or | |
1159 | * "ibm,ppc-interrupt-gserver#s" | |
1160 | * - R6: "priority" is a valid priority not in | |
1161 | * "ibm,plat-res-int-priorities" | |
1162 | * | |
1163 | * Output: | |
1164 | * - R4: "flags": | |
1165 | * Bits 0-61: Reserved | |
1166 | * Bit 62: The value of Event Queue Generation Number (g) per | |
1167 | * the XIVE spec if "Debug" = 1 | |
1168 | * Bit 63: The value of Unconditional Notify (n) per the XIVE spec | |
1169 | * - R5: The logical real address of the start of the EQ | |
1170 | * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" | |
1171 | * - R7: The value of Event Queue Offset Counter per XIVE spec | |
1172 | * if "Debug" = 1, else 0 | |
1173 | * | |
1174 | */ | |
1175 | ||
1176 | #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) | |
1177 | ||
1178 | static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, | |
ce2918cb | 1179 | SpaprMachineState *spapr, |
23bcd5eb CLG |
1180 | target_ulong opcode, |
1181 | target_ulong *args) | |
1182 | { | |
ce2918cb | 1183 | SpaprXive *xive = spapr->xive; |
23bcd5eb CLG |
1184 | target_ulong flags = args[0]; |
1185 | target_ulong target = args[1]; | |
1186 | target_ulong priority = args[2]; | |
1187 | XiveEND *end; | |
1188 | uint8_t end_blk; | |
1189 | uint32_t end_idx; | |
1190 | ||
1191 | if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { | |
1192 | return H_FUNCTION; | |
1193 | } | |
1194 | ||
1195 | if (flags & ~SPAPR_XIVE_END_DEBUG) { | |
1196 | return H_PARAMETER; | |
1197 | } | |
1198 | ||
1199 | /* | |
1200 | * H_STATE should be returned if a H_INT_RESET is in progress. | |
1201 | * This is not needed when running the emulation under QEMU | |
1202 | */ | |
1203 | ||
1204 | if (spapr_xive_priority_is_reserved(priority)) { | |
1205 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld | |
1206 | " is reserved\n", priority); | |
1207 | return H_P3; | |
1208 | } | |
1209 | ||
1210 | /* | |
1211 | * Validate that "target" is part of the list of threads allocated | |
1212 | * to the partition. For that, find the END corresponding to the | |
1213 | * target. | |
1214 | */ | |
1215 | if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { | |
1216 | return H_P2; | |
1217 | } | |
1218 | ||
1219 | assert(end_idx < xive->nr_ends); | |
1220 | end = &xive->endt[end_idx]; | |
1221 | ||
1222 | args[0] = 0; | |
1223 | if (xive_end_is_notify(end)) { | |
1224 | args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; | |
1225 | } | |
1226 | ||
1227 | if (xive_end_is_enqueue(end)) { | |
13df9324 | 1228 | args[1] = xive_end_qaddr(end); |
23bcd5eb CLG |
1229 | args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; |
1230 | } else { | |
1231 | args[1] = 0; | |
1232 | args[2] = 0; | |
1233 | } | |
1234 | ||
0c575703 CLG |
1235 | if (kvm_irqchip_in_kernel()) { |
1236 | Error *local_err = NULL; | |
1237 | ||
1238 | kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); | |
1239 | if (local_err) { | |
1240 | error_report_err(local_err); | |
1241 | return H_HARDWARE; | |
1242 | } | |
1243 | } | |
1244 | ||
23bcd5eb CLG |
1245 | /* TODO: do we need any locking on the END ? */ |
1246 | if (flags & SPAPR_XIVE_END_DEBUG) { | |
1247 | /* Load the event queue generation number into the return flags */ | |
1248 | args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; | |
1249 | ||
1250 | /* Load R7 with the event queue offset counter */ | |
1251 | args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); | |
1252 | } else { | |
1253 | args[3] = 0; | |
1254 | } | |
1255 | ||
1256 | return H_SUCCESS; | |
1257 | } | |
1258 | ||
1259 | /* | |
1260 | * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the | |
1261 | * reporting cache line pair for the calling thread. The reporting | |
1262 | * cache lines will contain the OS interrupt context when the OS | |
1263 | * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS | |
1264 | * interrupt. The reporting cache lines can be reset by inputting -1 | |
1265 | * in "reportingLine". Issuing the CI store byte without reporting | |
1266 | * cache lines registered will result in the data not being accessible | |
1267 | * to the OS. | |
1268 | * | |
1269 | * Parameters: | |
1270 | * Input: | |
1271 | * - R4: "flags" | |
1272 | * Bits 0-63: Reserved | |
1273 | * - R5: "reportingLine": The logical real address of the reporting cache | |
1274 | * line pair | |
1275 | * | |
1276 | * Output: | |
1277 | * - None | |
1278 | */ | |
1279 | static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, | |
ce2918cb | 1280 | SpaprMachineState *spapr, |
23bcd5eb CLG |
1281 | target_ulong opcode, |
1282 | target_ulong *args) | |
1283 | { | |
1284 | if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { | |
1285 | return H_FUNCTION; | |
1286 | } | |
1287 | ||
1288 | /* | |
1289 | * H_STATE should be returned if a H_INT_RESET is in progress. | |
1290 | * This is not needed when running the emulation under QEMU | |
1291 | */ | |
1292 | ||
1293 | /* TODO: H_INT_SET_OS_REPORTING_LINE */ | |
1294 | return H_FUNCTION; | |
1295 | } | |
1296 | ||
1297 | /* | |
1298 | * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical | |
1299 | * real address of the reporting cache line pair set for the input | |
1300 | * "target". If no reporting cache line pair has been set, -1 is | |
1301 | * returned. | |
1302 | * | |
1303 | * Parameters: | |
1304 | * Input: | |
1305 | * - R4: "flags" | |
1306 | * Bits 0-63: Reserved | |
1307 | * - R5: "target" is per "ibm,ppc-interrupt-server#s" or | |
1308 | * "ibm,ppc-interrupt-gserver#s" | |
1309 | * - R6: "reportingLine": The logical real address of the reporting | |
1310 | * cache line pair | |
1311 | * | |
1312 | * Output: | |
1313 | * - R4: The logical real address of the reporting line if set, else -1 | |
1314 | */ | |
1315 | static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, | |
ce2918cb | 1316 | SpaprMachineState *spapr, |
23bcd5eb CLG |
1317 | target_ulong opcode, |
1318 | target_ulong *args) | |
1319 | { | |
1320 | if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { | |
1321 | return H_FUNCTION; | |
1322 | } | |
1323 | ||
1324 | /* | |
1325 | * H_STATE should be returned if a H_INT_RESET is in progress. | |
1326 | * This is not needed when running the emulation under QEMU | |
1327 | */ | |
1328 | ||
1329 | /* TODO: H_INT_GET_OS_REPORTING_LINE */ | |
1330 | return H_FUNCTION; | |
1331 | } | |
1332 | ||
1333 | /* | |
1334 | * The H_INT_ESB hcall() is used to issue a load or store to the ESB | |
1335 | * page for the input "lisn". This hcall is only supported for LISNs | |
1336 | * that have the ESB hcall flag set to 1 when returned from hcall() | |
1337 | * H_INT_GET_SOURCE_INFO. | |
1338 | * | |
1339 | * Parameters: | |
1340 | * Input: | |
1341 | * - R4: "flags" | |
1342 | * Bits 0-62: Reserved | |
1343 | * bit 63: Store: Store=1, store operation, else load operation | |
1344 | * - R5: "lisn" is per "interrupts", "interrupt-map", or | |
1345 | * "ibm,xive-lisn-ranges" properties, or as returned by the | |
1346 | * ibm,query-interrupt-source-number RTAS call, or as | |
1347 | * returned by the H_ALLOCATE_VAS_WINDOW hcall | |
1348 | * - R6: "esbOffset" is the offset into the ESB page for the load or | |
1349 | * store operation | |
1350 | * - R7: "storeData" is the data to write for a store operation | |
1351 | * | |
1352 | * Output: | |
1353 | * - R4: The value of the load if load operation, else -1 | |
1354 | */ | |
1355 | ||
1356 | #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) | |
1357 | ||
1358 | static target_ulong h_int_esb(PowerPCCPU *cpu, | |
ce2918cb | 1359 | SpaprMachineState *spapr, |
23bcd5eb CLG |
1360 | target_ulong opcode, |
1361 | target_ulong *args) | |
1362 | { | |
ce2918cb | 1363 | SpaprXive *xive = spapr->xive; |
23bcd5eb CLG |
1364 | XiveEAS eas; |
1365 | target_ulong flags = args[0]; | |
1366 | target_ulong lisn = args[1]; | |
1367 | target_ulong offset = args[2]; | |
1368 | target_ulong data = args[3]; | |
1369 | hwaddr mmio_addr; | |
1370 | XiveSource *xsrc = &xive->source; | |
1371 | ||
1372 | if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { | |
1373 | return H_FUNCTION; | |
1374 | } | |
1375 | ||
1376 | if (flags & ~SPAPR_XIVE_ESB_STORE) { | |
1377 | return H_PARAMETER; | |
1378 | } | |
1379 | ||
1380 | if (lisn >= xive->nr_irqs) { | |
1381 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", | |
1382 | lisn); | |
1383 | return H_P2; | |
1384 | } | |
1385 | ||
1386 | eas = xive->eat[lisn]; | |
1387 | if (!xive_eas_is_valid(&eas)) { | |
1388 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", | |
1389 | lisn); | |
1390 | return H_P2; | |
1391 | } | |
1392 | ||
1393 | if (offset > (1ull << xsrc->esb_shift)) { | |
1394 | return H_P3; | |
1395 | } | |
1396 | ||
0c575703 CLG |
1397 | if (kvm_irqchip_in_kernel()) { |
1398 | args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, | |
1399 | flags & SPAPR_XIVE_ESB_STORE); | |
1400 | } else { | |
1401 | mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; | |
23bcd5eb | 1402 | |
0c575703 CLG |
1403 | if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, |
1404 | (flags & SPAPR_XIVE_ESB_STORE))) { | |
1405 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" | |
1406 | HWADDR_PRIx "\n", mmio_addr); | |
1407 | return H_HARDWARE; | |
1408 | } | |
1409 | args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; | |
23bcd5eb | 1410 | } |
23bcd5eb CLG |
1411 | return H_SUCCESS; |
1412 | } | |
1413 | ||
1414 | /* | |
1415 | * The H_INT_SYNC hcall() is used to issue hardware syncs that will | |
1416 | * ensure any in flight events for the input lisn are in the event | |
1417 | * queue. | |
1418 | * | |
1419 | * Parameters: | |
1420 | * Input: | |
1421 | * - R4: "flags" | |
1422 | * Bits 0-63: Reserved | |
1423 | * - R5: "lisn" is per "interrupts", "interrupt-map", or | |
1424 | * "ibm,xive-lisn-ranges" properties, or as returned by the | |
1425 | * ibm,query-interrupt-source-number RTAS call, or as | |
1426 | * returned by the H_ALLOCATE_VAS_WINDOW hcall | |
1427 | * | |
1428 | * Output: | |
1429 | * - None | |
1430 | */ | |
1431 | static target_ulong h_int_sync(PowerPCCPU *cpu, | |
ce2918cb | 1432 | SpaprMachineState *spapr, |
23bcd5eb CLG |
1433 | target_ulong opcode, |
1434 | target_ulong *args) | |
1435 | { | |
ce2918cb | 1436 | SpaprXive *xive = spapr->xive; |
23bcd5eb CLG |
1437 | XiveEAS eas; |
1438 | target_ulong flags = args[0]; | |
1439 | target_ulong lisn = args[1]; | |
1440 | ||
1441 | if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { | |
1442 | return H_FUNCTION; | |
1443 | } | |
1444 | ||
1445 | if (flags) { | |
1446 | return H_PARAMETER; | |
1447 | } | |
1448 | ||
1449 | if (lisn >= xive->nr_irqs) { | |
1450 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", | |
1451 | lisn); | |
1452 | return H_P2; | |
1453 | } | |
1454 | ||
1455 | eas = xive->eat[lisn]; | |
1456 | if (!xive_eas_is_valid(&eas)) { | |
1457 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", | |
1458 | lisn); | |
1459 | return H_P2; | |
1460 | } | |
1461 | ||
1462 | /* | |
1463 | * H_STATE should be returned if a H_INT_RESET is in progress. | |
1464 | * This is not needed when running the emulation under QEMU | |
1465 | */ | |
1466 | ||
0c575703 CLG |
1467 | /* |
1468 | * This is not real hardware. Nothing to be done unless when | |
1469 | * under KVM | |
1470 | */ | |
1471 | ||
1472 | if (kvm_irqchip_in_kernel()) { | |
1473 | Error *local_err = NULL; | |
1474 | ||
1475 | kvmppc_xive_sync_source(xive, lisn, &local_err); | |
1476 | if (local_err) { | |
1477 | error_report_err(local_err); | |
1478 | return H_HARDWARE; | |
1479 | } | |
1480 | } | |
23bcd5eb CLG |
1481 | return H_SUCCESS; |
1482 | } | |
1483 | ||
1484 | /* | |
1485 | * The H_INT_RESET hcall() is used to reset all of the partition's | |
1486 | * interrupt exploitation structures to their initial state. This | |
1487 | * means losing all previously set interrupt state set via | |
1488 | * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. | |
1489 | * | |
1490 | * Parameters: | |
1491 | * Input: | |
1492 | * - R4: "flags" | |
1493 | * Bits 0-63: Reserved | |
1494 | * | |
1495 | * Output: | |
1496 | * - None | |
1497 | */ | |
1498 | static target_ulong h_int_reset(PowerPCCPU *cpu, | |
ce2918cb | 1499 | SpaprMachineState *spapr, |
23bcd5eb CLG |
1500 | target_ulong opcode, |
1501 | target_ulong *args) | |
1502 | { | |
ce2918cb | 1503 | SpaprXive *xive = spapr->xive; |
23bcd5eb CLG |
1504 | target_ulong flags = args[0]; |
1505 | ||
1506 | if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { | |
1507 | return H_FUNCTION; | |
1508 | } | |
1509 | ||
1510 | if (flags) { | |
1511 | return H_PARAMETER; | |
1512 | } | |
1513 | ||
1514 | device_reset(DEVICE(xive)); | |
0c575703 CLG |
1515 | |
1516 | if (kvm_irqchip_in_kernel()) { | |
1517 | Error *local_err = NULL; | |
1518 | ||
1519 | kvmppc_xive_reset(xive, &local_err); | |
1520 | if (local_err) { | |
1521 | error_report_err(local_err); | |
1522 | return H_HARDWARE; | |
1523 | } | |
1524 | } | |
23bcd5eb CLG |
1525 | return H_SUCCESS; |
1526 | } | |
1527 | ||
ce2918cb | 1528 | void spapr_xive_hcall_init(SpaprMachineState *spapr) |
23bcd5eb CLG |
1529 | { |
1530 | spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); | |
1531 | spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); | |
1532 | spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); | |
1533 | spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); | |
1534 | spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); | |
1535 | spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); | |
1536 | spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, | |
1537 | h_int_set_os_reporting_line); | |
1538 | spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, | |
1539 | h_int_get_os_reporting_line); | |
1540 | spapr_register_hypercall(H_INT_ESB, h_int_esb); | |
1541 | spapr_register_hypercall(H_INT_SYNC, h_int_sync); | |
1542 | spapr_register_hypercall(H_INT_RESET, h_int_reset); | |
1543 | } | |
6e21de4a | 1544 | |
ce2918cb | 1545 | void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, |
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1546 | uint32_t phandle) |
1547 | { | |
ce2918cb | 1548 | SpaprXive *xive = spapr->xive; |
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1549 | int node; |
1550 | uint64_t timas[2 * 2]; | |
1551 | /* Interrupt number ranges for the IPIs */ | |
1552 | uint32_t lisn_ranges[] = { | |
1553 | cpu_to_be32(0), | |
1554 | cpu_to_be32(nr_servers), | |
1555 | }; | |
1556 | /* | |
1557 | * EQ size - the sizes of pages supported by the system 4K, 64K, | |
1558 | * 2M, 16M. We only advertise 64K for the moment. | |
1559 | */ | |
1560 | uint32_t eq_sizes[] = { | |
1561 | cpu_to_be32(16), /* 64K */ | |
1562 | }; | |
1563 | /* | |
1564 | * The following array is in sync with the reserved priorities | |
1565 | * defined by the 'spapr_xive_priority_is_reserved' routine. | |
1566 | */ | |
1567 | uint32_t plat_res_int_priorities[] = { | |
1568 | cpu_to_be32(7), /* start */ | |
1569 | cpu_to_be32(0xf8), /* count */ | |
1570 | }; | |
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1571 | |
1572 | /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ | |
1573 | timas[0] = cpu_to_be64(xive->tm_base + | |
1574 | XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); | |
1575 | timas[1] = cpu_to_be64(1ull << TM_SHIFT); | |
1576 | timas[2] = cpu_to_be64(xive->tm_base + | |
1577 | XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); | |
1578 | timas[3] = cpu_to_be64(1ull << TM_SHIFT); | |
1579 | ||
743ed566 | 1580 | _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); |
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1581 | |
1582 | _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); | |
1583 | _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); | |
1584 | ||
1585 | _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); | |
1586 | _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, | |
1587 | sizeof(eq_sizes))); | |
1588 | _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, | |
1589 | sizeof(lisn_ranges))); | |
1590 | ||
1591 | /* For Linux to link the LSIs to the interrupt controller. */ | |
1592 | _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); | |
1593 | _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); | |
1594 | ||
1595 | /* For SLOF */ | |
1596 | _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); | |
1597 | _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); | |
1598 | ||
1599 | /* | |
1600 | * The "ibm,plat-res-int-priorities" property defines the priority | |
1601 | * ranges reserved by the hypervisor | |
1602 | */ | |
1603 | _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", | |
1604 | plat_res_int_priorities, sizeof(plat_res_int_priorities))); | |
1605 | } |