[mirror_qemu.git] / hw / intc / xics_spapr.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
 *
 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

#include "qemu/osdep.h"
#include "trace.h"
#include "qemu/timer.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/xics_spapr.h"
#include "hw/ppc/fdt.h"
#include "qapi/visitor.h"

/*
 * Guest interfaces
 */

static bool check_emulated_xics(SpaprMachineState *spapr, const char *func)
{
    if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ||
        kvm_irqchip_in_kernel()) {
        error_report("pseries: %s must only be called for emulated XICS",
                     func);
        return false;
    }

    return true;
}

#define CHECK_EMULATED_XICS_HCALL(spapr)               \
    do {                                               \
        if (!check_emulated_xics((spapr), __func__)) { \
            return H_HARDWARE;                         \
        }                                              \
    } while (0)

static target_ulong h_cppr(PowerPCCPU *cpu, SpaprMachineState *spapr,
                           target_ulong opcode, target_ulong *args)
{
    target_ulong cppr = args[0];

    CHECK_EMULATED_XICS_HCALL(spapr);

    icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
    return H_SUCCESS;
}

static target_ulong h_ipi(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong mfrr = args[1];
    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);

    CHECK_EMULATED_XICS_HCALL(spapr);

    if (!icp) {
        return H_PARAMETER;
    }

    icp_set_mfrr(icp, mfrr);
    return H_SUCCESS;
}

static target_ulong h_xirr(PowerPCCPU *cpu, SpaprMachineState *spapr,
                           target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);

    CHECK_EMULATED_XICS_HCALL(spapr);

    args[0] = xirr;
    return H_SUCCESS;
}

static target_ulong h_xirr_x(PowerPCCPU *cpu, SpaprMachineState *spapr,
                             target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);

    CHECK_EMULATED_XICS_HCALL(spapr);

    args[0] = xirr;
    args[1] = cpu_get_host_ticks();
    return H_SUCCESS;
}

static target_ulong h_eoi(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong xirr = args[0];

    CHECK_EMULATED_XICS_HCALL(spapr);

    icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
    return H_SUCCESS;
}

static target_ulong h_ipoll(PowerPCCPU *cpu, SpaprMachineState *spapr,
                            target_ulong opcode, target_ulong *args)
{
    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
    uint32_t mfrr;
    uint32_t xirr;

    CHECK_EMULATED_XICS_HCALL(spapr);

    if (!icp) {
        return H_PARAMETER;
    }

    xirr = icp_ipoll(icp, &mfrr);

    args[0] = xirr;
    args[1] = mfrr;

    return H_SUCCESS;
}

#define CHECK_EMULATED_XICS_RTAS(spapr, rets)          \
    do {                                               \
        if (!check_emulated_xics((spapr), __func__)) { \
            rtas_st((rets), 0, RTAS_OUT_HW_ERROR);     \
            return;                                    \
        }                                              \
    } while (0)

static void rtas_set_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno, server, priority;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 3) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);
    server = rtas_ld(args, 1);
    priority = rtas_ld(args, 2);

    if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server)
        || (priority > 0xff)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_write_xive(ics, srcno, server, priority, priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void rtas_get_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 1) || (nret != 3)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
    srcno = nr - ics->offset;
    rtas_st(rets, 1, ics->irqs[srcno].server);
    rtas_st(rets, 2, ics->irqs[srcno].priority);
}

static void rtas_int_off(PowerPCCPU *cpu, SpaprMachineState *spapr,
                         uint32_t token,
                         uint32_t nargs, target_ulong args,
                         uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
                   ics->irqs[srcno].priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void rtas_int_on(PowerPCCPU *cpu, SpaprMachineState *spapr,
                        uint32_t token,
                        uint32_t nargs, target_ulong args,
                        uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_write_xive(ics, srcno, ics->irqs[srcno].server,
                   ics->irqs[srcno].saved_priority,
                   ics->irqs[srcno].saved_priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void ics_spapr_realize(DeviceState *dev, Error **errp)
{
    ICSState *ics = ICS_SPAPR(dev);
    ICSStateClass *icsc = ICS_GET_CLASS(ics);
    Error *local_err = NULL;

    icsc->parent_realize(dev, &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
    spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
    spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
    spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);

    spapr_register_hypercall(H_CPPR, h_cppr);
    spapr_register_hypercall(H_IPI, h_ipi);
    spapr_register_hypercall(H_XIRR, h_xirr);
    spapr_register_hypercall(H_XIRR_X, h_xirr_x);
    spapr_register_hypercall(H_EOI, h_eoi);
    spapr_register_hypercall(H_IPOLL, h_ipoll);
}

static void xics_spapr_dt(SpaprInterruptController *intc, uint32_t nr_servers,
                          void *fdt, uint32_t phandle)
{
    uint32_t interrupt_server_ranges_prop[] = {
        0, cpu_to_be32(nr_servers),
    };
    int node;

    _FDT(node = fdt_add_subnode(fdt, 0, "interrupt-controller"));

    _FDT(fdt_setprop_string(fdt, node, "device_type",
                            "PowerPC-External-Interrupt-Presentation"));
    _FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
    _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
    _FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
                     interrupt_server_ranges_prop,
                     sizeof(interrupt_server_ranges_prop)));
    _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
    _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
    _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
}

static int xics_spapr_cpu_intc_create(SpaprInterruptController *intc,
                                       PowerPCCPU *cpu, Error **errp)
{
    ICSState *ics = ICS_SPAPR(intc);
    Object *obj;
    SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);

    obj = icp_create(OBJECT(cpu), TYPE_ICP, ics->xics, errp);
    if (!obj) {
        return -1;
    }

    spapr_cpu->icp = ICP(obj);
    return 0;
}

static void xics_spapr_cpu_intc_reset(SpaprInterruptController *intc,
                                     PowerPCCPU *cpu)
{
    icp_reset(spapr_cpu_state(cpu)->icp);
}

static void xics_spapr_cpu_intc_destroy(SpaprInterruptController *intc,
                                        PowerPCCPU *cpu)
{
    SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);

    icp_destroy(spapr_cpu->icp);
    spapr_cpu->icp = NULL;
}

static int xics_spapr_claim_irq(SpaprInterruptController *intc, int irq,
                                bool lsi, Error **errp)
{
    ICSState *ics = ICS_SPAPR(intc);

    assert(ics);
    assert(ics_valid_irq(ics, irq));

    if (!ics_irq_free(ics, irq - ics->offset)) {
        error_setg(errp, "IRQ %d is not free", irq);
        return -EBUSY;
    }

    ics_set_irq_type(ics, irq - ics->offset, lsi);
    return 0;
}

static void xics_spapr_free_irq(SpaprInterruptController *intc, int irq)
{
    ICSState *ics = ICS_SPAPR(intc);
    uint32_t srcno = irq - ics->offset;

    assert(ics_valid_irq(ics, irq));

    memset(&ics->irqs[srcno], 0, sizeof(ICSIRQState));
}

static void xics_spapr_set_irq(SpaprInterruptController *intc, int irq, int val)
{
    ICSState *ics = ICS_SPAPR(intc);
    uint32_t srcno = irq - ics->offset;

    ics_set_irq(ics, srcno, val);
}

static void xics_spapr_print_info(SpaprInterruptController *intc, Monitor *mon)
{
    ICSState *ics = ICS_SPAPR(intc);
    CPUState *cs;

    CPU_FOREACH(cs) {
        PowerPCCPU *cpu = POWERPC_CPU(cs);

        icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
    }

    ics_pic_print_info(ics, mon);
}

static int xics_spapr_post_load(SpaprInterruptController *intc, int version_id)
{
    if (!kvm_irqchip_in_kernel()) {
        CPUState *cs;
        CPU_FOREACH(cs) {
            PowerPCCPU *cpu = POWERPC_CPU(cs);
            icp_resend(spapr_cpu_state(cpu)->icp);
        }
    }
    return 0;
}

static int xics_spapr_activate(SpaprInterruptController *intc,
                               uint32_t nr_servers, Error **errp)
{
    if (kvm_enabled()) {
        return spapr_irq_init_kvm(xics_kvm_connect, intc, nr_servers, errp);
    }
    return 0;
}

static void xics_spapr_deactivate(SpaprInterruptController *intc)
{
    if (kvm_irqchip_in_kernel()) {
        xics_kvm_disconnect(intc);
    }
}

static void ics_spapr_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    ICSStateClass *isc = ICS_CLASS(klass);
    SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass);

    device_class_set_parent_realize(dc, ics_spapr_realize,
                                    &isc->parent_realize);
    sicc->activate = xics_spapr_activate;
    sicc->deactivate = xics_spapr_deactivate;
    sicc->cpu_intc_create = xics_spapr_cpu_intc_create;
    sicc->cpu_intc_reset = xics_spapr_cpu_intc_reset;
    sicc->cpu_intc_destroy = xics_spapr_cpu_intc_destroy;
    sicc->claim_irq = xics_spapr_claim_irq;
    sicc->free_irq = xics_spapr_free_irq;
    sicc->set_irq = xics_spapr_set_irq;
    sicc->print_info = xics_spapr_print_info;
    sicc->dt = xics_spapr_dt;
    sicc->post_load = xics_spapr_post_load;
}

static const TypeInfo ics_spapr_info = {
    .name = TYPE_ICS_SPAPR,
    .parent = TYPE_ICS,
    .class_init = ics_spapr_class_init,
    .interfaces = (InterfaceInfo[]) {
        { TYPE_SPAPR_INTC },
        { }
    },
};

static void xics_spapr_register_types(void)
{
    type_register_static(&ics_spapr_info);
}

type_init(xics_spapr_register_types)
Commit	Line	Data
9c7027ba BH	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
	5	*
	6	* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27
	28	#include "qemu/osdep.h"
9c7027ba BH	29	#include "trace.h"
	30	#include "qemu/timer.h"
	31	#include "hw/ppc/spapr.h"
a28b9a5a	32	#include "hw/ppc/spapr_cpu_core.h"
9c7027ba	33	#include "hw/ppc/xics.h"
a51d5afc	34	#include "hw/ppc/xics_spapr.h"
9b9a1908	35	#include "hw/ppc/fdt.h"
9c7027ba	36	#include "qapi/visitor.h"
9c7027ba BH	37
	38	/*
	39	* Guest interfaces
	40	*/
	41
25c79a30	42	static bool check_emulated_xics(SpaprMachineState spapr, const char func)
d9715d67	43	{
25c79a30 GK	44	if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) \|\|
	45	kvm_irqchip_in_kernel()) {
	46	error_report("pseries: %s must only be called for emulated XICS",
d9715d67	47	func);
25c79a30	48	return false;
d9715d67 GK	49	}
d9715d67 GK	50
25c79a30	51	return true;
d9715d67 GK	52	}
d9715d67 GK	53
25c79a30 GK	54	#define CHECK_EMULATED_XICS_HCALL(spapr) \
	55	do { \
	56	if (!check_emulated_xics((spapr), __func__)) { \
	57	return H_HARDWARE; \
	58	} \
d9715d67 GK	59	} while (0)
d9715d67 GK	60
ce2918cb	61	static target_ulong h_cppr(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	62	target_ulong opcode, target_ulong *args)
9c7027ba BH	63	{
9c7027ba BH	64	target_ulong cppr = args[0];
9c7027ba BH	65
25c79a30	66	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	67
a28b9a5a	68	icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
9c7027ba BH	69	return H_SUCCESS;
	70	}
	71
ce2918cb	72	static target_ulong h_ipi(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	73	target_ulong opcode, target_ulong *args)
9c7027ba BH	74	{
9c7027ba	75	target_ulong mfrr = args[1];
06747ba6	76	ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
9c7027ba	77
25c79a30	78	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	79
b4f27d71	80	if (!icp) {
9c7027ba BH	81	return H_PARAMETER;
	82	}
	83
b4f27d71	84	icp_set_mfrr(icp, mfrr);
9c7027ba BH	85	return H_SUCCESS;
	86	}
	87
ce2918cb	88	static target_ulong h_xirr(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	89	target_ulong opcode, target_ulong *args)
9c7027ba BH	90	{
a28b9a5a	91	uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
9c7027ba	92
25c79a30	93	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	94
9c7027ba BH	95	args[0] = xirr;
	96	return H_SUCCESS;
	97	}
	98
ce2918cb	99	static target_ulong h_xirr_x(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	100	target_ulong opcode, target_ulong *args)
9c7027ba BH	101	{
a28b9a5a	102	uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
9c7027ba	103
25c79a30	104	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	105
9c7027ba BH	106	args[0] = xirr;
	107	args[1] = cpu_get_host_ticks();
	108	return H_SUCCESS;
	109	}
	110
ce2918cb	111	static target_ulong h_eoi(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	112	target_ulong opcode, target_ulong *args)
9c7027ba BH	113	{
9c7027ba BH	114	target_ulong xirr = args[0];
9c7027ba BH	115
25c79a30	116	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	117
a28b9a5a	118	icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
9c7027ba BH	119	return H_SUCCESS;
	120	}
	121
ce2918cb	122	static target_ulong h_ipoll(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	123	target_ulong opcode, target_ulong *args)
9c7027ba BH	124	{
ebc184be	125	ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
1cbd2220	126	uint32_t mfrr;
ebc184be BH	127	uint32_t xirr;
ebc184be BH	128
25c79a30	129	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	130
ebc184be BH	131	if (!icp) {
	132	return H_PARAMETER;
	133	}
	134
	135	xirr = icp_ipoll(icp, &mfrr);
9c7027ba	136
1cbd2220 BH	137	args[0] = xirr;
1cbd2220 BH	138	args[1] = mfrr;
9c7027ba BH	139
	140	return H_SUCCESS;
	141	}
	142
25c79a30 GK	143	#define CHECK_EMULATED_XICS_RTAS(spapr, rets) \
	144	do { \
	145	if (!check_emulated_xics((spapr), __func__)) { \
	146	rtas_st((rets), 0, RTAS_OUT_HW_ERROR); \
	147	return; \
	148	} \
d9715d67 GK	149	} while (0)
d9715d67 GK	150
ce2918cb	151	static void rtas_set_xive(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	152	uint32_t token,
	153	uint32_t nargs, target_ulong args,
	154	uint32_t nret, target_ulong rets)
	155	{
681bfade	156	ICSState *ics = spapr->ics;
d4d7a59a	157	uint32_t nr, srcno, server, priority;
9c7027ba	158
25c79a30	159	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	160
9c7027ba BH	161	if ((nargs != 3) \|\| (nret != 1)) {
	162	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	163	return;
	164	}
cc706a53 BH	165	if (!ics) {
	166	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	167	return;
	168	}
9c7027ba BH	169
9c7027ba BH	170	nr = rtas_ld(args, 0);
06747ba6	171	server = rtas_ld(args, 1);
9c7027ba BH	172	priority = rtas_ld(args, 2);
9c7027ba BH	173
b4f27d71	174	if (!ics_valid_irq(ics, nr) \|\| !xics_icp_get(XICS_FABRIC(spapr), server)
9c7027ba BH	175	\|\| (priority > 0xff)) {
	176	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	177	return;
	178	}
	179
d4d7a59a	180	srcno = nr - ics->offset;
28976c99	181	ics_write_xive(ics, srcno, server, priority, priority);
9c7027ba BH	182
	183	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	184	}
	185
ce2918cb	186	static void rtas_get_xive(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	187	uint32_t token,
	188	uint32_t nargs, target_ulong args,
	189	uint32_t nret, target_ulong rets)
	190	{
681bfade	191	ICSState *ics = spapr->ics;
d4d7a59a	192	uint32_t nr, srcno;
9c7027ba	193
25c79a30	194	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	195
9c7027ba BH	196	if ((nargs != 1) \|\| (nret != 3)) {
	197	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	198	return;
	199	}
cc706a53 BH	200	if (!ics) {
	201	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	202	return;
	203	}
9c7027ba BH	204
	205	nr = rtas_ld(args, 0);
	206
	207	if (!ics_valid_irq(ics, nr)) {
	208	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	209	return;
	210	}
	211
	212	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
d4d7a59a BH	213	srcno = nr - ics->offset;
	214	rtas_st(rets, 1, ics->irqs[srcno].server);
	215	rtas_st(rets, 2, ics->irqs[srcno].priority);
9c7027ba BH	216	}
9c7027ba BH	217
ce2918cb	218	static void rtas_int_off(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	219	uint32_t token,
	220	uint32_t nargs, target_ulong args,
	221	uint32_t nret, target_ulong rets)
	222	{
681bfade	223	ICSState *ics = spapr->ics;
d4d7a59a	224	uint32_t nr, srcno;
9c7027ba	225
25c79a30	226	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	227
9c7027ba BH	228	if ((nargs != 1) \|\| (nret != 1)) {
	229	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	230	return;
	231	}
cc706a53 BH	232	if (!ics) {
	233	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	234	return;
	235	}
9c7027ba BH	236
	237	nr = rtas_ld(args, 0);
	238
	239	if (!ics_valid_irq(ics, nr)) {
	240	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	241	return;
	242	}
	243
d4d7a59a	244	srcno = nr - ics->offset;
28976c99 DG	245	ics_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
28976c99 DG	246	ics->irqs[srcno].priority);
9c7027ba BH	247
	248	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	249	}
	250
ce2918cb	251	static void rtas_int_on(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	252	uint32_t token,
	253	uint32_t nargs, target_ulong args,
	254	uint32_t nret, target_ulong rets)
	255	{
681bfade	256	ICSState *ics = spapr->ics;
d4d7a59a	257	uint32_t nr, srcno;
9c7027ba	258
25c79a30	259	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	260
9c7027ba BH	261	if ((nargs != 1) \|\| (nret != 1)) {
	262	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	263	return;
	264	}
cc706a53 BH	265	if (!ics) {
	266	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	267	return;
	268	}
9c7027ba BH	269
	270	nr = rtas_ld(args, 0);
	271
	272	if (!ics_valid_irq(ics, nr)) {
	273	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	274	return;
	275	}
	276
d4d7a59a	277	srcno = nr - ics->offset;
28976c99 DG	278	ics_write_xive(ics, srcno, ics->irqs[srcno].server,
	279	ics->irqs[srcno].saved_priority,
	280	ics->irqs[srcno].saved_priority);
9c7027ba BH	281
	282	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	283	}
	284
9db8c551	285	static void ics_spapr_realize(DeviceState dev, Error *errp)
9c7027ba	286	{
9db8c551 DG	287	ICSState *ics = ICS_SPAPR(dev);
	288	ICSStateClass *icsc = ICS_GET_CLASS(ics);
	289	Error *local_err = NULL;
	290
	291	icsc->parent_realize(dev, &local_err);
	292	if (local_err) {
	293	error_propagate(errp, local_err);
	294	return;
	295	}
	296
9c7027ba BH	297	spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
	298	spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
	299	spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
	300	spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
	301
	302	spapr_register_hypercall(H_CPPR, h_cppr);
	303	spapr_register_hypercall(H_IPI, h_ipi);
	304	spapr_register_hypercall(H_XIRR, h_xirr);
	305	spapr_register_hypercall(H_XIRR_X, h_xirr_x);
	306	spapr_register_hypercall(H_EOI, h_eoi);
	307	spapr_register_hypercall(H_IPOLL, h_ipoll);
9c7027ba BH	308	}
9c7027ba BH	309
05289273 DG	310	static void xics_spapr_dt(SpaprInterruptController *intc, uint32_t nr_servers,
05289273 DG	311	void *fdt, uint32_t phandle)
9b9a1908 DG	312	{
9b9a1908 DG	313	uint32_t interrupt_server_ranges_prop[] = {
b0ec3129	314	0, cpu_to_be32(nr_servers),
9b9a1908 DG	315	};
	316	int node;
	317
14789694	318	_FDT(node = fdt_add_subnode(fdt, 0, "interrupt-controller"));
9b9a1908 DG	319
	320	_FDT(fdt_setprop_string(fdt, node, "device_type",
	321	"PowerPC-External-Interrupt-Presentation"));
	322	_FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
	323	_FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
	324	_FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
	325	interrupt_server_ranges_prop,
	326	sizeof(interrupt_server_ranges_prop)));
	327	_FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
	328	_FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
	329	_FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
	330	}
9db8c551	331
ebd6be08 DG	332	static int xics_spapr_cpu_intc_create(SpaprInterruptController *intc,
	333	PowerPCCPU cpu, Error *errp)
	334	{
	335	ICSState *ics = ICS_SPAPR(intc);
	336	Object *obj;
	337	SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
	338
	339	obj = icp_create(OBJECT(cpu), TYPE_ICP, ics->xics, errp);
	340	if (!obj) {
	341	return -1;
	342	}
	343
	344	spapr_cpu->icp = ICP(obj);
	345	return 0;
	346	}
	347
d49e8a9b CLG	348	static void xics_spapr_cpu_intc_reset(SpaprInterruptController *intc,
	349	PowerPCCPU *cpu)
	350	{
	351	icp_reset(spapr_cpu_state(cpu)->icp);
	352	}
	353
0990ce6a GK	354	static void xics_spapr_cpu_intc_destroy(SpaprInterruptController *intc,
	355	PowerPCCPU *cpu)
	356	{
	357	SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
	358
	359	icp_destroy(spapr_cpu->icp);
	360	spapr_cpu->icp = NULL;
	361	}
	362
0b0e52b1 DG	363	static int xics_spapr_claim_irq(SpaprInterruptController *intc, int irq,
	364	bool lsi, Error **errp)
	365	{
	366	ICSState *ics = ICS_SPAPR(intc);
	367
	368	assert(ics);
	369	assert(ics_valid_irq(ics, irq));
	370
	371	if (!ics_irq_free(ics, irq - ics->offset)) {
	372	error_setg(errp, "IRQ %d is not free", irq);
	373	return -EBUSY;
	374	}
	375
	376	ics_set_irq_type(ics, irq - ics->offset, lsi);
	377	return 0;
	378	}
	379
	380	static void xics_spapr_free_irq(SpaprInterruptController *intc, int irq)
	381	{
	382	ICSState *ics = ICS_SPAPR(intc);
	383	uint32_t srcno = irq - ics->offset;
	384
	385	assert(ics_valid_irq(ics, irq));
	386
	387	memset(&ics->irqs[srcno], 0, sizeof(ICSIRQState));
	388	}
	389
7bcdbcca DG	390	static void xics_spapr_set_irq(SpaprInterruptController *intc, int irq, int val)
	391	{
	392	ICSState *ics = ICS_SPAPR(intc);
	393	uint32_t srcno = irq - ics->offset;
	394
	395	ics_set_irq(ics, srcno, val);
	396	}
	397
328d8eb2 DG	398	static void xics_spapr_print_info(SpaprInterruptController intc, Monitor mon)
	399	{
	400	ICSState *ics = ICS_SPAPR(intc);
	401	CPUState *cs;
	402
	403	CPU_FOREACH(cs) {
	404	PowerPCCPU *cpu = POWERPC_CPU(cs);
	405
	406	icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
	407	}
	408
	409	ics_pic_print_info(ics, mon);
	410	}
	411
605994e5 DG	412	static int xics_spapr_post_load(SpaprInterruptController *intc, int version_id)
	413	{
	414	if (!kvm_irqchip_in_kernel()) {
	415	CPUState *cs;
	416	CPU_FOREACH(cs) {
	417	PowerPCCPU *cpu = POWERPC_CPU(cs);
	418	icp_resend(spapr_cpu_state(cpu)->icp);
	419	}
	420	}
	421	return 0;
	422	}
	423
4ffb7496 GK	424	static int xics_spapr_activate(SpaprInterruptController *intc,
4ffb7496 GK	425	uint32_t nr_servers, Error **errp)
567192d4 DG	426	{
567192d4 DG	427	if (kvm_enabled()) {
4ffb7496	428	return spapr_irq_init_kvm(xics_kvm_connect, intc, nr_servers, errp);
567192d4 DG	429	}
	430	return 0;
	431	}
	432
	433	static void xics_spapr_deactivate(SpaprInterruptController *intc)
	434	{
	435	if (kvm_irqchip_in_kernel()) {
	436	xics_kvm_disconnect(intc);
	437	}
	438	}
	439
9db8c551 DG	440	static void ics_spapr_class_init(ObjectClass klass, void data)
	441	{
	442	DeviceClass *dc = DEVICE_CLASS(klass);
	443	ICSStateClass *isc = ICS_CLASS(klass);
ebd6be08	444	SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass);
9db8c551 DG	445
	446	device_class_set_parent_realize(dc, ics_spapr_realize,
	447	&isc->parent_realize);
567192d4 DG	448	sicc->activate = xics_spapr_activate;
567192d4 DG	449	sicc->deactivate = xics_spapr_deactivate;
ebd6be08	450	sicc->cpu_intc_create = xics_spapr_cpu_intc_create;
d49e8a9b	451	sicc->cpu_intc_reset = xics_spapr_cpu_intc_reset;
0990ce6a	452	sicc->cpu_intc_destroy = xics_spapr_cpu_intc_destroy;
0b0e52b1 DG	453	sicc->claim_irq = xics_spapr_claim_irq;
0b0e52b1 DG	454	sicc->free_irq = xics_spapr_free_irq;
7bcdbcca	455	sicc->set_irq = xics_spapr_set_irq;
328d8eb2	456	sicc->print_info = xics_spapr_print_info;
05289273	457	sicc->dt = xics_spapr_dt;
605994e5	458	sicc->post_load = xics_spapr_post_load;
9db8c551 DG	459	}
	460
	461	static const TypeInfo ics_spapr_info = {
	462	.name = TYPE_ICS_SPAPR,
	463	.parent = TYPE_ICS,
	464	.class_init = ics_spapr_class_init,
150e25f8 DG	465	.interfaces = (InterfaceInfo[]) {
	466	{ TYPE_SPAPR_INTC },
	467	{ }
	468	},
9db8c551 DG	469	};
	470
	471	static void xics_spapr_register_types(void)
	472	{
	473	type_register_static(&ics_spapr_info);
	474	}
	475
	476	type_init(xics_spapr_register_types)