[mirror_qemu.git] / hw / microblaze / xlnx-zynqmp-pmu.c

/*
 * Xilinx Zynq MPSoC PMU (Power Management Unit) emulation
 *
 * Copyright (C) 2017 Xilinx Inc
 * Written by Alistair Francis <alistair.francis@xilinx.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "cpu.h"
#include "boot.h"

#include "hw/intc/xlnx-zynqmp-ipi.h"
#include "hw/intc/xlnx-pmu-iomod-intc.h"

/* Define the PMU device */

#define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc"
#define XLNX_ZYNQMP_PMU_SOC(obj) OBJECT_CHECK(XlnxZynqMPPMUSoCState, (obj), \
                                              TYPE_XLNX_ZYNQMP_PMU_SOC)

#define XLNX_ZYNQMP_PMU_ROM_SIZE    0x8000
#define XLNX_ZYNQMP_PMU_ROM_ADDR    0xFFD00000
#define XLNX_ZYNQMP_PMU_RAM_ADDR    0xFFDC0000

#define XLNX_ZYNQMP_PMU_INTC_ADDR   0xFFD40000

#define XLNX_ZYNQMP_PMU_NUM_IPIS    4

static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
    0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
};
static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
    19, 20, 21, 22,
};

typedef struct XlnxZynqMPPMUSoCState {
    /*< private >*/
    DeviceState parent_obj;

    /*< public >*/
    MicroBlazeCPU cpu;
    XlnxPMUIOIntc intc;
    XlnxZynqMPIPI ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
}  XlnxZynqMPPMUSoCState;


static void xlnx_zynqmp_pmu_soc_init(Object *obj)
{
    XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);

    object_initialize_child(obj, "pmu-cpu", &s->cpu, TYPE_MICROBLAZE_CPU);

    object_initialize_child(obj, "intc", &s->intc, TYPE_XLNX_PMU_IO_INTC);

    /* Create the IPI device */
    for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
        char *name = g_strdup_printf("ipi%d", i);
        object_initialize_child(obj, name, &s->ipi[i], TYPE_XLNX_ZYNQMP_IPI);
        g_free(name);
    }
}

static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
{
    XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(dev);

    object_property_set_uint(OBJECT(&s->cpu), "base-vectors",
                             XLNX_ZYNQMP_PMU_ROM_ADDR, &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), "use-stack-protection", true,
                             &error_abort);
    object_property_set_uint(OBJECT(&s->cpu), "use-fpu", 0, &error_abort);
    object_property_set_uint(OBJECT(&s->cpu), "use-hw-mul", 0, &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), "use-barrel", true,
                             &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), "use-msr-instr", true,
                             &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), "use-pcmp-instr", true,
                             &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), "use-mmu", false, &error_abort);
    object_property_set_bool(OBJECT(&s->cpu), "endianness", true,
                             &error_abort);
    object_property_set_str(OBJECT(&s->cpu), "version", "8.40.b",
                            &error_abort);
    object_property_set_uint(OBJECT(&s->cpu), "pvr", 0, &error_abort);
    if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
        return;
    }

    object_property_set_uint(OBJECT(&s->intc), "intc-intr-size", 0x10,
                             &error_abort);
    object_property_set_uint(OBJECT(&s->intc), "intc-level-edge", 0x0,
                             &error_abort);
    object_property_set_uint(OBJECT(&s->intc), "intc-positive", 0xffff,
                             &error_abort);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) {
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));

    /* Connect the IPI device */
    for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
        sysbus_realize(SYS_BUS_DEVICE(&s->ipi[i]), &error_abort);
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->intc), ipi_irq[i]));
    }
}

static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = xlnx_zynqmp_pmu_soc_realize;
}

static const TypeInfo xlnx_zynqmp_pmu_soc_type_info = {
    .name = TYPE_XLNX_ZYNQMP_PMU_SOC,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(XlnxZynqMPPMUSoCState),
    .instance_init = xlnx_zynqmp_pmu_soc_init,
    .class_init = xlnx_zynqmp_pmu_soc_class_init,
};

static void xlnx_zynqmp_pmu_soc_register_types(void)
{
    type_register_static(&xlnx_zynqmp_pmu_soc_type_info);
}

type_init(xlnx_zynqmp_pmu_soc_register_types)

/* Define the PMU Machine */

static void xlnx_zynqmp_pmu_init(MachineState *machine)
{
    XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
    MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);

    /* Create the ROM */
    memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
                           XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
                                pmu_rom);

    /* Create the RAM */
    memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",
                           machine->ram_size, &error_fatal);
    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
                                pmu_ram);

    /* Create the PMU device */
    object_initialize_child(OBJECT(machine), "pmu", pmu,
                            TYPE_XLNX_ZYNQMP_PMU_SOC);
    qdev_realize(DEVICE(pmu), NULL, &error_fatal);

    /* Load the kernel */
    microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
                           machine->ram_size,
                           machine->initrd_filename,
                           machine->dtb,
                           NULL);
}

static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
{
    mc->desc = "Xilinx ZynqMP PMU machine";
    mc->init = xlnx_zynqmp_pmu_init;
}

DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
Commit	Line	Data
4690bf4e AF	1	/*
	2	* Xilinx Zynq MPSoC PMU (Power Management Unit) emulation
	3	*
	4	* Copyright (C) 2017 Xilinx Inc
	5	* Written by Alistair Francis <alistair.francis@xilinx.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*/
	17
	18	#include "qemu/osdep.h"
	19	#include "qapi/error.h"
133d23b3	20	#include "exec/address-spaces.h"
4690bf4e AF	21	#include "hw/boards.h"
4690bf4e AF	22	#include "cpu.h"
133d23b3	23	#include "boot.h"
4690bf4e	24
07b30201	25	#include "hw/intc/xlnx-zynqmp-ipi.h"
633a91b6 AF	26	#include "hw/intc/xlnx-pmu-iomod-intc.h"
633a91b6 AF	27
4690bf4e AF	28	/* Define the PMU device */
	29
	30	#define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc"
	31	#define XLNX_ZYNQMP_PMU_SOC(obj) OBJECT_CHECK(XlnxZynqMPPMUSoCState, (obj), \
	32	TYPE_XLNX_ZYNQMP_PMU_SOC)
	33
133d23b3 AF	34	#define XLNX_ZYNQMP_PMU_ROM_SIZE 0x8000
	35	#define XLNX_ZYNQMP_PMU_ROM_ADDR 0xFFD00000
	36	#define XLNX_ZYNQMP_PMU_RAM_ADDR 0xFFDC0000
	37
633a91b6 AF	38	#define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000
633a91b6 AF	39
07b30201 AF	40	#define XLNX_ZYNQMP_PMU_NUM_IPIS 4
	41
	42	static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
	43	0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
	44	};
	45	static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
	46	19, 20, 21, 22,
	47	};
	48
4690bf4e AF	49	typedef struct XlnxZynqMPPMUSoCState {
	50	/< private >/
	51	DeviceState parent_obj;
	52
	53	/< public >/
133d23b3	54	MicroBlazeCPU cpu;
633a91b6	55	XlnxPMUIOIntc intc;
a8ae92e0	56	XlnxZynqMPIPI ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
4690bf4e AF	57	} XlnxZynqMPPMUSoCState;
4690bf4e AF	58
633a91b6	59
4690bf4e AF	60	static void xlnx_zynqmp_pmu_soc_init(Object *obj)
4690bf4e AF	61	{
133d23b3	62	XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);
4690bf4e	63
9fc7fc4d	64	object_initialize_child(obj, "pmu-cpu", &s->cpu, TYPE_MICROBLAZE_CPU);
633a91b6	65
db873cc5	66	object_initialize_child(obj, "intc", &s->intc, TYPE_XLNX_PMU_IO_INTC);
da4aeff9 PMD	67
	68	/* Create the IPI device */
	69	for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
ff5d4dc9	70	char *name = g_strdup_printf("ipi%d", i);
db873cc5	71	object_initialize_child(obj, name, &s->ipi[i], TYPE_XLNX_ZYNQMP_IPI);
ff5d4dc9	72	g_free(name);
da4aeff9	73	}
4690bf4e AF	74	}
	75
	76	static void xlnx_zynqmp_pmu_soc_realize(DeviceState dev, Error *errp)
	77	{
133d23b3	78	XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(dev);
133d23b3	79
5325cc34 MA	80	object_property_set_uint(OBJECT(&s->cpu), "base-vectors",
	81	XLNX_ZYNQMP_PMU_ROM_ADDR, &error_abort);
	82	object_property_set_bool(OBJECT(&s->cpu), "use-stack-protection", true,
133d23b3	83	&error_abort);
5325cc34 MA	84	object_property_set_uint(OBJECT(&s->cpu), "use-fpu", 0, &error_abort);
	85	object_property_set_uint(OBJECT(&s->cpu), "use-hw-mul", 0, &error_abort);
	86	object_property_set_bool(OBJECT(&s->cpu), "use-barrel", true,
133d23b3	87	&error_abort);
5325cc34	88	object_property_set_bool(OBJECT(&s->cpu), "use-msr-instr", true,
133d23b3	89	&error_abort);
5325cc34	90	object_property_set_bool(OBJECT(&s->cpu), "use-pcmp-instr", true,
133d23b3	91	&error_abort);
5325cc34 MA	92	object_property_set_bool(OBJECT(&s->cpu), "use-mmu", false, &error_abort);
5325cc34 MA	93	object_property_set_bool(OBJECT(&s->cpu), "endianness", true,
133d23b3	94	&error_abort);
5325cc34	95	object_property_set_str(OBJECT(&s->cpu), "version", "8.40.b",
133d23b3	96	&error_abort);
5325cc34	97	object_property_set_uint(OBJECT(&s->cpu), "pvr", 0, &error_abort);
668f62ec	98	if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
133d23b3 AF	99	return;
133d23b3 AF	100	}
633a91b6	101
5325cc34	102	object_property_set_uint(OBJECT(&s->intc), "intc-intr-size", 0x10,
633a91b6	103	&error_abort);
5325cc34	104	object_property_set_uint(OBJECT(&s->intc), "intc-level-edge", 0x0,
633a91b6	105	&error_abort);
5325cc34	106	object_property_set_uint(OBJECT(&s->intc), "intc-positive", 0xffff,
633a91b6	107	&error_abort);
668f62ec	108	if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) {
633a91b6 AF	109	return;
	110	}
	111	sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
	112	sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
	113	qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
da4aeff9 PMD	114
	115	/* Connect the IPI device */
	116	for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
db873cc5	117	sysbus_realize(SYS_BUS_DEVICE(&s->ipi[i]), &error_abort);
da4aeff9 PMD	118	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]);
	119	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi[i]), 0,
	120	qdev_get_gpio_in(DEVICE(&s->intc), ipi_irq[i]));
	121	}
4690bf4e AF	122	}
	123
	124	static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass oc, void data)
	125	{
	126	DeviceClass *dc = DEVICE_CLASS(oc);
	127
	128	dc->realize = xlnx_zynqmp_pmu_soc_realize;
	129	}
	130
	131	static const TypeInfo xlnx_zynqmp_pmu_soc_type_info = {
	132	.name = TYPE_XLNX_ZYNQMP_PMU_SOC,
	133	.parent = TYPE_DEVICE,
	134	.instance_size = sizeof(XlnxZynqMPPMUSoCState),
	135	.instance_init = xlnx_zynqmp_pmu_soc_init,
	136	.class_init = xlnx_zynqmp_pmu_soc_class_init,
	137	};
	138
	139	static void xlnx_zynqmp_pmu_soc_register_types(void)
	140	{
	141	type_register_static(&xlnx_zynqmp_pmu_soc_type_info);
	142	}
	143
	144	type_init(xlnx_zynqmp_pmu_soc_register_types)
	145
	146	/* Define the PMU Machine */
	147
	148	static void xlnx_zynqmp_pmu_init(MachineState *machine)
	149	{
133d23b3 AF	150	XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);
	151	MemoryRegion *address_space_mem = get_system_memory();
	152	MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
	153	MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
	154
	155	/* Create the ROM */
	156	memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
	157	XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
	158	memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
	159	pmu_rom);
	160
	161	/* Create the RAM */
	162	memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",
	163	machine->ram_size, &error_fatal);
	164	memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
	165	pmu_ram);
	166
	167	/* Create the PMU device */
9fc7fc4d MA	168	object_initialize_child(OBJECT(machine), "pmu", pmu,
9fc7fc4d MA	169	TYPE_XLNX_ZYNQMP_PMU_SOC);
ce189ab2	170	qdev_realize(DEVICE(pmu), NULL, &error_fatal);
133d23b3 AF	171
	172	/* Load the kernel */
	173	microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
	174	machine->ram_size,
	175	machine->initrd_filename,
	176	machine->dtb,
	177	NULL);
4690bf4e AF	178	}
	179
	180	static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
	181	{
	182	mc->desc = "Xilinx ZynqMP PMU machine";
	183	mc->init = xlnx_zynqmp_pmu_init;
	184	}
	185
	186	DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
	187