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df1d8a1f PB |
1 | /* |
2 | * MIPS Boston development board emulation. | |
3 | * | |
4 | * Copyright (c) 2016 Imagination Technologies | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
fc6b3cf9 | 21 | #include "qemu/units.h" |
df1d8a1f PB |
22 | |
23 | #include "exec/address-spaces.h" | |
24 | #include "hw/boards.h" | |
25 | #include "hw/char/serial.h" | |
26 | #include "hw/hw.h" | |
27 | #include "hw/ide/pci.h" | |
28 | #include "hw/ide/ahci.h" | |
29 | #include "hw/loader.h" | |
30 | #include "hw/loader-fit.h" | |
31 | #include "hw/mips/cps.h" | |
32 | #include "hw/mips/cpudevs.h" | |
33 | #include "hw/pci-host/xilinx-pcie.h" | |
34 | #include "qapi/error.h" | |
df1d8a1f PB |
35 | #include "qemu/error-report.h" |
36 | #include "qemu/log.h" | |
8228e353 | 37 | #include "chardev/char.h" |
df1d8a1f PB |
38 | #include "sysemu/device_tree.h" |
39 | #include "sysemu/sysemu.h" | |
40 | #include "sysemu/qtest.h" | |
41 | ||
42 | #include <libfdt.h> | |
43 | ||
44 | #define TYPE_MIPS_BOSTON "mips-boston" | |
45 | #define BOSTON(obj) OBJECT_CHECK(BostonState, (obj), TYPE_MIPS_BOSTON) | |
46 | ||
47 | typedef struct { | |
48 | SysBusDevice parent_obj; | |
49 | ||
50 | MachineState *mach; | |
2d5fac80 | 51 | MIPSCPSState cps; |
df1d8a1f PB |
52 | SerialState *uart; |
53 | ||
54 | CharBackend lcd_display; | |
55 | char lcd_content[8]; | |
56 | bool lcd_inited; | |
57 | ||
58 | hwaddr kernel_entry; | |
59 | hwaddr fdt_base; | |
60 | } BostonState; | |
61 | ||
62 | enum boston_plat_reg { | |
63 | PLAT_FPGA_BUILD = 0x00, | |
64 | PLAT_CORE_CL = 0x04, | |
65 | PLAT_WRAPPER_CL = 0x08, | |
66 | PLAT_SYSCLK_STATUS = 0x0c, | |
67 | PLAT_SOFTRST_CTL = 0x10, | |
68 | #define PLAT_SOFTRST_CTL_SYSRESET (1 << 4) | |
69 | PLAT_DDR3_STATUS = 0x14, | |
70 | #define PLAT_DDR3_STATUS_LOCKED (1 << 0) | |
71 | #define PLAT_DDR3_STATUS_CALIBRATED (1 << 2) | |
72 | PLAT_PCIE_STATUS = 0x18, | |
73 | #define PLAT_PCIE_STATUS_PCIE0_LOCKED (1 << 0) | |
74 | #define PLAT_PCIE_STATUS_PCIE1_LOCKED (1 << 8) | |
75 | #define PLAT_PCIE_STATUS_PCIE2_LOCKED (1 << 16) | |
76 | PLAT_FLASH_CTL = 0x1c, | |
77 | PLAT_SPARE0 = 0x20, | |
78 | PLAT_SPARE1 = 0x24, | |
79 | PLAT_SPARE2 = 0x28, | |
80 | PLAT_SPARE3 = 0x2c, | |
81 | PLAT_MMCM_DIV = 0x30, | |
82 | #define PLAT_MMCM_DIV_CLK0DIV_SHIFT 0 | |
83 | #define PLAT_MMCM_DIV_INPUT_SHIFT 8 | |
84 | #define PLAT_MMCM_DIV_MUL_SHIFT 16 | |
85 | #define PLAT_MMCM_DIV_CLK1DIV_SHIFT 24 | |
86 | PLAT_BUILD_CFG = 0x34, | |
87 | #define PLAT_BUILD_CFG_IOCU_EN (1 << 0) | |
88 | #define PLAT_BUILD_CFG_PCIE0_EN (1 << 1) | |
89 | #define PLAT_BUILD_CFG_PCIE1_EN (1 << 2) | |
90 | #define PLAT_BUILD_CFG_PCIE2_EN (1 << 3) | |
91 | PLAT_DDR_CFG = 0x38, | |
92 | #define PLAT_DDR_CFG_SIZE (0xf << 0) | |
93 | #define PLAT_DDR_CFG_MHZ (0xfff << 4) | |
94 | PLAT_NOC_PCIE0_ADDR = 0x3c, | |
95 | PLAT_NOC_PCIE1_ADDR = 0x40, | |
96 | PLAT_NOC_PCIE2_ADDR = 0x44, | |
97 | PLAT_SYS_CTL = 0x48, | |
98 | }; | |
99 | ||
100 | static void boston_lcd_event(void *opaque, int event) | |
101 | { | |
102 | BostonState *s = opaque; | |
103 | if (event == CHR_EVENT_OPENED && !s->lcd_inited) { | |
104 | qemu_chr_fe_printf(&s->lcd_display, " "); | |
105 | s->lcd_inited = true; | |
106 | } | |
107 | } | |
108 | ||
109 | static uint64_t boston_lcd_read(void *opaque, hwaddr addr, | |
110 | unsigned size) | |
111 | { | |
112 | BostonState *s = opaque; | |
113 | uint64_t val = 0; | |
114 | ||
115 | switch (size) { | |
116 | case 8: | |
117 | val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56; | |
118 | val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48; | |
119 | val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40; | |
120 | val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32; | |
121 | /* fall through */ | |
122 | case 4: | |
123 | val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24; | |
124 | val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16; | |
125 | /* fall through */ | |
126 | case 2: | |
127 | val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8; | |
128 | /* fall through */ | |
129 | case 1: | |
130 | val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7]; | |
131 | break; | |
132 | } | |
133 | ||
134 | return val; | |
135 | } | |
136 | ||
137 | static void boston_lcd_write(void *opaque, hwaddr addr, | |
138 | uint64_t val, unsigned size) | |
139 | { | |
140 | BostonState *s = opaque; | |
141 | ||
142 | switch (size) { | |
143 | case 8: | |
144 | s->lcd_content[(addr + 7) & 0x7] = val >> 56; | |
145 | s->lcd_content[(addr + 6) & 0x7] = val >> 48; | |
146 | s->lcd_content[(addr + 5) & 0x7] = val >> 40; | |
147 | s->lcd_content[(addr + 4) & 0x7] = val >> 32; | |
148 | /* fall through */ | |
149 | case 4: | |
150 | s->lcd_content[(addr + 3) & 0x7] = val >> 24; | |
151 | s->lcd_content[(addr + 2) & 0x7] = val >> 16; | |
152 | /* fall through */ | |
153 | case 2: | |
154 | s->lcd_content[(addr + 1) & 0x7] = val >> 8; | |
155 | /* fall through */ | |
156 | case 1: | |
157 | s->lcd_content[(addr + 0) & 0x7] = val; | |
158 | break; | |
159 | } | |
160 | ||
161 | qemu_chr_fe_printf(&s->lcd_display, | |
162 | "\r%-8.8s", s->lcd_content); | |
163 | } | |
164 | ||
165 | static const MemoryRegionOps boston_lcd_ops = { | |
166 | .read = boston_lcd_read, | |
167 | .write = boston_lcd_write, | |
168 | .endianness = DEVICE_NATIVE_ENDIAN, | |
169 | }; | |
170 | ||
171 | static uint64_t boston_platreg_read(void *opaque, hwaddr addr, | |
172 | unsigned size) | |
173 | { | |
174 | BostonState *s = opaque; | |
175 | uint32_t gic_freq, val; | |
176 | ||
177 | if (size != 4) { | |
c4c98835 | 178 | qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size); |
df1d8a1f PB |
179 | return 0; |
180 | } | |
181 | ||
182 | switch (addr & 0xffff) { | |
183 | case PLAT_FPGA_BUILD: | |
184 | case PLAT_CORE_CL: | |
185 | case PLAT_WRAPPER_CL: | |
186 | return 0; | |
187 | case PLAT_DDR3_STATUS: | |
188 | return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED; | |
189 | case PLAT_MMCM_DIV: | |
2d5fac80 | 190 | gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000; |
df1d8a1f PB |
191 | val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT; |
192 | val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT; | |
193 | val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT; | |
194 | val |= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT; | |
195 | return val; | |
196 | case PLAT_BUILD_CFG: | |
197 | val = PLAT_BUILD_CFG_PCIE0_EN; | |
198 | val |= PLAT_BUILD_CFG_PCIE1_EN; | |
199 | val |= PLAT_BUILD_CFG_PCIE2_EN; | |
200 | return val; | |
201 | case PLAT_DDR_CFG: | |
d23b6caa | 202 | val = s->mach->ram_size / GiB; |
df1d8a1f PB |
203 | assert(!(val & ~PLAT_DDR_CFG_SIZE)); |
204 | val |= PLAT_DDR_CFG_MHZ; | |
205 | return val; | |
206 | default: | |
c4c98835 | 207 | qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n", |
df1d8a1f PB |
208 | addr & 0xffff); |
209 | return 0; | |
210 | } | |
211 | } | |
212 | ||
213 | static void boston_platreg_write(void *opaque, hwaddr addr, | |
214 | uint64_t val, unsigned size) | |
215 | { | |
216 | if (size != 4) { | |
c4c98835 | 217 | qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size); |
df1d8a1f PB |
218 | return; |
219 | } | |
220 | ||
221 | switch (addr & 0xffff) { | |
222 | case PLAT_FPGA_BUILD: | |
223 | case PLAT_CORE_CL: | |
224 | case PLAT_WRAPPER_CL: | |
225 | case PLAT_DDR3_STATUS: | |
226 | case PLAT_PCIE_STATUS: | |
227 | case PLAT_MMCM_DIV: | |
228 | case PLAT_BUILD_CFG: | |
229 | case PLAT_DDR_CFG: | |
230 | /* read only */ | |
231 | break; | |
232 | case PLAT_SOFTRST_CTL: | |
233 | if (val & PLAT_SOFTRST_CTL_SYSRESET) { | |
cf83f140 | 234 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
df1d8a1f PB |
235 | } |
236 | break; | |
237 | default: | |
238 | qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx | |
c4c98835 | 239 | " = 0x%" PRIx64 "\n", addr & 0xffff, val); |
df1d8a1f PB |
240 | break; |
241 | } | |
242 | } | |
243 | ||
244 | static const MemoryRegionOps boston_platreg_ops = { | |
245 | .read = boston_platreg_read, | |
246 | .write = boston_platreg_write, | |
247 | .endianness = DEVICE_NATIVE_ENDIAN, | |
248 | }; | |
249 | ||
df1d8a1f PB |
250 | static const TypeInfo boston_device = { |
251 | .name = TYPE_MIPS_BOSTON, | |
252 | .parent = TYPE_SYS_BUS_DEVICE, | |
253 | .instance_size = sizeof(BostonState), | |
254 | }; | |
255 | ||
256 | static void boston_register_types(void) | |
257 | { | |
258 | type_register_static(&boston_device); | |
259 | } | |
260 | type_init(boston_register_types) | |
261 | ||
262 | static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr, | |
263 | bool is_64b) | |
264 | { | |
265 | const uint32_t cm_base = 0x16100000; | |
266 | const uint32_t gic_base = 0x16120000; | |
267 | const uint32_t cpc_base = 0x16200000; | |
268 | ||
269 | /* Move CM GCRs */ | |
270 | if (is_64b) { | |
271 | stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */ | |
272 | stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */ | |
273 | } else { | |
274 | stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */ | |
275 | stl_p(p++, 0x00084100); /* sll $8, $8, 4 */ | |
276 | } | |
277 | stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */ | |
278 | stl_p(p++, 0x01094025); /* or $8, $9 */ | |
279 | stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */ | |
280 | if (is_64b) { | |
281 | stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */ | |
282 | } else { | |
283 | stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */ | |
284 | } | |
285 | stl_p(p++, 0x012a4025); /* or $8, $10 */ | |
286 | ||
287 | /* Move & enable GIC GCRs */ | |
288 | stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */ | |
289 | stl_p(p++, 0x35290001); /* ori $9, 0x1 */ | |
290 | if (is_64b) { | |
291 | stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */ | |
292 | } else { | |
293 | stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */ | |
294 | } | |
295 | ||
296 | /* Move & enable CPC GCRs */ | |
297 | stl_p(p++, 0x3c090000 | (cpc_base >> 16)); /* lui $9, cpc_base >> 16 */ | |
298 | stl_p(p++, 0x35290001); /* ori $9, 0x1 */ | |
299 | if (is_64b) { | |
300 | stl_p(p++, 0xfd090088); /* sd $9, 0x88($8) */ | |
301 | } else { | |
302 | stl_p(p++, 0xad090088); /* sw $9, 0x88($8) */ | |
303 | } | |
304 | ||
305 | /* | |
306 | * Setup argument registers to follow the UHI boot protocol: | |
307 | * | |
308 | * a0/$4 = -2 | |
309 | * a1/$5 = virtual address of FDT | |
310 | * a2/$6 = 0 | |
311 | * a3/$7 = 0 | |
312 | */ | |
313 | stl_p(p++, 0x2404fffe); /* li $4, -2 */ | |
314 | /* lui $5, hi(fdt_addr) */ | |
315 | stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff)); | |
316 | if (fdt_addr & 0xffff) { /* ori $5, lo(fdt_addr) */ | |
317 | stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff)); | |
318 | } | |
319 | stl_p(p++, 0x34060000); /* li $6, 0 */ | |
320 | stl_p(p++, 0x34070000); /* li $7, 0 */ | |
321 | ||
322 | /* Load kernel entry address & jump to it */ | |
323 | /* lui $25, hi(kernel_entry) */ | |
324 | stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff)); | |
325 | /* ori $25, lo(kernel_entry) */ | |
326 | stl_p(p++, 0x37390000 | (kernel_entry & 0xffff)); | |
327 | stl_p(p++, 0x03200009); /* jr $25 */ | |
328 | } | |
329 | ||
330 | static const void *boston_fdt_filter(void *opaque, const void *fdt_orig, | |
331 | const void *match_data, hwaddr *load_addr) | |
332 | { | |
333 | BostonState *s = BOSTON(opaque); | |
334 | MachineState *machine = s->mach; | |
335 | const char *cmdline; | |
336 | int err; | |
337 | void *fdt; | |
338 | size_t fdt_sz, ram_low_sz, ram_high_sz; | |
339 | ||
340 | fdt_sz = fdt_totalsize(fdt_orig) * 2; | |
341 | fdt = g_malloc0(fdt_sz); | |
342 | ||
343 | err = fdt_open_into(fdt_orig, fdt, fdt_sz); | |
344 | if (err) { | |
345 | fprintf(stderr, "unable to open FDT\n"); | |
346 | return NULL; | |
347 | } | |
348 | ||
349 | cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0]) | |
350 | ? machine->kernel_cmdline : " "; | |
351 | err = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | |
352 | if (err < 0) { | |
353 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
354 | return NULL; | |
355 | } | |
356 | ||
d23b6caa | 357 | ram_low_sz = MIN(256 * MiB, machine->ram_size); |
df1d8a1f PB |
358 | ram_high_sz = machine->ram_size - ram_low_sz; |
359 | qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg", | |
360 | 1, 0x00000000, 1, ram_low_sz, | |
361 | 1, 0x90000000, 1, ram_high_sz); | |
362 | ||
363 | fdt = g_realloc(fdt, fdt_totalsize(fdt)); | |
364 | qemu_fdt_dumpdtb(fdt, fdt_sz); | |
365 | ||
366 | s->fdt_base = *load_addr; | |
367 | ||
368 | return fdt; | |
369 | } | |
370 | ||
371 | static const void *boston_kernel_filter(void *opaque, const void *kernel, | |
372 | hwaddr *load_addr, hwaddr *entry_addr) | |
373 | { | |
374 | BostonState *s = BOSTON(opaque); | |
375 | ||
376 | s->kernel_entry = *entry_addr; | |
377 | ||
378 | return kernel; | |
379 | } | |
380 | ||
381 | static const struct fit_loader_match boston_matches[] = { | |
382 | { "img,boston" }, | |
383 | { NULL }, | |
384 | }; | |
385 | ||
386 | static const struct fit_loader boston_fit_loader = { | |
387 | .matches = boston_matches, | |
388 | .addr_to_phys = cpu_mips_kseg0_to_phys, | |
389 | .fdt_filter = boston_fdt_filter, | |
390 | .kernel_filter = boston_kernel_filter, | |
391 | }; | |
392 | ||
393 | static inline XilinxPCIEHost * | |
394 | xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, | |
395 | hwaddr cfg_base, uint64_t cfg_size, | |
396 | hwaddr mmio_base, uint64_t mmio_size, | |
397 | qemu_irq irq, bool link_up) | |
398 | { | |
399 | DeviceState *dev; | |
400 | MemoryRegion *cfg, *mmio; | |
401 | ||
402 | dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST); | |
403 | ||
404 | qdev_prop_set_uint32(dev, "bus_nr", bus_nr); | |
405 | qdev_prop_set_uint64(dev, "cfg_base", cfg_base); | |
406 | qdev_prop_set_uint64(dev, "cfg_size", cfg_size); | |
407 | qdev_prop_set_uint64(dev, "mmio_base", mmio_base); | |
408 | qdev_prop_set_uint64(dev, "mmio_size", mmio_size); | |
409 | qdev_prop_set_bit(dev, "link_up", link_up); | |
410 | ||
411 | qdev_init_nofail(dev); | |
412 | ||
413 | cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
414 | memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); | |
415 | ||
416 | mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
417 | memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0); | |
418 | ||
419 | qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq); | |
420 | ||
421 | return XILINX_PCIE_HOST(dev); | |
422 | } | |
423 | ||
424 | static void boston_mach_init(MachineState *machine) | |
425 | { | |
426 | DeviceState *dev; | |
427 | BostonState *s; | |
428 | Error *err = NULL; | |
df1d8a1f PB |
429 | MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg; |
430 | MemoryRegion *sys_mem = get_system_memory(); | |
431 | XilinxPCIEHost *pcie2; | |
432 | PCIDevice *ahci; | |
433 | DriveInfo *hd[6]; | |
434 | Chardev *chr; | |
435 | int fw_size, fit_err; | |
436 | bool is_64b; | |
437 | ||
d23b6caa PMD |
438 | if ((machine->ram_size % GiB) || |
439 | (machine->ram_size > (2 * GiB))) { | |
df1d8a1f PB |
440 | error_report("Memory size must be 1GB or 2GB"); |
441 | exit(1); | |
442 | } | |
443 | ||
df1d8a1f PB |
444 | dev = qdev_create(NULL, TYPE_MIPS_BOSTON); |
445 | qdev_init_nofail(dev); | |
446 | ||
447 | s = BOSTON(dev); | |
448 | s->mach = machine; | |
df1d8a1f | 449 | |
a7519f2b | 450 | if (!cpu_supports_cps_smp(machine->cpu_type)) { |
df1d8a1f PB |
451 | error_report("Boston requires CPUs which support CPS"); |
452 | exit(1); | |
453 | } | |
454 | ||
a7519f2b | 455 | is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64); |
df1d8a1f | 456 | |
4626548b PMD |
457 | sysbus_init_child_obj(OBJECT(machine), "cps", OBJECT(&s->cps), |
458 | sizeof(s->cps), TYPE_MIPS_CPS); | |
2d5fac80 | 459 | object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type", |
a7519f2b | 460 | &err); |
33decbd2 | 461 | object_property_set_int(OBJECT(&s->cps), machine->smp.cpus, "num-vp", &err); |
2d5fac80 | 462 | object_property_set_bool(OBJECT(&s->cps), true, "realized", &err); |
df1d8a1f PB |
463 | |
464 | if (err != NULL) { | |
465 | error_report("%s", error_get_pretty(err)); | |
466 | exit(1); | |
467 | } | |
468 | ||
2d5fac80 | 469 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); |
df1d8a1f PB |
470 | |
471 | flash = g_new(MemoryRegion, 1); | |
d23b6caa | 472 | memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err); |
df1d8a1f PB |
473 | memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); |
474 | ||
475 | ddr = g_new(MemoryRegion, 1); | |
476 | memory_region_allocate_system_memory(ddr, NULL, "boston.ddr", | |
477 | machine->ram_size); | |
478 | memory_region_add_subregion_overlap(sys_mem, 0x80000000, ddr, 0); | |
479 | ||
480 | ddr_low_alias = g_new(MemoryRegion, 1); | |
481 | memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", | |
d23b6caa | 482 | ddr, 0, MIN(machine->ram_size, (256 * MiB))); |
df1d8a1f PB |
483 | memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); |
484 | ||
485 | xilinx_pcie_init(sys_mem, 0, | |
d23b6caa PMD |
486 | 0x10000000, 32 * MiB, |
487 | 0x40000000, 1 * GiB, | |
2d5fac80 | 488 | get_cps_irq(&s->cps, 2), false); |
df1d8a1f PB |
489 | |
490 | xilinx_pcie_init(sys_mem, 1, | |
d23b6caa PMD |
491 | 0x12000000, 32 * MiB, |
492 | 0x20000000, 512 * MiB, | |
2d5fac80 | 493 | get_cps_irq(&s->cps, 1), false); |
df1d8a1f PB |
494 | |
495 | pcie2 = xilinx_pcie_init(sys_mem, 2, | |
d23b6caa PMD |
496 | 0x14000000, 32 * MiB, |
497 | 0x16000000, 1 * MiB, | |
2d5fac80 | 498 | get_cps_irq(&s->cps, 0), true); |
df1d8a1f PB |
499 | |
500 | platreg = g_new(MemoryRegion, 1); | |
501 | memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, | |
502 | "boston-platregs", 0x1000); | |
503 | memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); | |
504 | ||
df1d8a1f | 505 | s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2, |
2d5fac80 | 506 | get_cps_irq(&s->cps, 3), 10000000, |
9bca0edb | 507 | serial_hd(0), DEVICE_NATIVE_ENDIAN); |
df1d8a1f PB |
508 | |
509 | lcd = g_new(MemoryRegion, 1); | |
510 | memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); | |
511 | memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0); | |
512 | ||
4ad6f6cb | 513 | chr = qemu_chr_new("lcd", "vc:320x240", NULL); |
df1d8a1f PB |
514 | qemu_chr_fe_init(&s->lcd_display, chr, NULL); |
515 | qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, | |
81517ba3 | 516 | boston_lcd_event, NULL, s, NULL, true); |
df1d8a1f PB |
517 | |
518 | ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, | |
519 | PCI_DEVFN(0, 0), | |
520 | true, TYPE_ICH9_AHCI); | |
bbe3179a JS |
521 | g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci)); |
522 | ide_drive_get(hd, ahci_get_num_ports(ahci)); | |
df1d8a1f PB |
523 | ahci_ide_create_devs(ahci, hd); |
524 | ||
525 | if (machine->firmware) { | |
526 | fw_size = load_image_targphys(machine->firmware, | |
d23b6caa | 527 | 0x1fc00000, 4 * MiB); |
df1d8a1f | 528 | if (fw_size == -1) { |
036a2604 | 529 | error_report("unable to load firmware image '%s'", |
df1d8a1f PB |
530 | machine->firmware); |
531 | exit(1); | |
532 | } | |
533 | } else if (machine->kernel_filename) { | |
534 | fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s); | |
535 | if (fit_err) { | |
036a2604 | 536 | error_report("unable to load FIT image"); |
df1d8a1f PB |
537 | exit(1); |
538 | } | |
539 | ||
540 | gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, | |
541 | s->kernel_entry, s->fdt_base, is_64b); | |
542 | } else if (!qtest_enabled()) { | |
036a2604 | 543 | error_report("Please provide either a -kernel or -bios argument"); |
df1d8a1f PB |
544 | exit(1); |
545 | } | |
546 | } | |
547 | ||
548 | static void boston_mach_class_init(MachineClass *mc) | |
549 | { | |
550 | mc->desc = "MIPS Boston"; | |
551 | mc->init = boston_mach_init; | |
552 | mc->block_default_type = IF_IDE; | |
d23b6caa | 553 | mc->default_ram_size = 1 * GiB; |
df1d8a1f | 554 | mc->max_cpus = 16; |
a7519f2b | 555 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400"); |
df1d8a1f PB |
556 | } |
557 | ||
558 | DEFINE_MACHINE("boston", boston_mach_class_init) |