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8e7e8a5b LA |
1 | /* |
2 | * Coherent Processing System emulation. | |
3 | * | |
4 | * Copyright (c) 2016 Imagination Technologies | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qapi/error.h" | |
0b8fa32f | 22 | #include "qemu/module.h" |
8e7e8a5b LA |
23 | #include "hw/mips/cps.h" |
24 | #include "hw/mips/mips.h" | |
a27bd6c7 | 25 | #include "hw/qdev-properties.h" |
8e7e8a5b | 26 | #include "hw/mips/cpudevs.h" |
40829435 | 27 | #include "sysemu/kvm.h" |
71e8a915 | 28 | #include "sysemu/reset.h" |
8e7e8a5b LA |
29 | |
30 | qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number) | |
31 | { | |
8e7e8a5b | 32 | assert(pin_number < s->num_irq); |
19494f81 | 33 | return s->gic.irq_state[pin_number].irq; |
8e7e8a5b LA |
34 | } |
35 | ||
36 | static void mips_cps_init(Object *obj) | |
37 | { | |
38 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
39 | MIPSCPSState *s = MIPS_CPS(obj); | |
40 | ||
f5c3fbfc AM |
41 | /* |
42 | * Cover entire address space as there do not seem to be any | |
43 | * constraints for the base address of CPC and GIC. | |
44 | */ | |
8e7e8a5b LA |
45 | memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX); |
46 | sysbus_init_mmio(sbd, &s->container); | |
47 | } | |
48 | ||
49 | static void main_cpu_reset(void *opaque) | |
50 | { | |
51 | MIPSCPU *cpu = opaque; | |
52 | CPUState *cs = CPU(cpu); | |
53 | ||
54 | cpu_reset(cs); | |
55 | ||
56 | /* All VPs are halted on reset. Leave powering up to CPC. */ | |
57 | cs->halted = 1; | |
58 | } | |
59 | ||
40829435 LA |
60 | static bool cpu_mips_itu_supported(CPUMIPSState *env) |
61 | { | |
62 | bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || | |
63 | (env->CP0_Config3 & (1 << CP0C3_MT)); | |
64 | ||
65 | return is_mt && !kvm_enabled(); | |
66 | } | |
67 | ||
8e7e8a5b LA |
68 | static void mips_cps_realize(DeviceState *dev, Error **errp) |
69 | { | |
70 | MIPSCPSState *s = MIPS_CPS(dev); | |
71 | CPUMIPSState *env; | |
72 | MIPSCPU *cpu; | |
73 | int i; | |
a9bd9b5a LA |
74 | Error *err = NULL; |
75 | target_ulong gcr_base; | |
40829435 | 76 | bool itu_present = false; |
043715d1 | 77 | bool saar_present = false; |
8e7e8a5b LA |
78 | |
79 | for (i = 0; i < s->num_vp; i++) { | |
a7519f2b | 80 | cpu = MIPS_CPU(cpu_create(s->cpu_type)); |
8e7e8a5b LA |
81 | |
82 | /* Init internal devices */ | |
5a975d43 PB |
83 | cpu_mips_irq_init_cpu(cpu); |
84 | cpu_mips_clock_init(cpu); | |
85 | ||
86 | env = &cpu->env; | |
40829435 LA |
87 | if (cpu_mips_itu_supported(env)) { |
88 | itu_present = true; | |
89 | /* Attach ITC Tag to the VP */ | |
90 | env->itc_tag = mips_itu_get_tag_region(&s->itu); | |
043715d1 | 91 | env->itu = &s->itu; |
40829435 | 92 | } |
8e7e8a5b LA |
93 | qemu_register_reset(main_cpu_reset, cpu); |
94 | } | |
a9bd9b5a LA |
95 | |
96 | cpu = MIPS_CPU(first_cpu); | |
97 | env = &cpu->env; | |
043715d1 | 98 | saar_present = (bool)env->saarp; |
a9bd9b5a | 99 | |
40829435 LA |
100 | /* Inter-Thread Communication Unit */ |
101 | if (itu_present) { | |
0074fce6 | 102 | object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); |
81f66cfd MA |
103 | object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", |
104 | &error_abort); | |
105 | object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", | |
106 | &error_abort); | |
043715d1 | 107 | object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present", |
81f66cfd | 108 | &error_abort); |
043715d1 | 109 | if (saar_present) { |
3cff8173 | 110 | s->itu.saar = &env->CP0_SAAR; |
043715d1 | 111 | } |
118bfd76 | 112 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), &err)) { |
40829435 LA |
113 | error_propagate(errp, err); |
114 | return; | |
115 | } | |
116 | ||
117 | memory_region_add_subregion(&s->container, 0, | |
118 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0)); | |
119 | } | |
120 | ||
2edd5261 | 121 | /* Cluster Power Controller */ |
0074fce6 | 122 | object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC); |
81f66cfd MA |
123 | object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", |
124 | &error_abort); | |
125 | object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", | |
126 | &error_abort); | |
118bfd76 | 127 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), &err)) { |
2edd5261 LA |
128 | error_propagate(errp, err); |
129 | return; | |
130 | } | |
131 | ||
132 | memory_region_add_subregion(&s->container, 0, | |
133 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); | |
134 | ||
19494f81 | 135 | /* Global Interrupt Controller */ |
0074fce6 | 136 | object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC); |
81f66cfd MA |
137 | object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", |
138 | &error_abort); | |
139 | object_property_set_int(OBJECT(&s->gic), 128, "num-irq", | |
140 | &error_abort); | |
118bfd76 | 141 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err)) { |
19494f81 LA |
142 | error_propagate(errp, err); |
143 | return; | |
144 | } | |
145 | ||
146 | memory_region_add_subregion(&s->container, 0, | |
147 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); | |
148 | ||
a9bd9b5a LA |
149 | /* Global Configuration Registers */ |
150 | gcr_base = env->CP0_CMGCRBase << 4; | |
151 | ||
0074fce6 | 152 | object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); |
81f66cfd MA |
153 | object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", |
154 | &error_abort); | |
155 | object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", | |
156 | &error_abort); | |
157 | object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", | |
158 | &error_abort); | |
2726dc51 MA |
159 | object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", |
160 | &error_abort); | |
161 | object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", | |
162 | &error_abort); | |
118bfd76 | 163 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), &err)) { |
a9bd9b5a LA |
164 | error_propagate(errp, err); |
165 | return; | |
166 | } | |
167 | ||
168 | memory_region_add_subregion(&s->container, gcr_base, | |
169 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); | |
8e7e8a5b LA |
170 | } |
171 | ||
172 | static Property mips_cps_properties[] = { | |
173 | DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), | |
19494f81 | 174 | DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), |
a7519f2b | 175 | DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type), |
8e7e8a5b LA |
176 | DEFINE_PROP_END_OF_LIST() |
177 | }; | |
178 | ||
179 | static void mips_cps_class_init(ObjectClass *klass, void *data) | |
180 | { | |
181 | DeviceClass *dc = DEVICE_CLASS(klass); | |
182 | ||
183 | dc->realize = mips_cps_realize; | |
4f67d30b | 184 | device_class_set_props(dc, mips_cps_properties); |
8e7e8a5b LA |
185 | } |
186 | ||
187 | static const TypeInfo mips_cps_info = { | |
188 | .name = TYPE_MIPS_CPS, | |
189 | .parent = TYPE_SYS_BUS_DEVICE, | |
190 | .instance_size = sizeof(MIPSCPSState), | |
191 | .instance_init = mips_cps_init, | |
192 | .class_init = mips_cps_class_init, | |
193 | }; | |
194 | ||
195 | static void mips_cps_register_types(void) | |
196 | { | |
197 | type_register_static(&mips_cps_info); | |
198 | } | |
199 | ||
200 | type_init(mips_cps_register_types) |