[mirror_qemu.git] / hw / openpic.h

#if !defined(__OPENPIC_H__)
#define __OPENPIC_H__

/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
enum {
    OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
    OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
    OPENPIC_OUTPUT_MCK,     /* Machine check event       */
    OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
    OPENPIC_OUTPUT_RESET,   /* Core reset event          */
    OPENPIC_OUTPUT_NB,
};

qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
                        qemu_irq **irqs, qemu_irq irq_out);
qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
                     int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
#endif /* __OPENPIC_H__ */
Commit	Line	Data
b7169916 AJ	1	#if !defined(__OPENPIC_H__)
	2	#define __OPENPIC_H__
	3
	4	/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
	5	enum {
	6	OPENPIC_OUTPUT_INT = 0, /* IRQ */
	7	OPENPIC_OUTPUT_CINT, /* critical IRQ */
	8	OPENPIC_OUTPUT_MCK, /* Machine check event */
	9	OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
	10	OPENPIC_OUTPUT_RESET, /* Core reset event */
	11	OPENPIC_OUTPUT_NB,
	12	};
	13
8a5faa1d	14	qemu_irq openpic_init (MemoryRegion *pmem, int nb_cpus,
b7169916	15	qemu_irq **irqs, qemu_irq irq_out);
a8170e5e	16	qemu_irq mpic_init (MemoryRegion address_space, hwaddr base,
71cf9e62	17	int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
b7169916	18	#endif /* __OPENPIC_H__ */