]>
Commit | Line | Data |
---|---|---|
d0f7453d HC |
1 | /* |
2 | * bonito north bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
6 | * | |
7 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
d0f7453d HC |
11 | */ |
12 | ||
13 | /* | |
14 | * fulong 2e mini pc has a bonito north bridge. | |
15 | */ | |
16 | ||
f3db354c FB |
17 | /* |
18 | * what is the meaning of devfn in qemu and IDSEL in bonito northbridge? | |
d0f7453d HC |
19 | * |
20 | * devfn pci_slot<<3 + funno | |
21 | * one pci bus can have 32 devices and each device can have 8 functions. | |
22 | * | |
23 | * In bonito north bridge, pci slot = IDSEL bit - 12. | |
24 | * For example, PCI_IDSEL_VIA686B = 17, | |
25 | * pci slot = 17-12=5 | |
26 | * | |
27 | * so | |
28 | * VT686B_FUN0's devfn = (5<<3)+0 | |
29 | * VT686B_FUN1's devfn = (5<<3)+1 | |
30 | * | |
31 | * qemu also uses pci address for north bridge to access pci config register. | |
32 | * bus_no [23:16] | |
33 | * dev_no [15:11] | |
34 | * fun_no [10:8] | |
35 | * reg_no [7:2] | |
36 | * | |
37 | * so function bonito_sbridge_pciaddr for the translation from | |
38 | * north bridge address to pci address. | |
39 | */ | |
40 | ||
97d5408f | 41 | #include "qemu/osdep.h" |
0151abe4 | 42 | #include "qemu/error-report.h" |
83c9f4ca | 43 | #include "hw/pci/pci.h" |
64552b6b | 44 | #include "hw/irq.h" |
0d09e41a | 45 | #include "hw/mips/mips.h" |
83c9f4ca | 46 | #include "hw/pci/pci_host.h" |
d6454270 | 47 | #include "migration/vmstate.h" |
71e8a915 | 48 | #include "sysemu/reset.h" |
54d31236 | 49 | #include "sysemu/runstate.h" |
022c62cb | 50 | #include "exec/address-spaces.h" |
d0f7453d | 51 | |
f3db354c | 52 | /* #define DEBUG_BONITO */ |
d0f7453d HC |
53 | |
54 | #ifdef DEBUG_BONITO | |
a89f364a | 55 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) |
d0f7453d HC |
56 | #else |
57 | #define DPRINTF(fmt, ...) | |
58 | #endif | |
59 | ||
60 | /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ | |
61 | #define BONITO_BOOT_BASE 0x1fc00000 | |
62 | #define BONITO_BOOT_SIZE 0x00100000 | |
f3db354c | 63 | #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1) |
d0f7453d HC |
64 | #define BONITO_FLASH_BASE 0x1c000000 |
65 | #define BONITO_FLASH_SIZE 0x03000000 | |
f3db354c | 66 | #define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1) |
d0f7453d HC |
67 | #define BONITO_SOCKET_BASE 0x1f800000 |
68 | #define BONITO_SOCKET_SIZE 0x00400000 | |
f3db354c | 69 | #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1) |
d0f7453d HC |
70 | #define BONITO_REG_BASE 0x1fe00000 |
71 | #define BONITO_REG_SIZE 0x00040000 | |
f3db354c | 72 | #define BONITO_REG_TOP (BONITO_REG_BASE + BONITO_REG_SIZE - 1) |
d0f7453d HC |
73 | #define BONITO_DEV_BASE 0x1ff00000 |
74 | #define BONITO_DEV_SIZE 0x00100000 | |
f3db354c | 75 | #define BONITO_DEV_TOP (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1) |
d0f7453d HC |
76 | #define BONITO_PCILO_BASE 0x10000000 |
77 | #define BONITO_PCILO_BASE_VA 0xb0000000 | |
78 | #define BONITO_PCILO_SIZE 0x0c000000 | |
f3db354c | 79 | #define BONITO_PCILO_TOP (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1) |
d0f7453d HC |
80 | #define BONITO_PCILO0_BASE 0x10000000 |
81 | #define BONITO_PCILO1_BASE 0x14000000 | |
82 | #define BONITO_PCILO2_BASE 0x18000000 | |
83 | #define BONITO_PCIHI_BASE 0x20000000 | |
84 | #define BONITO_PCIHI_SIZE 0x20000000 | |
f3db354c | 85 | #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1) |
d0f7453d HC |
86 | #define BONITO_PCIIO_BASE 0x1fd00000 |
87 | #define BONITO_PCIIO_BASE_VA 0xbfd00000 | |
88 | #define BONITO_PCIIO_SIZE 0x00010000 | |
f3db354c | 89 | #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1) |
d0f7453d HC |
90 | #define BONITO_PCICFG_BASE 0x1fe80000 |
91 | #define BONITO_PCICFG_SIZE 0x00080000 | |
f3db354c | 92 | #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1) |
d0f7453d HC |
93 | |
94 | ||
95 | #define BONITO_PCICONFIGBASE 0x00 | |
96 | #define BONITO_REGBASE 0x100 | |
97 | ||
f3db354c | 98 | #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE + BONITO_REG_BASE) |
d0f7453d HC |
99 | #define BONITO_PCICONFIG_SIZE (0x100) |
100 | ||
f3db354c | 101 | #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE + BONITO_REG_BASE) |
d0f7453d HC |
102 | #define BONITO_INTERNAL_REG_SIZE (0x70) |
103 | ||
104 | #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) | |
105 | #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) | |
106 | ||
107 | ||
108 | ||
109 | /* 1. Bonito h/w Configuration */ | |
110 | /* Power on register */ | |
111 | ||
112 | #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ | |
113 | #define BONITO_BONGENCFG_OFFSET 0x4 | |
f3db354c | 114 | #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */ |
d0f7453d HC |
115 | |
116 | /* 2. IO & IDE configuration */ | |
117 | #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ | |
118 | ||
119 | /* 3. IO & IDE configuration */ | |
120 | #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ | |
121 | ||
122 | /* 4. PCI address map control */ | |
123 | #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ | |
124 | #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ | |
125 | #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ | |
126 | ||
127 | /* 5. ICU & GPIO regs */ | |
128 | /* GPIO Regs - r/w */ | |
129 | #define BONITO_GPIODATA_OFFSET 0x1c | |
130 | #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ | |
131 | #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ | |
132 | ||
133 | /* ICU Configuration Regs - r/w */ | |
134 | #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ | |
135 | #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ | |
136 | #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ | |
137 | ||
138 | /* ICU Enable Regs - IntEn & IntISR are r/o. */ | |
139 | #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ | |
140 | #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ | |
141 | #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ | |
142 | #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ | |
143 | ||
144 | /* PCI mail boxes */ | |
145 | #define BONITO_PCIMAIL0_OFFSET 0x40 | |
146 | #define BONITO_PCIMAIL1_OFFSET 0x44 | |
147 | #define BONITO_PCIMAIL2_OFFSET 0x48 | |
148 | #define BONITO_PCIMAIL3_OFFSET 0x4c | |
149 | #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ | |
150 | #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ | |
151 | #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ | |
152 | #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ | |
153 | ||
154 | /* 6. PCI cache */ | |
155 | #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ | |
156 | #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ | |
157 | #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ | |
158 | #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ | |
159 | ||
160 | /* 7. other*/ | |
161 | #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ | |
162 | #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ | |
163 | #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ | |
164 | #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ | |
165 | ||
166 | #define BONITO_REGS (0x70 >> 2) | |
167 | ||
168 | /* PCI config for south bridge. type 0 */ | |
169 | #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ | |
170 | #define BONITO_PCICONF_IDSEL_OFFSET 11 | |
171 | #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ | |
172 | #define BONITO_PCICONF_FUN_OFFSET 8 | |
173 | #define BONITO_PCICONF_REG_MASK 0xFC | |
174 | #define BONITO_PCICONF_REG_OFFSET 0 | |
175 | ||
176 | ||
177 | /* idsel BIT = pci slot number +12 */ | |
178 | #define PCI_SLOT_BASE 12 | |
179 | #define PCI_IDSEL_VIA686B_BIT (17) | |
f3db354c | 180 | #define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT) |
d0f7453d | 181 | |
f3db354c FB |
182 | #define PCI_ADDR(busno , devno , funno , regno) \ |
183 | ((((busno) << 16) & 0xff0000) + (((devno) << 11) & 0xf800) + \ | |
184 | (((funno) << 8) & 0x700) + (regno)) | |
d0f7453d | 185 | |
c5589ee9 | 186 | typedef struct BonitoState BonitoState; |
d0f7453d | 187 | |
f3db354c | 188 | typedef struct PCIBonitoState { |
d0f7453d | 189 | PCIDevice dev; |
c5589ee9 | 190 | |
d0f7453d HC |
191 | BonitoState *pcihost; |
192 | uint32_t regs[BONITO_REGS]; | |
193 | ||
194 | struct bonldma { | |
195 | uint32_t ldmactrl; | |
196 | uint32_t ldmastat; | |
197 | uint32_t ldmaaddr; | |
198 | uint32_t ldmago; | |
199 | } bonldma; | |
200 | ||
201 | /* Based at 1fe00300, bonito Copier */ | |
202 | struct boncop { | |
203 | uint32_t copctrl; | |
204 | uint32_t copstat; | |
205 | uint32_t coppaddr; | |
206 | uint32_t copgo; | |
207 | } boncop; | |
208 | ||
209 | /* Bonito registers */ | |
89200979 | 210 | MemoryRegion iomem; |
def344a6 | 211 | MemoryRegion iomem_ldma; |
9a542a48 | 212 | MemoryRegion iomem_cop; |
e37b80fa PB |
213 | MemoryRegion bonito_pciio; |
214 | MemoryRegion bonito_localio; | |
d0f7453d | 215 | |
d0f7453d HC |
216 | } PCIBonitoState; |
217 | ||
c5589ee9 AF |
218 | struct BonitoState { |
219 | PCIHostState parent_obj; | |
c5589ee9 | 220 | qemu_irq *pic; |
c5589ee9 | 221 | PCIBonitoState *pci_dev; |
f7cf2219 | 222 | MemoryRegion pci_mem; |
c5589ee9 | 223 | }; |
d0f7453d | 224 | |
a2a645d9 C |
225 | #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost" |
226 | #define BONITO_PCI_HOST_BRIDGE(obj) \ | |
227 | OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE) | |
228 | ||
229 | #define TYPE_PCI_BONITO "Bonito" | |
230 | #define PCI_BONITO(obj) \ | |
231 | OBJECT_CHECK(PCIBonitoState, (obj), TYPE_PCI_BONITO) | |
232 | ||
a8170e5e | 233 | static void bonito_writel(void *opaque, hwaddr addr, |
89200979 | 234 | uint64_t val, unsigned size) |
d0f7453d HC |
235 | { |
236 | PCIBonitoState *s = opaque; | |
237 | uint32_t saddr; | |
238 | int reset = 0; | |
239 | ||
0ca4f941 | 240 | saddr = addr >> 2; |
d0f7453d | 241 | |
f3db354c FB |
242 | DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", |
243 | addr, val, saddr); | |
d0f7453d HC |
244 | switch (saddr) { |
245 | case BONITO_BONPONCFG: | |
246 | case BONITO_IODEVCFG: | |
247 | case BONITO_SDCFG: | |
248 | case BONITO_PCIMAP: | |
249 | case BONITO_PCIMEMBASECFG: | |
250 | case BONITO_PCIMAP_CFG: | |
251 | case BONITO_GPIODATA: | |
252 | case BONITO_GPIOIE: | |
253 | case BONITO_INTEDGE: | |
254 | case BONITO_INTSTEER: | |
255 | case BONITO_INTPOL: | |
256 | case BONITO_PCIMAIL0: | |
257 | case BONITO_PCIMAIL1: | |
258 | case BONITO_PCIMAIL2: | |
259 | case BONITO_PCIMAIL3: | |
260 | case BONITO_PCICACHECTRL: | |
261 | case BONITO_PCICACHETAG: | |
262 | case BONITO_PCIBADADDR: | |
263 | case BONITO_PCIMSTAT: | |
264 | case BONITO_TIMECFG: | |
265 | case BONITO_CPUCFG: | |
266 | case BONITO_DQCFG: | |
267 | case BONITO_MEMSIZE: | |
268 | s->regs[saddr] = val; | |
269 | break; | |
270 | case BONITO_BONGENCFG: | |
271 | if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { | |
272 | reset = 1; /* bit 2 jump from 0 to 1 cause reset */ | |
273 | } | |
274 | s->regs[saddr] = val; | |
275 | if (reset) { | |
cf83f140 | 276 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
d0f7453d HC |
277 | } |
278 | break; | |
279 | case BONITO_INTENSET: | |
280 | s->regs[BONITO_INTENSET] = val; | |
281 | s->regs[BONITO_INTEN] |= val; | |
282 | break; | |
283 | case BONITO_INTENCLR: | |
284 | s->regs[BONITO_INTENCLR] = val; | |
285 | s->regs[BONITO_INTEN] &= ~val; | |
286 | break; | |
287 | case BONITO_INTEN: | |
288 | case BONITO_INTISR: | |
b2bedb21 | 289 | DPRINTF("write to readonly bonito register %x\n", saddr); |
d0f7453d HC |
290 | break; |
291 | default: | |
b2bedb21 | 292 | DPRINTF("write to unknown bonito register %x\n", saddr); |
d0f7453d HC |
293 | break; |
294 | } | |
295 | } | |
296 | ||
a8170e5e | 297 | static uint64_t bonito_readl(void *opaque, hwaddr addr, |
89200979 | 298 | unsigned size) |
d0f7453d HC |
299 | { |
300 | PCIBonitoState *s = opaque; | |
301 | uint32_t saddr; | |
302 | ||
0ca4f941 | 303 | saddr = addr >> 2; |
d0f7453d | 304 | |
b2bedb21 | 305 | DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); |
d0f7453d HC |
306 | switch (saddr) { |
307 | case BONITO_INTISR: | |
308 | return s->regs[saddr]; | |
309 | default: | |
310 | return s->regs[saddr]; | |
311 | } | |
312 | } | |
313 | ||
89200979 BC |
314 | static const MemoryRegionOps bonito_ops = { |
315 | .read = bonito_readl, | |
316 | .write = bonito_writel, | |
317 | .endianness = DEVICE_NATIVE_ENDIAN, | |
318 | .valid = { | |
319 | .min_access_size = 4, | |
320 | .max_access_size = 4, | |
321 | }, | |
d0f7453d HC |
322 | }; |
323 | ||
a8170e5e | 324 | static void bonito_pciconf_writel(void *opaque, hwaddr addr, |
183e1d40 | 325 | uint64_t val, unsigned size) |
d0f7453d HC |
326 | { |
327 | PCIBonitoState *s = opaque; | |
c5589ee9 | 328 | PCIDevice *d = PCI_DEVICE(s); |
d0f7453d | 329 | |
b2bedb21 | 330 | DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); |
c5589ee9 | 331 | d->config_write(d, addr, val, 4); |
d0f7453d HC |
332 | } |
333 | ||
a8170e5e | 334 | static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr, |
183e1d40 | 335 | unsigned size) |
d0f7453d HC |
336 | { |
337 | ||
338 | PCIBonitoState *s = opaque; | |
c5589ee9 | 339 | PCIDevice *d = PCI_DEVICE(s); |
d0f7453d HC |
340 | |
341 | DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); | |
c5589ee9 | 342 | return d->config_read(d, addr, 4); |
d0f7453d HC |
343 | } |
344 | ||
345 | /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ | |
d0f7453d | 346 | |
183e1d40 BC |
347 | static const MemoryRegionOps bonito_pciconf_ops = { |
348 | .read = bonito_pciconf_readl, | |
349 | .write = bonito_pciconf_writel, | |
350 | .endianness = DEVICE_NATIVE_ENDIAN, | |
351 | .valid = { | |
352 | .min_access_size = 4, | |
353 | .max_access_size = 4, | |
354 | }, | |
d0f7453d HC |
355 | }; |
356 | ||
a8170e5e | 357 | static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr, |
def344a6 | 358 | unsigned size) |
d0f7453d HC |
359 | { |
360 | uint32_t val; | |
361 | PCIBonitoState *s = opaque; | |
362 | ||
58d47978 PM |
363 | if (addr >= sizeof(s->bonldma)) { |
364 | return 0; | |
365 | } | |
366 | ||
f3db354c | 367 | val = ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)]; |
d0f7453d HC |
368 | |
369 | return val; | |
370 | } | |
371 | ||
a8170e5e | 372 | static void bonito_ldma_writel(void *opaque, hwaddr addr, |
def344a6 | 373 | uint64_t val, unsigned size) |
d0f7453d HC |
374 | { |
375 | PCIBonitoState *s = opaque; | |
376 | ||
58d47978 PM |
377 | if (addr >= sizeof(s->bonldma)) { |
378 | return; | |
379 | } | |
380 | ||
f3db354c | 381 | ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff; |
d0f7453d HC |
382 | } |
383 | ||
def344a6 BC |
384 | static const MemoryRegionOps bonito_ldma_ops = { |
385 | .read = bonito_ldma_readl, | |
386 | .write = bonito_ldma_writel, | |
387 | .endianness = DEVICE_NATIVE_ENDIAN, | |
388 | .valid = { | |
389 | .min_access_size = 4, | |
390 | .max_access_size = 4, | |
391 | }, | |
d0f7453d HC |
392 | }; |
393 | ||
a8170e5e | 394 | static uint64_t bonito_cop_readl(void *opaque, hwaddr addr, |
9a542a48 | 395 | unsigned size) |
d0f7453d HC |
396 | { |
397 | uint32_t val; | |
398 | PCIBonitoState *s = opaque; | |
399 | ||
58d47978 PM |
400 | if (addr >= sizeof(s->boncop)) { |
401 | return 0; | |
402 | } | |
403 | ||
f3db354c | 404 | val = ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)]; |
d0f7453d HC |
405 | |
406 | return val; | |
407 | } | |
408 | ||
a8170e5e | 409 | static void bonito_cop_writel(void *opaque, hwaddr addr, |
9a542a48 | 410 | uint64_t val, unsigned size) |
d0f7453d HC |
411 | { |
412 | PCIBonitoState *s = opaque; | |
413 | ||
58d47978 PM |
414 | if (addr >= sizeof(s->boncop)) { |
415 | return; | |
416 | } | |
417 | ||
f3db354c | 418 | ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff; |
d0f7453d HC |
419 | } |
420 | ||
9a542a48 BC |
421 | static const MemoryRegionOps bonito_cop_ops = { |
422 | .read = bonito_cop_readl, | |
423 | .write = bonito_cop_writel, | |
424 | .endianness = DEVICE_NATIVE_ENDIAN, | |
425 | .valid = { | |
426 | .min_access_size = 4, | |
427 | .max_access_size = 4, | |
428 | }, | |
d0f7453d HC |
429 | }; |
430 | ||
a8170e5e | 431 | static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr) |
d0f7453d HC |
432 | { |
433 | PCIBonitoState *s = opaque; | |
8558d942 | 434 | PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); |
d0f7453d HC |
435 | uint32_t cfgaddr; |
436 | uint32_t idsel; | |
437 | uint32_t devno; | |
438 | uint32_t funno; | |
439 | uint32_t regno; | |
440 | uint32_t pciaddr; | |
441 | ||
442 | /* support type0 pci config */ | |
443 | if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { | |
444 | return 0xffffffff; | |
445 | } | |
446 | ||
447 | cfgaddr = addr & 0xffff; | |
448 | cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; | |
449 | ||
f3db354c FB |
450 | idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> |
451 | BONITO_PCICONF_IDSEL_OFFSET; | |
786a4ea8 | 452 | devno = ctz32(idsel); |
d0f7453d HC |
453 | funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; |
454 | regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; | |
455 | ||
456 | if (idsel == 0) { | |
0151abe4 AF |
457 | error_report("error in bonito pci config address " TARGET_FMT_plx |
458 | ",pcimap_cfg=%x", addr, s->regs[BONITO_PCIMAP_CFG]); | |
d0f7453d HC |
459 | exit(1); |
460 | } | |
c5589ee9 | 461 | pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); |
b2bedb21 | 462 | DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", |
c5589ee9 | 463 | cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); |
d0f7453d HC |
464 | |
465 | return pciaddr; | |
466 | } | |
467 | ||
421ab725 PM |
468 | static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val, |
469 | unsigned size) | |
d0f7453d HC |
470 | { |
471 | PCIBonitoState *s = opaque; | |
c5589ee9 | 472 | PCIDevice *d = PCI_DEVICE(s); |
8558d942 | 473 | PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); |
d0f7453d HC |
474 | uint32_t pciaddr; |
475 | uint16_t status; | |
476 | ||
421ab725 PM |
477 | DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %x\n", |
478 | addr, size, val); | |
d0f7453d HC |
479 | |
480 | pciaddr = bonito_sbridge_pciaddr(s, addr); | |
481 | ||
482 | if (pciaddr == 0xffffffff) { | |
483 | return; | |
484 | } | |
485 | ||
486 | /* set the pci address in s->config_reg */ | |
c5589ee9 | 487 | phb->config_reg = (pciaddr) | (1u << 31); |
421ab725 | 488 | pci_data_write(phb->bus, phb->config_reg, val, size); |
d0f7453d HC |
489 | |
490 | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ | |
c5589ee9 | 491 | status = pci_get_word(d->config + PCI_STATUS); |
d0f7453d | 492 | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
c5589ee9 | 493 | pci_set_word(d->config + PCI_STATUS, status); |
d0f7453d HC |
494 | } |
495 | ||
421ab725 | 496 | static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size) |
d0f7453d HC |
497 | { |
498 | PCIBonitoState *s = opaque; | |
c5589ee9 | 499 | PCIDevice *d = PCI_DEVICE(s); |
8558d942 | 500 | PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); |
d0f7453d HC |
501 | uint32_t pciaddr; |
502 | uint16_t status; | |
503 | ||
421ab725 | 504 | DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size); |
d0f7453d HC |
505 | |
506 | pciaddr = bonito_sbridge_pciaddr(s, addr); | |
507 | ||
508 | if (pciaddr == 0xffffffff) { | |
421ab725 | 509 | return MAKE_64BIT_MASK(0, size * 8); |
d0f7453d HC |
510 | } |
511 | ||
512 | /* set the pci address in s->config_reg */ | |
c5589ee9 | 513 | phb->config_reg = (pciaddr) | (1u << 31); |
d0f7453d HC |
514 | |
515 | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ | |
c5589ee9 | 516 | status = pci_get_word(d->config + PCI_STATUS); |
d0f7453d | 517 | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
c5589ee9 | 518 | pci_set_word(d->config + PCI_STATUS, status); |
d0f7453d | 519 | |
421ab725 | 520 | return pci_data_read(phb->bus, phb->config_reg, size); |
d0f7453d HC |
521 | } |
522 | ||
523 | /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ | |
845cbeb8 | 524 | static const MemoryRegionOps bonito_spciconf_ops = { |
421ab725 PM |
525 | .read = bonito_spciconf_read, |
526 | .write = bonito_spciconf_write, | |
527 | .valid.min_access_size = 1, | |
528 | .valid.max_access_size = 4, | |
529 | .impl.min_access_size = 1, | |
530 | .impl.max_access_size = 4, | |
845cbeb8 | 531 | .endianness = DEVICE_NATIVE_ENDIAN, |
d0f7453d HC |
532 | }; |
533 | ||
534 | #define BONITO_IRQ_BASE 32 | |
535 | ||
536 | static void pci_bonito_set_irq(void *opaque, int irq_num, int level) | |
537 | { | |
c5589ee9 AF |
538 | BonitoState *s = opaque; |
539 | qemu_irq *pic = s->pic; | |
540 | PCIBonitoState *bonito_state = s->pci_dev; | |
d0f7453d HC |
541 | int internal_irq = irq_num - BONITO_IRQ_BASE; |
542 | ||
c5589ee9 | 543 | if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) { |
d0f7453d HC |
544 | qemu_irq_pulse(*pic); |
545 | } else { /* level triggered */ | |
c5589ee9 | 546 | if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) { |
d0f7453d HC |
547 | qemu_irq_raise(*pic); |
548 | } else { | |
549 | qemu_irq_lower(*pic); | |
550 | } | |
551 | } | |
552 | } | |
553 | ||
554 | /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ | |
f3db354c | 555 | static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num) |
d0f7453d HC |
556 | { |
557 | int slot; | |
558 | ||
559 | slot = (pci_dev->devfn >> 3); | |
560 | ||
561 | switch (slot) { | |
562 | case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ | |
563 | return irq_num % 4 + BONITO_IRQ_BASE; | |
564 | case 6: /* FULONG2E_ATI_SLOT, VGA */ | |
565 | return 4 + BONITO_IRQ_BASE; | |
566 | case 7: /* FULONG2E_RTL_SLOT, RTL8139 */ | |
567 | return 5 + BONITO_IRQ_BASE; | |
568 | case 8 ... 12: /* PCI slot 1 to 4 */ | |
569 | return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; | |
570 | default: /* Unknown device, don't do any translation */ | |
571 | return irq_num; | |
572 | } | |
573 | } | |
574 | ||
575 | static void bonito_reset(void *opaque) | |
576 | { | |
577 | PCIBonitoState *s = opaque; | |
578 | ||
579 | /* set the default value of north bridge registers */ | |
580 | ||
581 | s->regs[BONITO_BONPONCFG] = 0xc40; | |
582 | s->regs[BONITO_BONGENCFG] = 0x1384; | |
583 | s->regs[BONITO_IODEVCFG] = 0x2bff8010; | |
584 | s->regs[BONITO_SDCFG] = 0x255e0091; | |
585 | ||
586 | s->regs[BONITO_GPIODATA] = 0x1ff; | |
587 | s->regs[BONITO_GPIOIE] = 0x1ff; | |
588 | s->regs[BONITO_DQCFG] = 0x8; | |
589 | s->regs[BONITO_MEMSIZE] = 0x10000000; | |
590 | s->regs[BONITO_PCIMAP] = 0x6140; | |
591 | } | |
592 | ||
593 | static const VMStateDescription vmstate_bonito = { | |
594 | .name = "Bonito", | |
595 | .version_id = 1, | |
596 | .minimum_version_id = 1, | |
35d08458 | 597 | .fields = (VMStateField[]) { |
d0f7453d HC |
598 | VMSTATE_PCI_DEVICE(dev, PCIBonitoState), |
599 | VMSTATE_END_OF_LIST() | |
600 | } | |
601 | }; | |
602 | ||
e800894a | 603 | static void bonito_pcihost_realize(DeviceState *dev, Error **errp) |
d0f7453d | 604 | { |
8558d942 | 605 | PCIHostState *phb = PCI_HOST_BRIDGE(dev); |
f7cf2219 | 606 | BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev); |
c5589ee9 | 607 | |
f7cf2219 | 608 | memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCILO_SIZE); |
1115ff6d DG |
609 | phb->bus = pci_register_root_bus(DEVICE(dev), "pci", |
610 | pci_bonito_set_irq, pci_bonito_map_irq, | |
f7cf2219 | 611 | dev, &bs->pci_mem, get_system_io(), |
1115ff6d | 612 | 0x28, 32, TYPE_PCI_BUS); |
f7cf2219 BZ |
613 | memory_region_add_subregion(get_system_memory(), BONITO_PCILO_BASE, |
614 | &bs->pci_mem); | |
d0f7453d HC |
615 | } |
616 | ||
9af21dbe | 617 | static void bonito_realize(PCIDevice *dev, Error **errp) |
d0f7453d | 618 | { |
a2a645d9 | 619 | PCIBonitoState *s = PCI_BONITO(dev); |
c5589ee9 | 620 | SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost); |
8558d942 | 621 | PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); |
d0f7453d | 622 | |
f3db354c FB |
623 | /* |
624 | * Bonito North Bridge, built on FPGA, | |
625 | * VENDOR_ID/DEVICE_ID are "undefined" | |
626 | */ | |
d0f7453d | 627 | pci_config_set_prog_interface(dev->config, 0x00); |
d0f7453d HC |
628 | |
629 | /* set the north bridge register mapping */ | |
40c5dce9 | 630 | memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s, |
89200979 | 631 | "north-bridge-register", BONITO_INTERNAL_REG_SIZE); |
750ecd44 | 632 | sysbus_init_mmio(sysbus, &s->iomem); |
89200979 | 633 | sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); |
d0f7453d HC |
634 | |
635 | /* set the north bridge pci configure mapping */ | |
40c5dce9 | 636 | memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s, |
183e1d40 | 637 | "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); |
c5589ee9 | 638 | sysbus_init_mmio(sysbus, &phb->conf_mem); |
183e1d40 | 639 | sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); |
d0f7453d HC |
640 | |
641 | /* set the south bridge pci configure mapping */ | |
40c5dce9 | 642 | memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s, |
845cbeb8 | 643 | "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE); |
c5589ee9 | 644 | sysbus_init_mmio(sysbus, &phb->data_mem); |
845cbeb8 | 645 | sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE); |
d0f7453d | 646 | |
40c5dce9 | 647 | memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s, |
def344a6 | 648 | "ldma", 0x100); |
750ecd44 | 649 | sysbus_init_mmio(sysbus, &s->iomem_ldma); |
def344a6 | 650 | sysbus_mmio_map(sysbus, 3, 0xbfe00200); |
d0f7453d | 651 | |
40c5dce9 | 652 | memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s, |
9a542a48 | 653 | "cop", 0x100); |
750ecd44 | 654 | sysbus_init_mmio(sysbus, &s->iomem_cop); |
9a542a48 | 655 | sysbus_mmio_map(sysbus, 4, 0xbfe00300); |
d0f7453d HC |
656 | |
657 | /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ | |
e37b80fa PB |
658 | memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio", |
659 | get_system_io(), 0, BONITO_PCIIO_SIZE); | |
660 | sysbus_init_mmio(sysbus, &s->bonito_pciio); | |
661 | sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE); | |
d0f7453d HC |
662 | |
663 | /* add pci local io mapping */ | |
e37b80fa PB |
664 | memory_region_init_alias(&s->bonito_localio, OBJECT(s), "isa_mmio", |
665 | get_system_io(), 0, BONITO_DEV_SIZE); | |
666 | sysbus_init_mmio(sysbus, &s->bonito_localio); | |
667 | sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE); | |
d0f7453d HC |
668 | |
669 | /* set the default value of north bridge pci config */ | |
670 | pci_set_word(dev->config + PCI_COMMAND, 0x0000); | |
671 | pci_set_word(dev->config + PCI_STATUS, 0x0000); | |
672 | pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); | |
673 | pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); | |
674 | ||
675 | pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); | |
676 | pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01); | |
677 | pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); | |
678 | pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); | |
679 | ||
680 | qemu_register_reset(bonito_reset, s); | |
d0f7453d HC |
681 | } |
682 | ||
683 | PCIBus *bonito_init(qemu_irq *pic) | |
684 | { | |
685 | DeviceState *dev; | |
d0f7453d | 686 | BonitoState *pcihost; |
c5589ee9 | 687 | PCIHostState *phb; |
d0f7453d HC |
688 | PCIBonitoState *s; |
689 | PCIDevice *d; | |
690 | ||
c5589ee9 | 691 | dev = qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE); |
8558d942 | 692 | phb = PCI_HOST_BRIDGE(dev); |
c5589ee9 AF |
693 | pcihost = BONITO_PCI_HOST_BRIDGE(dev); |
694 | pcihost->pic = pic; | |
d0f7453d | 695 | qdev_init_nofail(dev); |
d0f7453d | 696 | |
a2a645d9 C |
697 | d = pci_create(phb->bus, PCI_DEVFN(0, 0), TYPE_PCI_BONITO); |
698 | s = PCI_BONITO(d); | |
d0f7453d | 699 | s->pcihost = pcihost; |
c5589ee9 AF |
700 | pcihost->pci_dev = s; |
701 | qdev_init_nofail(DEVICE(d)); | |
d0f7453d | 702 | |
c5589ee9 | 703 | return phb->bus; |
d0f7453d HC |
704 | } |
705 | ||
40021f08 AL |
706 | static void bonito_class_init(ObjectClass *klass, void *data) |
707 | { | |
39bffca2 | 708 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
709 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
710 | ||
9af21dbe | 711 | k->realize = bonito_realize; |
40021f08 AL |
712 | k->vendor_id = 0xdf53; |
713 | k->device_id = 0x00d5; | |
714 | k->revision = 0x01; | |
715 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
39bffca2 | 716 | dc->desc = "Host bridge"; |
39bffca2 | 717 | dc->vmsd = &vmstate_bonito; |
08c58f92 MA |
718 | /* |
719 | * PCI-facing part of the host bridge, not usable without the | |
720 | * host-facing part, which can't be device_add'ed, yet. | |
721 | */ | |
e90f2a8c | 722 | dc->user_creatable = false; |
40021f08 AL |
723 | } |
724 | ||
4240abff | 725 | static const TypeInfo bonito_info = { |
a2a645d9 | 726 | .name = TYPE_PCI_BONITO, |
39bffca2 AL |
727 | .parent = TYPE_PCI_DEVICE, |
728 | .instance_size = sizeof(PCIBonitoState), | |
729 | .class_init = bonito_class_init, | |
fd3b02c8 EH |
730 | .interfaces = (InterfaceInfo[]) { |
731 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
732 | { }, | |
733 | }, | |
d0f7453d HC |
734 | }; |
735 | ||
999e12bb AL |
736 | static void bonito_pcihost_class_init(ObjectClass *klass, void *data) |
737 | { | |
e800894a | 738 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 739 | |
e800894a | 740 | dc->realize = bonito_pcihost_realize; |
999e12bb AL |
741 | } |
742 | ||
4240abff | 743 | static const TypeInfo bonito_pcihost_info = { |
c5589ee9 | 744 | .name = TYPE_BONITO_PCI_HOST_BRIDGE, |
8558d942 | 745 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 AL |
746 | .instance_size = sizeof(BonitoState), |
747 | .class_init = bonito_pcihost_class_init, | |
d0f7453d HC |
748 | }; |
749 | ||
83f7d43a | 750 | static void bonito_register_types(void) |
d0f7453d | 751 | { |
39bffca2 AL |
752 | type_register_static(&bonito_pcihost_info); |
753 | type_register_static(&bonito_info); | |
d0f7453d | 754 | } |
83f7d43a AF |
755 | |
756 | type_init(bonito_register_types) |