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502a5395 1/*
3cbee15b 2 * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
502a5395 3 *
3cbee15b
JM
4 * Copyright (c) 2006-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
5fafdf24 6 *
502a5395
PB
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
0d75590d 26#include "qemu/osdep.h"
83c9f4ca
PB
27#include "hw/pci/pci_host.h"
28#include "hw/ppc/mac.h"
a27bd6c7 29#include "hw/qdev-properties.h"
83c9f4ca 30#include "hw/pci/pci.h"
b0318ec1 31#include "hw/intc/heathrow_pic.h"
64552b6b 32#include "hw/irq.h"
b0318ec1 33#include "qapi/error.h"
0b8fa32f 34#include "qemu/module.h"
b728fbbc 35#include "trace.h"
ea026b2f 36
0e655047
AF
37#define GRACKLE_PCI_HOST_BRIDGE(obj) \
38 OBJECT_CHECK(GrackleState, (obj), TYPE_GRACKLE_PCI_HOST_BRIDGE)
39
426f17bb 40typedef struct GrackleState {
67c332fd 41 PCIHostState parent_obj;
0e655047 42
ac43eb2e 43 uint32_t ofw_addr;
b0318ec1
MCA
44 HeathrowState *pic;
45 qemu_irq irqs[4];
46f3069c
BS
46 MemoryRegion pci_mmio;
47 MemoryRegion pci_hole;
a94e5f99 48 MemoryRegion pci_io;
426f17bb 49} GrackleState;
502a5395 50
d2b59317
PB
51/* Don't know if this matches real hardware, but it agrees with OHW. */
52static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395 53{
d2b59317
PB
54 return (irq_num + (pci_dev->devfn >> 3)) & 3;
55}
56
5d4e84c8 57static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
d2b59317 58{
b0318ec1 59 GrackleState *s = opaque;
5d4e84c8 60
b728fbbc 61 trace_grackle_set_irq(irq_num, level);
b0318ec1 62 qemu_set_irq(s->irqs[irq_num], level);
502a5395
PB
63}
64
b0318ec1
MCA
65static void grackle_init_irqs(GrackleState *s)
66{
67 int i;
68
69 for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
70 s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), 0x15 + i);
71 }
72}
73
b0318ec1
MCA
74static void grackle_realize(DeviceState *dev, Error **errp)
75{
76 GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev);
77 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
78
1115ff6d
DG
79 phb->bus = pci_register_root_bus(dev, NULL,
80 pci_grackle_set_irq,
81 pci_grackle_map_irq,
b0318ec1
MCA
82 s,
83 &s->pci_mmio,
a94e5f99 84 &s->pci_io,
1115ff6d 85 0, 4, TYPE_PCI_BUS);
426f17bb 86
0e655047 87 pci_create_simple(phb->bus, 0, "grackle");
b0318ec1 88 grackle_init_irqs(s);
426f17bb
BS
89}
90
b0318ec1 91static void grackle_init(Object *obj)
426f17bb 92{
b0318ec1
MCA
93 GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(obj);
94 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
95 PCIHostState *phb = PCI_HOST_BRIDGE(obj);
426f17bb 96
b0318ec1 97 memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
a94e5f99
MCA
98 memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
99 "pci-isa-mmio", 0x00200000);
100
b0318ec1
MCA
101 memory_region_init_alias(&s->pci_hole, OBJECT(s), "pci-hole", &s->pci_mmio,
102 0x80000000ULL, 0x7e000000ULL);
426f17bb 103
b0318ec1
MCA
104 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops,
105 DEVICE(obj), "pci-conf-idx", 0x1000);
106 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops,
107 DEVICE(obj), "pci-data-idx", 0x1000);
426f17bb 108
b0318ec1
MCA
109 object_property_add_link(obj, "pic", TYPE_HEATHROW,
110 (Object **) &s->pic,
111 qdev_prop_allow_set_link_before_realize,
d2623129 112 0);
b0318ec1
MCA
113
114 sysbus_init_mmio(sbd, &phb->conf_mem);
115 sysbus_init_mmio(sbd, &phb->data_mem);
a773e64a 116 sysbus_init_mmio(sbd, &s->pci_hole);
a94e5f99 117 sysbus_init_mmio(sbd, &s->pci_io);
426f17bb
BS
118}
119
b0318ec1 120static void grackle_pci_realize(PCIDevice *d, Error **errp)
426f17bb 121{
502a5395 122 d->config[0x09] = 0x01;
426f17bb 123}
502a5395 124
40021f08
AL
125static void grackle_pci_class_init(ObjectClass *klass, void *data)
126{
39bffca2 127 DeviceClass *dc = DEVICE_CLASS(klass);
b0318ec1 128 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 129
b0318ec1 130 k->realize = grackle_pci_realize;
40021f08
AL
131 k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
132 k->device_id = PCI_DEVICE_ID_MOTOROLA_MPC106;
133 k->revision = 0x00;
134 k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92
MA
135 /*
136 * PCI-facing part of the host bridge, not usable without the
137 * host-facing part, which can't be device_add'ed, yet.
138 */
e90f2a8c 139 dc->user_creatable = false;
40021f08
AL
140}
141
4240abff 142static const TypeInfo grackle_pci_info = {
39bffca2
AL
143 .name = "grackle",
144 .parent = TYPE_PCI_DEVICE,
145 .instance_size = sizeof(PCIDevice),
40021f08 146 .class_init = grackle_pci_class_init,
fd3b02c8
EH
147 .interfaces = (InterfaceInfo[]) {
148 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
149 { },
150 },
426f17bb 151};
6e6b7363 152
ac43eb2e
MCA
153static char *grackle_ofw_unit_address(const SysBusDevice *dev)
154{
155 GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev);
156
157 return g_strdup_printf("%x", s->ofw_addr);
158}
159
160static Property grackle_properties[] = {
161 DEFINE_PROP_UINT32("ofw-addr", GrackleState, ofw_addr, -1),
162 DEFINE_PROP_END_OF_LIST()
163};
164
b0318ec1 165static void grackle_class_init(ObjectClass *klass, void *data)
999e12bb 166{
e1624435 167 DeviceClass *dc = DEVICE_CLASS(klass);
ac43eb2e 168 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
999e12bb 169
b0318ec1 170 dc->realize = grackle_realize;
4f67d30b 171 device_class_set_props(dc, grackle_properties);
e1624435 172 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
ac43eb2e
MCA
173 dc->fw_name = "pci";
174 sbc->explicit_ofw_unit_address = grackle_ofw_unit_address;
999e12bb
AL
175}
176
b0318ec1 177static const TypeInfo grackle_host_info = {
0e655047 178 .name = TYPE_GRACKLE_PCI_HOST_BRIDGE,
8558d942 179 .parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 180 .instance_size = sizeof(GrackleState),
b0318ec1
MCA
181 .instance_init = grackle_init,
182 .class_init = grackle_class_init,
0ae46996
AF
183};
184
83f7d43a 185static void grackle_register_types(void)
426f17bb 186{
39bffca2 187 type_register_static(&grackle_pci_info);
b0318ec1 188 type_register_static(&grackle_host_info);
502a5395 189}
426f17bb 190
83f7d43a 191type_init(grackle_register_types)