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Commit | Line | Data |
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502a5395 | 1 | /* |
9b301794 | 2 | * QEMU Ultrasparc Sabre PCI host (PBM) |
502a5395 PB |
3 | * |
4 | * Copyright (c) 2006 Fabrice Bellard | |
9625036d | 5 | * Copyright (c) 2012,2013 Artyom Tarasenko |
9b301794 | 6 | * Copyright (c) 2018 Mark Cave-Ayland |
5fafdf24 | 7 | * |
502a5395 PB |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | */ | |
80b3ada7 | 26 | |
97d5408f | 27 | #include "qemu/osdep.h" |
83c9f4ca PB |
28 | #include "hw/sysbus.h" |
29 | #include "hw/pci/pci.h" | |
30 | #include "hw/pci/pci_host.h" | |
a27bd6c7 | 31 | #include "hw/qdev-properties.h" |
83c9f4ca PB |
32 | #include "hw/pci/pci_bridge.h" |
33 | #include "hw/pci/pci_bus.h" | |
64552b6b | 34 | #include "hw/irq.h" |
ffd9589e | 35 | #include "hw/pci-bridge/simba.h" |
9b301794 | 36 | #include "hw/pci-host/sabre.h" |
022c62cb | 37 | #include "exec/address-spaces.h" |
03dd024f | 38 | #include "qemu/log.h" |
0b8fa32f | 39 | #include "qemu/module.h" |
54d31236 | 40 | #include "sysemu/runstate.h" |
bfec08b5 | 41 | #include "trace.h" |
a94fd955 | 42 | |
930f3fe1 BS |
43 | /* |
44 | * Chipset docs: | |
45 | * PBM: "UltraSPARC IIi User's Manual", | |
46 | * http://www.sun.com/processors/manuals/805-0087.pdf | |
930f3fe1 BS |
47 | */ |
48 | ||
95819af0 BS |
49 | #define PBM_PCI_IMR_MASK 0x7fffffff |
50 | #define PBM_PCI_IMR_ENABLED 0x80000000 | |
51 | ||
af23906d PM |
52 | #define POR (1U << 31) |
53 | #define SOFT_POR (1U << 30) | |
54 | #define SOFT_XIR (1U << 29) | |
55 | #define BTN_POR (1U << 28) | |
56 | #define BTN_XIR (1U << 27) | |
95819af0 BS |
57 | #define RESET_MASK 0xf8000000 |
58 | #define RESET_WCMASK 0x98000000 | |
59 | #define RESET_WMASK 0x60000000 | |
60 | ||
9625036d | 61 | #define NO_IRQ_REQUEST (MAX_IVEC + 1) |
361dea40 | 62 | |
b14dcaf4 | 63 | static inline void sabre_set_request(SabreState *s, unsigned int irq_num) |
9625036d | 64 | { |
bfec08b5 | 65 | trace_sabre_set_request(irq_num); |
9625036d AT |
66 | s->irq_request = irq_num; |
67 | qemu_set_irq(s->ivec_irqs[irq_num], 1); | |
68 | } | |
69 | ||
b14dcaf4 | 70 | static inline void sabre_check_irqs(SabreState *s) |
9625036d | 71 | { |
9625036d AT |
72 | unsigned int i; |
73 | ||
74 | /* Previous request is not acknowledged, resubmit */ | |
75 | if (s->irq_request != NO_IRQ_REQUEST) { | |
fe984c7d | 76 | sabre_set_request(s, s->irq_request); |
9625036d AT |
77 | return; |
78 | } | |
79 | /* no request pending */ | |
80 | if (s->pci_irq_in == 0ULL) { | |
81 | return; | |
82 | } | |
83 | for (i = 0; i < 32; i++) { | |
84 | if (s->pci_irq_in & (1ULL << i)) { | |
85 | if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) { | |
fe984c7d | 86 | sabre_set_request(s, i); |
9625036d AT |
87 | return; |
88 | } | |
89 | } | |
90 | } | |
91 | for (i = 32; i < 64; i++) { | |
92 | if (s->pci_irq_in & (1ULL << i)) { | |
93 | if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) { | |
fe984c7d | 94 | sabre_set_request(s, i); |
9625036d AT |
95 | break; |
96 | } | |
97 | } | |
98 | } | |
99 | } | |
100 | ||
b14dcaf4 | 101 | static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) |
9625036d | 102 | { |
bfec08b5 | 103 | trace_sabre_clear_request(irq_num); |
9625036d AT |
104 | qemu_set_irq(s->ivec_irqs[irq_num], 0); |
105 | s->irq_request = NO_IRQ_REQUEST; | |
106 | } | |
94d19914 | 107 | |
fe984c7d | 108 | static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
ae74bbe7 MCA |
109 | { |
110 | IOMMUState *is = opaque; | |
111 | ||
112 | return &is->iommu_as; | |
113 | } | |
114 | ||
fe984c7d | 115 | static void sabre_config_write(void *opaque, hwaddr addr, |
3812ed0b | 116 | uint64_t val, unsigned size) |
502a5395 | 117 | { |
b14dcaf4 | 118 | SabreState *s = opaque; |
95819af0 | 119 | |
bfec08b5 | 120 | trace_sabre_config_write(addr, val); |
95819af0 BS |
121 | |
122 | switch (addr & 0xffff) { | |
123 | case 0x30 ... 0x4f: /* DMA error registers */ | |
124 | /* XXX: not implemented yet */ | |
125 | break; | |
95819af0 BS |
126 | case 0xc00 ... 0xc3f: /* PCI interrupt control */ |
127 | if (addr & 4) { | |
9625036d AT |
128 | unsigned int ino = (addr & 0x3f) >> 3; |
129 | s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK; | |
130 | s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; | |
131 | if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) { | |
fe984c7d | 132 | sabre_clear_request(s, ino); |
9625036d | 133 | } |
fe984c7d | 134 | sabre_check_irqs(s); |
95819af0 BS |
135 | } |
136 | break; | |
de739df8 | 137 | case 0x1000 ... 0x107f: /* OBIO interrupt control */ |
361dea40 | 138 | if (addr & 4) { |
9625036d AT |
139 | unsigned int ino = ((addr & 0xff) >> 3); |
140 | s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK; | |
141 | s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; | |
142 | if ((s->irq_request == (ino | 0x20)) | |
143 | && !(val & ~PBM_PCI_IMR_MASK)) { | |
fe984c7d | 144 | sabre_clear_request(s, ino | 0x20); |
9625036d | 145 | } |
fe984c7d | 146 | sabre_check_irqs(s); |
361dea40 BS |
147 | } |
148 | break; | |
9625036d | 149 | case 0x1400 ... 0x14ff: /* PCI interrupt clear */ |
94d19914 | 150 | if (addr & 4) { |
9625036d AT |
151 | unsigned int ino = (addr & 0xff) >> 5; |
152 | if ((s->irq_request / 4) == ino) { | |
fe984c7d MCA |
153 | sabre_clear_request(s, s->irq_request); |
154 | sabre_check_irqs(s); | |
9625036d | 155 | } |
94d19914 AT |
156 | } |
157 | break; | |
158 | case 0x1800 ... 0x1860: /* OBIO interrupt clear */ | |
159 | if (addr & 4) { | |
9625036d AT |
160 | unsigned int ino = ((addr & 0xff) >> 3) | 0x20; |
161 | if (s->irq_request == ino) { | |
fe984c7d MCA |
162 | sabre_clear_request(s, ino); |
163 | sabre_check_irqs(s); | |
9625036d | 164 | } |
94d19914 AT |
165 | } |
166 | break; | |
95819af0 BS |
167 | case 0x2000 ... 0x202f: /* PCI control */ |
168 | s->pci_control[(addr & 0x3f) >> 2] = val; | |
169 | break; | |
170 | case 0xf020 ... 0xf027: /* Reset control */ | |
171 | if (addr & 4) { | |
172 | val &= RESET_MASK; | |
173 | s->reset_control &= ~(val & RESET_WCMASK); | |
174 | s->reset_control |= val & RESET_WMASK; | |
175 | if (val & SOFT_POR) { | |
9c0afd0e | 176 | s->nr_resets = 0; |
cf83f140 | 177 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
95819af0 | 178 | } else if (val & SOFT_XIR) { |
cf83f140 | 179 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
95819af0 BS |
180 | } |
181 | } | |
182 | break; | |
183 | case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ | |
184 | case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ | |
185 | case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ | |
186 | case 0xf000 ... 0xf01f: /* FFB config, memory control */ | |
187 | /* we don't care */ | |
502a5395 | 188 | default: |
f930d07e | 189 | break; |
502a5395 PB |
190 | } |
191 | } | |
192 | ||
fe984c7d | 193 | static uint64_t sabre_config_read(void *opaque, |
a8170e5e | 194 | hwaddr addr, unsigned size) |
502a5395 | 195 | { |
b14dcaf4 | 196 | SabreState *s = opaque; |
502a5395 PB |
197 | uint32_t val; |
198 | ||
95819af0 BS |
199 | switch (addr & 0xffff) { |
200 | case 0x30 ... 0x4f: /* DMA error registers */ | |
201 | val = 0; | |
202 | /* XXX: not implemented yet */ | |
203 | break; | |
95819af0 BS |
204 | case 0xc00 ... 0xc3f: /* PCI interrupt control */ |
205 | if (addr & 4) { | |
206 | val = s->pci_irq_map[(addr & 0x3f) >> 3]; | |
207 | } else { | |
208 | val = 0; | |
209 | } | |
210 | break; | |
de739df8 | 211 | case 0x1000 ... 0x107f: /* OBIO interrupt control */ |
361dea40 BS |
212 | if (addr & 4) { |
213 | val = s->obio_irq_map[(addr & 0xff) >> 3]; | |
214 | } else { | |
215 | val = 0; | |
216 | } | |
217 | break; | |
de739df8 MCA |
218 | case 0x1080 ... 0x108f: /* PCI bus error */ |
219 | if (addr & 4) { | |
220 | val = s->pci_err_irq_map[(addr & 0xf) >> 3]; | |
221 | } else { | |
222 | val = 0; | |
223 | } | |
224 | break; | |
95819af0 BS |
225 | case 0x2000 ... 0x202f: /* PCI control */ |
226 | val = s->pci_control[(addr & 0x3f) >> 2]; | |
227 | break; | |
228 | case 0xf020 ... 0xf027: /* Reset control */ | |
229 | if (addr & 4) { | |
230 | val = s->reset_control; | |
231 | } else { | |
232 | val = 0; | |
233 | } | |
234 | break; | |
235 | case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ | |
236 | case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ | |
237 | case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ | |
238 | case 0xf000 ... 0xf01f: /* FFB config, memory control */ | |
239 | /* we don't care */ | |
502a5395 | 240 | default: |
f930d07e BS |
241 | val = 0; |
242 | break; | |
502a5395 | 243 | } |
bfec08b5 | 244 | trace_sabre_config_read(addr, val); |
95819af0 | 245 | |
502a5395 PB |
246 | return val; |
247 | } | |
248 | ||
fe984c7d MCA |
249 | static const MemoryRegionOps sabre_config_ops = { |
250 | .read = sabre_config_read, | |
251 | .write = sabre_config_write, | |
b2f9005a | 252 | .endianness = DEVICE_BIG_ENDIAN, |
502a5395 PB |
253 | }; |
254 | ||
fe984c7d MCA |
255 | static void sabre_pci_config_write(void *opaque, hwaddr addr, |
256 | uint64_t val, unsigned size) | |
5a5d4a76 | 257 | { |
b14dcaf4 | 258 | SabreState *s = opaque; |
2b8fbcd8 | 259 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
63e6f31d | 260 | |
bfec08b5 | 261 | trace_sabre_pci_config_write(addr, val); |
2b8fbcd8 | 262 | pci_data_write(phb->bus, addr, val, size); |
5a5d4a76 BS |
263 | } |
264 | ||
fe984c7d MCA |
265 | static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr, |
266 | unsigned size) | |
5a5d4a76 BS |
267 | { |
268 | uint32_t ret; | |
b14dcaf4 | 269 | SabreState *s = opaque; |
2b8fbcd8 | 270 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
5a5d4a76 | 271 | |
2b8fbcd8 | 272 | ret = pci_data_read(phb->bus, addr, size); |
bfec08b5 | 273 | trace_sabre_pci_config_read(addr, ret); |
5a5d4a76 BS |
274 | return ret; |
275 | } | |
276 | ||
fe984c7d MCA |
277 | /* The sabre host has an IRQ line for each IRQ line of each slot. */ |
278 | static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) | |
502a5395 | 279 | { |
6864fa38 MCA |
280 | /* Return the irq as swizzled by the PBM */ |
281 | return irq_num; | |
80b3ada7 PB |
282 | } |
283 | ||
90302ada | 284 | static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num) |
80b3ada7 | 285 | { |
d9e4d682 MCA |
286 | /* The on-board devices have fixed (legacy) OBIO intnos */ |
287 | switch (PCI_SLOT(pci_dev->devfn)) { | |
288 | case 1: | |
289 | /* Onboard NIC */ | |
a5546222 | 290 | return OBIO_NIC_IRQ; |
d9e4d682 MCA |
291 | case 3: |
292 | /* Onboard IDE */ | |
a5546222 | 293 | return OBIO_HDD_IRQ; |
d9e4d682 MCA |
294 | default: |
295 | /* Normal intno, fall through */ | |
296 | break; | |
6864fa38 | 297 | } |
6864fa38 | 298 | |
d9e4d682 MCA |
299 | return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; |
300 | } | |
6864fa38 | 301 | |
90302ada | 302 | static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num) |
d9e4d682 MCA |
303 | { |
304 | return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; | |
d2b59317 PB |
305 | } |
306 | ||
fe984c7d | 307 | static void pci_sabre_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 308 | { |
b14dcaf4 | 309 | SabreState *s = opaque; |
5d4e84c8 | 310 | |
bfec08b5 MCA |
311 | trace_sabre_pci_set_irq(irq_num, level); |
312 | ||
80b3ada7 | 313 | /* PCI IRQ map onto the first 32 INO. */ |
95819af0 | 314 | if (irq_num < 32) { |
9625036d AT |
315 | if (level) { |
316 | s->pci_irq_in |= 1ULL << irq_num; | |
317 | if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { | |
fe984c7d | 318 | sabre_set_request(s, irq_num); |
9625036d | 319 | } |
361dea40 | 320 | } else { |
9625036d | 321 | s->pci_irq_in &= ~(1ULL << irq_num); |
361dea40 BS |
322 | } |
323 | } else { | |
9625036d AT |
324 | /* OBIO IRQ map onto the next 32 INO. */ |
325 | if (level) { | |
bfec08b5 | 326 | trace_sabre_pci_set_obio_irq(irq_num, level); |
9625036d AT |
327 | s->pci_irq_in |= 1ULL << irq_num; |
328 | if ((s->irq_request == NO_IRQ_REQUEST) | |
329 | && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { | |
fe984c7d | 330 | sabre_set_request(s, irq_num); |
9625036d | 331 | } |
95819af0 | 332 | } else { |
9625036d | 333 | s->pci_irq_in &= ~(1ULL << irq_num); |
95819af0 BS |
334 | } |
335 | } | |
502a5395 PB |
336 | } |
337 | ||
fe984c7d | 338 | static void sabre_reset(DeviceState *d) |
72f44c8c | 339 | { |
b14dcaf4 | 340 | SabreState *s = SABRE_DEVICE(d); |
33c5eb02 MCA |
341 | PCIDevice *pci_dev; |
342 | unsigned int i; | |
343 | uint16_t cmd; | |
72f44c8c | 344 | |
95819af0 BS |
345 | for (i = 0; i < 8; i++) { |
346 | s->pci_irq_map[i] &= PBM_PCI_IMR_MASK; | |
347 | } | |
d1d80055 AT |
348 | for (i = 0; i < 32; i++) { |
349 | s->obio_irq_map[i] &= PBM_PCI_IMR_MASK; | |
350 | } | |
95819af0 | 351 | |
9625036d AT |
352 | s->irq_request = NO_IRQ_REQUEST; |
353 | s->pci_irq_in = 0ULL; | |
354 | ||
9c0afd0e | 355 | if (s->nr_resets++ == 0) { |
95819af0 BS |
356 | /* Power on reset */ |
357 | s->reset_control = POR; | |
358 | } | |
33c5eb02 MCA |
359 | |
360 | /* As this is the busA PCI bridge which contains the on-board devices | |
361 | * attached to the ebus, ensure that we initially allow IO transactions | |
362 | * so that we get the early serial console until OpenBIOS can properly | |
363 | * configure the PCI bridge itself */ | |
364 | pci_dev = PCI_DEVICE(s->bridgeA); | |
365 | cmd = pci_get_word(pci_dev->config + PCI_COMMAND); | |
366 | pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO); | |
367 | pci_bridge_update_mappings(PCI_BRIDGE(pci_dev)); | |
95819af0 BS |
368 | } |
369 | ||
3812ed0b | 370 | static const MemoryRegionOps pci_config_ops = { |
fe984c7d MCA |
371 | .read = sabre_pci_config_read, |
372 | .write = sabre_pci_config_write, | |
b2f9005a | 373 | .endianness = DEVICE_LITTLE_ENDIAN, |
3812ed0b AK |
374 | }; |
375 | ||
fe984c7d | 376 | static void sabre_realize(DeviceState *dev, Error **errp) |
95819af0 | 377 | { |
b14dcaf4 | 378 | SabreState *s = SABRE_DEVICE(dev); |
cacd0580 MCA |
379 | PCIHostState *phb = PCI_HOST_BRIDGE(dev); |
380 | SysBusDevice *sbd = SYS_BUS_DEVICE(s); | |
68f79994 | 381 | PCIDevice *pci_dev; |
502a5395 | 382 | |
9b301794 | 383 | /* sabre_config */ |
cacd0580 | 384 | sysbus_mmio_map(sbd, 0, s->special_base); |
d63baf92 | 385 | /* PCI configuration space */ |
cacd0580 | 386 | sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL); |
72f44c8c | 387 | /* pci_ioport */ |
cacd0580 | 388 | sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL); |
d63baf92 | 389 | |
cacd0580 MCA |
390 | memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); |
391 | memory_region_add_subregion(get_system_memory(), s->mem_base, | |
392 | &s->pci_mmio); | |
393 | ||
acc95bc8 | 394 | phb->bus = pci_register_root_bus(dev, "pci", |
fe984c7d | 395 | pci_sabre_set_irq, pci_sabre_map_irq, s, |
acc95bc8 MT |
396 | &s->pci_mmio, |
397 | &s->pci_ioport, | |
398 | 0, 32, TYPE_PCI_BUS); | |
f69539b1 | 399 | |
8fb28035 | 400 | pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); |
d63baf92 | 401 | |
fe984c7d | 402 | /* IOMMU */ |
9b301794 | 403 | memory_region_add_subregion_overlap(&s->sabre_config, 0x200, |
aea5b071 | 404 | sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1); |
fe984c7d | 405 | pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu); |
ae74bbe7 | 406 | |
72f44c8c | 407 | /* APB secondary busses */ |
2b8fbcd8 | 408 | pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, |
90302ada | 409 | TYPE_SIMBA_PCI_BRIDGE); |
cacd0580 | 410 | s->bridgeB = PCI_BRIDGE(pci_dev); |
90302ada | 411 | pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq); |
68f79994 | 412 | qdev_init_nofail(&pci_dev->qdev); |
68f79994 | 413 | |
2b8fbcd8 | 414 | pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, |
90302ada | 415 | TYPE_SIMBA_PCI_BRIDGE); |
cacd0580 | 416 | s->bridgeA = PCI_BRIDGE(pci_dev); |
90302ada | 417 | pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq); |
68f79994 | 418 | qdev_init_nofail(&pci_dev->qdev); |
95819af0 BS |
419 | } |
420 | ||
fe984c7d | 421 | static void sabre_init(Object *obj) |
95819af0 | 422 | { |
b14dcaf4 | 423 | SabreState *s = SABRE_DEVICE(obj); |
cacd0580 | 424 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
95819af0 | 425 | unsigned int i; |
72f44c8c | 426 | |
95819af0 BS |
427 | for (i = 0; i < 8; i++) { |
428 | s->pci_irq_map[i] = (0x1f << 6) | (i << 2); | |
429 | } | |
de739df8 MCA |
430 | for (i = 0; i < 2; i++) { |
431 | s->pci_err_irq_map[i] = (0x1f << 6) | 0x30; | |
432 | } | |
d1d80055 AT |
433 | for (i = 0; i < 32; i++) { |
434 | s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i; | |
435 | } | |
fe984c7d | 436 | qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC); |
2a4d6af5 | 437 | qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC); |
9625036d AT |
438 | s->irq_request = NO_IRQ_REQUEST; |
439 | s->pci_irq_in = 0ULL; | |
95819af0 | 440 | |
aea5b071 MCA |
441 | /* IOMMU */ |
442 | object_property_add_link(obj, "iommu", TYPE_SUN4U_IOMMU, | |
443 | (Object **) &s->iommu, | |
444 | qdev_prop_allow_set_link_before_realize, | |
d2623129 | 445 | 0); |
aea5b071 | 446 | |
9b301794 MCA |
447 | /* sabre_config */ |
448 | memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s, | |
449 | "sabre-config", 0x10000); | |
d63baf92 | 450 | /* at region 0 */ |
9b301794 | 451 | sysbus_init_mmio(sbd, &s->sabre_config); |
d63baf92 | 452 | |
40c5dce9 | 453 | memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, |
9b301794 | 454 | "sabre-pci-config", 0x1000000); |
d63baf92 | 455 | /* at region 1 */ |
b26f4419 | 456 | sysbus_init_mmio(sbd, &s->pci_config); |
d63baf92 IK |
457 | |
458 | /* pci_ioport */ | |
9b301794 MCA |
459 | memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport", |
460 | 0x1000000); | |
6864fa38 | 461 | |
d63baf92 | 462 | /* at region 2 */ |
b26f4419 | 463 | sysbus_init_mmio(sbd, &s->pci_ioport); |
72f44c8c | 464 | } |
502a5395 | 465 | |
5560c58a | 466 | static void sabre_pci_realize(PCIDevice *d, Error **errp) |
72f44c8c | 467 | { |
9fe52c7f BS |
468 | pci_set_word(d->config + PCI_COMMAND, |
469 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
470 | pci_set_word(d->config + PCI_STATUS, | |
471 | PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | | |
472 | PCI_STATUS_DEVSEL_MEDIUM); | |
72f44c8c | 473 | } |
80b3ada7 | 474 | |
5560c58a | 475 | static void sabre_pci_class_init(ObjectClass *klass, void *data) |
40021f08 AL |
476 | { |
477 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 478 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 479 | |
5560c58a | 480 | k->realize = sabre_pci_realize; |
40021f08 AL |
481 | k->vendor_id = PCI_VENDOR_ID_SUN; |
482 | k->device_id = PCI_DEVICE_ID_SUN_SABRE; | |
483 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
484 | /* |
485 | * PCI-facing part of the host bridge, not usable without the | |
486 | * host-facing part, which can't be device_add'ed, yet. | |
487 | */ | |
e90f2a8c | 488 | dc->user_creatable = false; |
40021f08 AL |
489 | } |
490 | ||
5560c58a | 491 | static const TypeInfo sabre_pci_info = { |
8fb28035 | 492 | .name = TYPE_SABRE_PCI_DEVICE, |
39bffca2 | 493 | .parent = TYPE_PCI_DEVICE, |
8fb28035 | 494 | .instance_size = sizeof(SabrePCIState), |
5560c58a | 495 | .class_init = sabre_pci_class_init, |
fd3b02c8 EH |
496 | .interfaces = (InterfaceInfo[]) { |
497 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
498 | { }, | |
499 | }, | |
72f44c8c BS |
500 | }; |
501 | ||
09af820e MCA |
502 | static char *sabre_ofw_unit_address(const SysBusDevice *dev) |
503 | { | |
504 | SabreState *s = SABRE_DEVICE(dev); | |
505 | ||
506 | return g_strdup_printf("%x,%x", | |
507 | (uint32_t)((s->special_base >> 32) & 0xffffffff), | |
508 | (uint32_t)(s->special_base & 0xffffffff)); | |
509 | } | |
510 | ||
fe984c7d | 511 | static Property sabre_properties[] = { |
b14dcaf4 MCA |
512 | DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0), |
513 | DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0), | |
cacd0580 MCA |
514 | DEFINE_PROP_END_OF_LIST(), |
515 | }; | |
516 | ||
fe984c7d | 517 | static void sabre_class_init(ObjectClass *klass, void *data) |
999e12bb | 518 | { |
39bffca2 | 519 | DeviceClass *dc = DEVICE_CLASS(klass); |
09af820e | 520 | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
999e12bb | 521 | |
fe984c7d MCA |
522 | dc->realize = sabre_realize; |
523 | dc->reset = sabre_reset; | |
4f67d30b | 524 | device_class_set_props(dc, sabre_properties); |
b26f4419 | 525 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
09af820e MCA |
526 | dc->fw_name = "pci"; |
527 | sbc->explicit_ofw_unit_address = sabre_ofw_unit_address; | |
999e12bb AL |
528 | } |
529 | ||
fe984c7d | 530 | static const TypeInfo sabre_info = { |
b14dcaf4 | 531 | .name = TYPE_SABRE, |
2b8fbcd8 | 532 | .parent = TYPE_PCI_HOST_BRIDGE, |
b14dcaf4 | 533 | .instance_size = sizeof(SabreState), |
fe984c7d MCA |
534 | .instance_init = sabre_init, |
535 | .class_init = sabre_class_init, | |
95819af0 | 536 | }; |
68f79994 | 537 | |
fe984c7d | 538 | static void sabre_register_types(void) |
72f44c8c | 539 | { |
fe984c7d | 540 | type_register_static(&sabre_info); |
5560c58a | 541 | type_register_static(&sabre_pci_info); |
502a5395 | 542 | } |
72f44c8c | 543 | |
fe984c7d | 544 | type_init(sabre_register_types) |