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1db09b84 1/*
b3305981 2 * QEMU PowerPC e500-based platforms
1db09b84
AJ
3 *
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author: Yu Liu, <yu.liu@freescale.com>
7 *
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
10 *
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
0d75590d 17#include "qemu/osdep.h"
a8d25326 18#include "qemu-common.h"
ab3dd749 19#include "qemu/units.h"
da34e65c 20#include "qapi/error.h"
e6eaabeb 21#include "e500.h"
3eddc1be 22#include "e500-ccsr.h"
1422e32d 23#include "net/net.h"
1de7afc9 24#include "qemu/config-file.h"
0d09e41a 25#include "hw/char/serial.h"
a2cb15b0 26#include "hw/pci/pci.h"
4a18e7c9 27#include "hw/boards.h"
9c17d615
PB
28#include "sysemu/sysemu.h"
29#include "sysemu/kvm.h"
71e8a915 30#include "sysemu/reset.h"
54d31236 31#include "sysemu/runstate.h"
1db09b84 32#include "kvm_ppc.h"
9c17d615 33#include "sysemu/device_tree.h"
0d09e41a 34#include "hw/ppc/openpic.h"
8d085cf0 35#include "hw/ppc/openpic_kvm.h"
0d09e41a 36#include "hw/ppc/ppc.h"
a27bd6c7 37#include "hw/qdev-properties.h"
4a18e7c9 38#include "hw/loader.h"
ca20cf32 39#include "elf.h"
4a18e7c9 40#include "hw/sysbus.h"
022c62cb 41#include "exec/address-spaces.h"
1de7afc9 42#include "qemu/host-utils.h"
922a01a0 43#include "qemu/option.h"
0d09e41a 44#include "hw/pci-host/ppce500.h"
f7087343
AG
45#include "qemu/error-report.h"
46#include "hw/platform-bus.h"
fdfb7f2c 47#include "hw/net/fsl_etsec/etsec.h"
7abb479c 48#include "hw/i2c/i2c.h"
64552b6b 49#include "hw/irq.h"
1db09b84 50
cefd3cdb 51#define EPAPR_MAGIC (0x45504150)
1db09b84 52#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
9dd5eba1 53#define DTC_LOAD_PAD 0x1800000
75bb6589 54#define DTC_PAD_MASK 0xFFFFF
ab3dd749 55#define DTB_MAX_SIZE (8 * MiB)
75bb6589
LY
56#define INITRD_LOAD_PAD 0x2000000
57#define INITRD_PAD_MASK 0xFFFFFF
1db09b84 58
ab3dd749 59#define RAM_SIZES_ALIGN (64 * MiB)
1db09b84 60
b3305981 61/* TODO: parameterize */
ed2bc496 62#define MPC8544_CCSRBAR_SIZE 0x00100000ULL
dffb1dc2 63#define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
a911b7a9 64#define MPC8544_MSI_REGS_OFFSET 0x41600ULL
dffb1dc2
BB
65#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
66#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
67#define MPC8544_PCI_REGS_OFFSET 0x8000ULL
ed2bc496 68#define MPC8544_PCI_REGS_SIZE 0x1000ULL
dffb1dc2 69#define MPC8544_UTIL_OFFSET 0xe0000ULL
b88e77f4 70#define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
7abb479c 71#define MPC8544_I2C_REGS_OFFSET 0x3000ULL
82e345f5 72#define MPC8XXX_GPIO_IRQ 47
7abb479c
AR
73#define MPC8544_I2C_IRQ 43
74#define RTC_REGS_OFFSET 0x68
1db09b84 75
3b989d49
AG
76struct boot_info
77{
78 uint32_t dt_base;
cba2026a 79 uint32_t dt_size;
3b989d49
AG
80 uint32_t entry;
81};
82
347dd79d
AG
83static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
84 int nr_slots, int *len)
0dbc0798 85{
347dd79d
AG
86 int i = 0;
87 int slot;
88 int pci_irq;
9e2c1298 89 int host_irq;
347dd79d
AG
90 int last_slot = first_slot + nr_slots;
91 uint32_t *pci_map;
92
93 *len = nr_slots * 4 * 7 * sizeof(uint32_t);
94 pci_map = g_malloc(*len);
95
96 for (slot = first_slot; slot < last_slot; slot++) {
97 for (pci_irq = 0; pci_irq < 4; pci_irq++) {
98 pci_map[i++] = cpu_to_be32(slot << 11);
99 pci_map[i++] = cpu_to_be32(0x0);
100 pci_map[i++] = cpu_to_be32(0x0);
101 pci_map[i++] = cpu_to_be32(pci_irq + 1);
102 pci_map[i++] = cpu_to_be32(mpic);
9e2c1298
AG
103 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
104 pci_map[i++] = cpu_to_be32(host_irq + 1);
347dd79d
AG
105 pci_map[i++] = cpu_to_be32(0x1);
106 }
0dbc0798 107 }
347dd79d
AG
108
109 assert((i * sizeof(uint32_t)) == *len);
110
111 return pci_map;
0dbc0798
AG
112}
113
a053a7ce
AG
114static void dt_serial_create(void *fdt, unsigned long long offset,
115 const char *soc, const char *mpic,
116 const char *alias, int idx, bool defcon)
117{
2fb513d3 118 char *ser;
a053a7ce 119
2fb513d3 120 ser = g_strdup_printf("%s/serial@%llx", soc, offset);
5a4348d1
PC
121 qemu_fdt_add_subnode(fdt, ser);
122 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial");
123 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
124 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
125 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
126 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0);
127 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
128 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
129 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
a053a7ce
AG
130
131 if (defcon) {
90ee4e01
ND
132 /*
133 * "linux,stdout-path" and "stdout" properties are deprecated by linux
134 * kernel. New platforms should only use the "stdout-path" property. Set
135 * the new property and continue using older property to remain
136 * compatible with the existing firmware.
137 */
5a4348d1 138 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
90ee4e01 139 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser);
a053a7ce 140 }
2fb513d3 141 g_free(ser);
a053a7ce
AG
142}
143
b88e77f4
AG
144static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic)
145{
146 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET;
147 int irq0 = MPC8XXX_GPIO_IRQ;
148 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0);
016f7758
AG
149 gchar *poweroff = g_strdup_printf("%s/power-off", soc);
150 int gpio_ph;
b88e77f4
AG
151
152 qemu_fdt_add_subnode(fdt, node);
153 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio");
154 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000);
155 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2);
156 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
157 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2);
158 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0);
016f7758
AG
159 gpio_ph = qemu_fdt_alloc_phandle(fdt);
160 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph);
161 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph);
162
163 /* Power Off Pin */
164 qemu_fdt_add_subnode(fdt, poweroff);
165 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff");
166 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0);
b88e77f4
AG
167
168 g_free(node);
016f7758 169 g_free(poweroff);
b88e77f4
AG
170}
171
7abb479c
AR
172static void dt_rtc_create(void *fdt, const char *i2c, const char *alias)
173{
174 int offset = RTC_REGS_OFFSET;
175
176 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset);
177 qemu_fdt_add_subnode(fdt, rtc);
178 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338");
179 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset);
180 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc);
181
182 g_free(rtc);
183}
184
185static void dt_i2c_create(void *fdt, const char *soc, const char *mpic,
186 const char *alias)
187{
188 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET;
189 int irq0 = MPC8544_I2C_IRQ;
190
191 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0);
192 qemu_fdt_add_subnode(fdt, i2c);
193 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c");
194 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c");
195 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14);
196 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0);
197 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2);
198 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic);
199 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c);
200
201 g_free(i2c);
202}
203
204
f7087343
AG
205typedef struct PlatformDevtreeData {
206 void *fdt;
207 const char *mpic;
208 int irq_start;
209 const char *node;
210 PlatformBusDevice *pbus;
211} PlatformDevtreeData;
212
fdfb7f2c
AG
213static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data)
214{
215 eTSEC *etsec = ETSEC_COMMON(sbdev);
216 PlatformBusDevice *pbus = data->pbus;
217 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0);
218 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0);
219 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1);
220 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2);
221 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0);
222 gchar *group = g_strdup_printf("%s/queue-group", node);
223 void *fdt = data->fdt;
224
225 assert((int64_t)mmio0 >= 0);
226 assert(irq0 >= 0);
227 assert(irq1 >= 0);
228 assert(irq2 >= 0);
229
230 qemu_fdt_add_subnode(fdt, node);
231 qemu_fdt_setprop_string(fdt, node, "device_type", "network");
232 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2");
233 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC");
234 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6);
235 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0);
236
237 qemu_fdt_add_subnode(fdt, group);
238 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000);
239 qemu_fdt_setprop_cells(fdt, group, "interrupts",
240 data->irq_start + irq0, 0x2,
241 data->irq_start + irq1, 0x2,
242 data->irq_start + irq2, 0x2);
243
244 g_free(node);
245 g_free(group);
246
247 return 0;
248}
249
4f01a637 250static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque)
f7087343
AG
251{
252 PlatformDevtreeData *data = opaque;
253 bool matched = false;
254
fdfb7f2c
AG
255 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) {
256 create_devtree_etsec(sbdev, data);
257 matched = true;
258 }
259
f7087343
AG
260 if (!matched) {
261 error_report("Device %s is not supported by this machine yet.",
262 qdev_fw_name(DEVICE(sbdev)));
263 exit(1);
264 }
f7087343
AG
265}
266
a3fc8396 267static void platform_bus_create_devtree(PPCE500MachineState *pms,
03f04809 268 void *fdt, const char *mpic)
f7087343 269{
a3fc8396 270 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
03f04809 271 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base);
f7087343 272 const char platcomp[] = "qemu,platform\0simple-bus";
03f04809
IM
273 uint64_t addr = pmc->platform_bus_base;
274 uint64_t size = pmc->platform_bus_size;
275 int irq_start = pmc->platform_bus_first_irq;
f7087343
AG
276
277 /* Create a /platform node that we can put all devices into */
278
279 qemu_fdt_add_subnode(fdt, node);
280 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp));
281
282 /* Our platform bus region is less than 32bit big, so 1 cell is enough for
283 address and size */
284 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
285 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
286 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size);
287
288 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
289
a3fc8396
IM
290 /* Create dt nodes for dynamic devices */
291 PlatformDevtreeData data = {
292 .fdt = fdt,
293 .mpic = mpic,
294 .irq_start = irq_start,
295 .node = node,
296 .pbus = pms->pbus_dev,
297 };
f7087343 298
a3fc8396
IM
299 /* Loop through all dynamic sysbus devices and create nodes for them */
300 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
f7087343
AG
301
302 g_free(node);
303}
304
03f04809 305static int ppce500_load_device_tree(PPCE500MachineState *pms,
a8170e5e
AK
306 hwaddr addr,
307 hwaddr initrd_base,
28290f37 308 hwaddr initrd_size,
903585de
AG
309 hwaddr kernel_base,
310 hwaddr kernel_size,
28290f37 311 bool dry_run)
1db09b84 312{
03f04809 313 MachineState *machine = MACHINE(pms);
fe6b6346 314 unsigned int smp_cpus = machine->smp.cpus;
03f04809 315 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
28290f37 316 CPUPPCState *env = first_cpu->env_ptr;
dbf916d8 317 int ret = -1;
3ef96221 318 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
7ec632b4 319 int fdt_size;
dbf916d8 320 void *fdt;
5de6b46d 321 uint8_t hypercall[16];
911d6e7a
AG
322 uint32_t clock_freq = 400000000;
323 uint32_t tb_freq = 400000000;
621d05e3 324 int i;
ebb9518a 325 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
2fb513d3
GK
326 char *soc;
327 char *mpic;
19ac9dea 328 uint32_t mpic_ph;
a911b7a9 329 uint32_t msi_ph;
2fb513d3
GK
330 char *gutil;
331 char *pci;
332 char *msi;
347dd79d
AG
333 uint32_t *pci_map = NULL;
334 int len;
3627757e
AG
335 uint32_t pci_ranges[14] =
336 {
03f04809
IM
337 0x2000000, 0x0, pmc->pci_mmio_bus_base,
338 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base,
3627757e
AG
339 0x0, 0x20000000,
340
341 0x1000000, 0x0, 0x0,
03f04809 342 pmc->pci_pio_base >> 32, pmc->pci_pio_base,
3627757e
AG
343 0x0, 0x10000,
344 };
2ff3de68
MA
345 QemuOpts *machine_opts = qemu_get_machine_opts();
346 const char *dtb_file = qemu_opt_get(machine_opts, "dtb");
347 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
d1b93565
AG
348
349 if (dtb_file) {
350 char *filename;
351 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
352 if (!filename) {
353 goto out;
354 }
355
356 fdt = load_device_tree(filename, &fdt_size);
2343dd11 357 g_free(filename);
d1b93565
AG
358 if (!fdt) {
359 goto out;
360 }
361 goto done;
362 }
1db09b84 363
2636fcb6 364 fdt = create_device_tree(&fdt_size);
5cea8590
PB
365 if (fdt == NULL) {
366 goto out;
367 }
1db09b84
AJ
368
369 /* Manipulate device tree in memory. */
5a4348d1
PC
370 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);
371 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);
51b852b7 372
5a4348d1
PC
373 qemu_fdt_add_subnode(fdt, "/memory");
374 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
375 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
376 sizeof(mem_reg_property));
1db09b84 377
5a4348d1 378 qemu_fdt_add_subnode(fdt, "/chosen");
3b989d49 379 if (initrd_size) {
5a4348d1
PC
380 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
381 initrd_base);
3b989d49
AG
382 if (ret < 0) {
383 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
384 }
1db09b84 385
5a4348d1
PC
386 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
387 (initrd_base + initrd_size));
3b989d49
AG
388 if (ret < 0) {
389 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
390 }
903585de
AG
391
392 }
393
394 if (kernel_base != -1ULL) {
395 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",
396 kernel_base >> 32, kernel_base,
397 kernel_size >> 32, kernel_size);
3b989d49 398 }
1db09b84 399
5a4348d1 400 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
3ef96221 401 machine->kernel_cmdline);
1db09b84
AJ
402 if (ret < 0)
403 fprintf(stderr, "couldn't set /chosen/bootargs\n");
404
405 if (kvm_enabled()) {
911d6e7a
AG
406 /* Read out host's frequencies */
407 clock_freq = kvmppc_get_clockfreq();
408 tb_freq = kvmppc_get_tbfreq();
5de6b46d
AG
409
410 /* indicate KVM hypercall interface */
5a4348d1
PC
411 qemu_fdt_add_subnode(fdt, "/hypervisor");
412 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",
413 "linux,kvm");
5de6b46d 414 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
5a4348d1
PC
415 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",
416 hypercall, sizeof(hypercall));
1a61a9ae
SY
417 /* if KVM supports the idle hcall, set property indicating this */
418 if (kvmppc_get_hasidle(env)) {
5a4348d1 419 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
1a61a9ae 420 }
1db09b84 421 }
3b989d49 422
625e665b 423 /* Create CPU nodes */
5a4348d1
PC
424 qemu_fdt_add_subnode(fdt, "/cpus");
425 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
426 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
625e665b 427
1e3debf0
AG
428 /* We need to generate the cpu nodes in reverse order, so Linux can pick
429 the first node as boot node and be happy */
430 for (i = smp_cpus - 1; i >= 0; i--) {
440c8152 431 CPUState *cpu;
2fb513d3 432 char *cpu_name;
03f04809 433 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20);
10f25a46 434
440c8152 435 cpu = qemu_get_cpu(i);
55e5c285 436 if (cpu == NULL) {
1e3debf0
AG
437 continue;
438 }
440c8152 439 env = cpu->env_ptr;
1e3debf0 440
2fb513d3 441 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i);
5a4348d1
PC
442 qemu_fdt_add_subnode(fdt, cpu_name);
443 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
444 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
445 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
6d536570 446 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i);
5a4348d1
PC
447 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
448 env->dcache_line_size);
449 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
450 env->icache_line_size);
451 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
452 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
453 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
55e5c285 454 if (cpu->cpu_index) {
5a4348d1
PC
455 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
456 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
457 "spin-table");
458 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",
459 cpu_release_addr);
1e3debf0 460 } else {
5a4348d1 461 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
1e3debf0 462 }
2fb513d3 463 g_free(cpu_name);
1db09b84
AJ
464 }
465
5a4348d1 466 qemu_fdt_add_subnode(fdt, "/aliases");
5da96624 467 /* XXX These should go into their respective devices' code */
2fb513d3 468 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base);
5a4348d1
PC
469 qemu_fdt_add_subnode(fdt, soc);
470 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
471 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
472 sizeof(compatible_sb));
473 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
474 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
475 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
03f04809 476 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base,
5a4348d1 477 MPC8544_CCSRBAR_SIZE);
5da96624 478 /* XXX should contain a reasonable value */
5a4348d1 479 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
5da96624 480
2fb513d3 481 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
5a4348d1
PC
482 qemu_fdt_add_subnode(fdt, mpic);
483 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");
484 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
485 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
486 0x40000);
487 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);
488 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
489 mpic_ph = qemu_fdt_alloc_phandle(fdt);
490 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);
491 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
492 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
19ac9dea 493
0cfc6e8d
AG
494 /*
495 * We have to generate ser1 first, because Linux takes the first
496 * device it finds in the dt as serial output device. And we generate
497 * devices in reverse order to the dt.
498 */
9bca0edb 499 if (serial_hd(1)) {
79c0ff2c
AG
500 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
501 soc, mpic, "serial1", 1, false);
502 }
503
9bca0edb 504 if (serial_hd(0)) {
79c0ff2c
AG
505 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
506 soc, mpic, "serial0", 0, true);
507 }
0cfc6e8d 508
7abb479c
AR
509 /* i2c */
510 dt_i2c_create(fdt, soc, mpic, "i2c");
511
512 dt_rtc_create(fdt, "i2c", "rtc");
513
514
2fb513d3
GK
515 gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
516 MPC8544_UTIL_OFFSET);
5a4348d1
PC
517 qemu_fdt_add_subnode(fdt, gutil);
518 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
519 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
520 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
2fb513d3 521 g_free(gutil);
f5038483 522
2fb513d3 523 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
5a4348d1
PC
524 qemu_fdt_add_subnode(fdt, msi);
525 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
526 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
527 msi_ph = qemu_fdt_alloc_phandle(fdt);
528 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
529 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
530 qemu_fdt_setprop_cells(fdt, msi, "interrupts",
a911b7a9
AG
531 0xe0, 0x0,
532 0xe1, 0x0,
533 0xe2, 0x0,
534 0xe3, 0x0,
535 0xe4, 0x0,
536 0xe5, 0x0,
537 0xe6, 0x0,
538 0xe7, 0x0);
5a4348d1
PC
539 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
540 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
2fb513d3 541 g_free(msi);
a911b7a9 542
2fb513d3
GK
543 pci = g_strdup_printf("/pci@%llx",
544 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
5a4348d1
PC
545 qemu_fdt_add_subnode(fdt, pci);
546 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
547 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
548 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");
549 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
550 0x0, 0x7);
551 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
03f04809 552 pmc->pci_first_slot, pmc->pci_nr_slots,
492ec48d 553 &len);
5a4348d1
PC
554 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
555 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
556 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);
557 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);
3627757e 558 for (i = 0; i < 14; i++) {
0dbc0798
AG
559 pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
560 }
5a4348d1
PC
561 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
562 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
2eaaac1f 563 qemu_fdt_setprop_cells(fdt, pci, "reg",
03f04809
IM
564 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
565 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
2eaaac1f 566 0, 0x1000);
5a4348d1
PC
567 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
568 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
569 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
570 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
571 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
2fb513d3 572 g_free(pci);
0dbc0798 573
03f04809 574 if (pmc->has_mpc8xxx_gpio) {
b88e77f4
AG
575 create_dt_mpc8xxx_gpio(fdt, soc, mpic);
576 }
2fb513d3 577 g_free(soc);
b88e77f4 578
a3fc8396
IM
579 if (pms->pbus_dev) {
580 platform_bus_create_devtree(pms, fdt, mpic);
f7087343 581 }
2fb513d3 582 g_free(mpic);
f7087343 583
03f04809 584 pmc->fixup_devtree(fdt);
e6eaabeb
SW
585
586 if (toplevel_compat) {
5a4348d1
PC
587 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
588 strlen(toplevel_compat) + 1);
e6eaabeb
SW
589 }
590
d1b93565 591done:
28290f37 592 if (!dry_run) {
5a4348d1 593 qemu_fdt_dumpdtb(fdt, fdt_size);
28290f37 594 cpu_physical_memory_write(addr, fdt, fdt_size);
cba2026a 595 }
cba2026a 596 ret = fdt_size;
b2fb7a43 597 g_free(fdt);
7ec632b4 598
1db09b84 599out:
347dd79d 600 g_free(pci_map);
1db09b84 601
04088adb 602 return ret;
1db09b84
AJ
603}
604
28290f37 605typedef struct DeviceTreeParams {
03f04809 606 PPCE500MachineState *machine;
28290f37
AG
607 hwaddr addr;
608 hwaddr initrd_base;
609 hwaddr initrd_size;
903585de
AG
610 hwaddr kernel_base;
611 hwaddr kernel_size;
f7087343 612 Notifier notifier;
28290f37
AG
613} DeviceTreeParams;
614
615static void ppce500_reset_device_tree(void *opaque)
616{
617 DeviceTreeParams *p = opaque;
03f04809 618 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base,
903585de
AG
619 p->initrd_size, p->kernel_base, p->kernel_size,
620 false);
28290f37
AG
621}
622
f7087343
AG
623static void ppce500_init_notify(Notifier *notifier, void *data)
624{
625 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier);
626 ppce500_reset_device_tree(p);
627}
628
03f04809 629static int ppce500_prep_device_tree(PPCE500MachineState *machine,
28290f37
AG
630 hwaddr addr,
631 hwaddr initrd_base,
903585de
AG
632 hwaddr initrd_size,
633 hwaddr kernel_base,
634 hwaddr kernel_size)
28290f37
AG
635{
636 DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
3ef96221 637 p->machine = machine;
28290f37
AG
638 p->addr = addr;
639 p->initrd_base = initrd_base;
640 p->initrd_size = initrd_size;
903585de
AG
641 p->kernel_base = kernel_base;
642 p->kernel_size = kernel_size;
28290f37
AG
643
644 qemu_register_reset(ppce500_reset_device_tree, p);
f7087343
AG
645 p->notifier.notify = ppce500_init_notify;
646 qemu_add_machine_init_done_notifier(&p->notifier);
28290f37
AG
647
648 /* Issue the device tree loader once, so that we get the size of the blob */
03f04809
IM
649 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size,
650 kernel_base, kernel_size, true);
28290f37
AG
651}
652
cba2026a 653/* Create -kernel TLB entries for BookE. */
a36848ff 654hwaddr booke206_page_size_to_tlb(uint64_t size)
d1e256fe 655{
ab3dd749 656 return 63 - clz64(size / KiB);
d1e256fe
AG
657}
658
cefd3cdb 659static int booke206_initial_map_tsize(CPUPPCState *env)
3b989d49 660{
cba2026a 661 struct boot_info *bi = env->load_info;
cefd3cdb 662 hwaddr dt_end;
cba2026a
AG
663 int ps;
664
665 /* Our initial TLB entry needs to cover everything from 0 to
666 the device tree top */
667 dt_end = bi->dt_base + bi->dt_size;
668 ps = booke206_page_size_to_tlb(dt_end) + 1;
fb37c302
AG
669 if (ps & 1) {
670 /* e500v2 can only do even TLB size bits */
671 ps++;
672 }
cefd3cdb
BB
673 return ps;
674}
675
676static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
677{
678 int tsize;
679
680 tsize = booke206_initial_map_tsize(env);
681 return (1ULL << 10 << tsize);
682}
683
684static void mmubooke_create_initial_mapping(CPUPPCState *env)
685{
686 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
687 hwaddr size;
688 int ps;
689
690 ps = booke206_initial_map_tsize(env);
cba2026a 691 size = (ps << MAS1_TSIZE_SHIFT);
d1e256fe 692 tlb->mas1 = MAS1_VALID | size;
cba2026a
AG
693 tlb->mas2 = 0;
694 tlb->mas7_3 = 0;
d1e256fe 695 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
93dd5e85
SW
696
697 env->tlb_dirty = true;
3b989d49
AG
698}
699
b3305981 700static void ppce500_cpu_reset_sec(void *opaque)
5c145dac 701{
38f92da6 702 PowerPCCPU *cpu = opaque;
259186a7 703 CPUState *cs = CPU(cpu);
5c145dac 704
259186a7 705 cpu_reset(cs);
5c145dac
AG
706
707 /* Secondary CPU starts in halted state for now. Needs to change when
708 implementing non-kernel boot. */
259186a7 709 cs->halted = 1;
27103424 710 cs->exception_index = EXCP_HLT;
3b989d49
AG
711}
712
b3305981 713static void ppce500_cpu_reset(void *opaque)
3b989d49 714{
38f92da6 715 PowerPCCPU *cpu = opaque;
259186a7 716 CPUState *cs = CPU(cpu);
38f92da6 717 CPUPPCState *env = &cpu->env;
3b989d49
AG
718 struct boot_info *bi = env->load_info;
719
259186a7 720 cpu_reset(cs);
3b989d49
AG
721
722 /* Set initial guest state. */
259186a7 723 cs->halted = 0;
ab3dd749 724 env->gpr[1] = (16 * MiB) - 8;
3b989d49 725 env->gpr[3] = bi->dt_base;
cefd3cdb
BB
726 env->gpr[4] = 0;
727 env->gpr[5] = 0;
728 env->gpr[6] = EPAPR_MAGIC;
729 env->gpr[7] = mmubooke_initial_mapsize(env);
730 env->gpr[8] = 0;
731 env->gpr[9] = 0;
3b989d49 732 env->nip = bi->entry;
cba2026a 733 mmubooke_create_initial_mapping(env);
3b989d49
AG
734}
735
03f04809 736static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
2104d4f5 737 IrqLines *irqs)
82fc73b6 738{
82fc73b6
SW
739 DeviceState *dev;
740 SysBusDevice *s;
741 int i, j, k;
03f04809 742 MachineState *machine = MACHINE(pms);
fe6b6346 743 unsigned int smp_cpus = machine->smp.cpus;
03f04809 744 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
82fc73b6 745
3e80f690 746 dev = qdev_new(TYPE_OPENPIC);
d2623129 747 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev));
03f04809 748 qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
d85937e6
SW
749 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
750
82fc73b6 751 s = SYS_BUS_DEVICE(dev);
3c6ef471 752 sysbus_realize_and_unref(s, &error_fatal);
82fc73b6
SW
753
754 k = 0;
755 for (i = 0; i < smp_cpus; i++) {
756 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
2104d4f5 757 sysbus_connect_irq(s, k++, irqs[i].irq[j]);
82fc73b6
SW
758 }
759 }
760
d85937e6
SW
761 return dev;
762}
763
03f04809 764static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
2104d4f5 765 IrqLines *irqs, Error **errp)
d85937e6
SW
766{
767 DeviceState *dev;
d85937e6 768 CPUState *cs;
d85937e6 769
3e80f690 770 dev = qdev_new(TYPE_KVM_OPENPIC);
03f04809 771 qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
d85937e6 772
668f62ec 773 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
fe656ebd 774 object_unparent(OBJECT(dev));
d85937e6
SW
775 return NULL;
776 }
777
bdc44640 778 CPU_FOREACH(cs) {
d85937e6
SW
779 if (kvm_openpic_connect_vcpu(dev, cs)) {
780 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
781 __func__);
782 abort();
783 }
784 }
785
786 return dev;
787}
788
03f04809 789static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms,
c91c187f 790 MemoryRegion *ccsr,
2104d4f5 791 IrqLines *irqs)
d85937e6 792{
03f04809 793 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
d85937e6
SW
794 DeviceState *dev = NULL;
795 SysBusDevice *s;
d85937e6
SW
796
797 if (kvm_enabled()) {
fe656ebd 798 Error *err = NULL;
d85937e6 799
4376c40d 800 if (kvm_kernel_irqchip_allowed()) {
03f04809 801 dev = ppce500_init_mpic_kvm(pmc, irqs, &err);
d85937e6 802 }
4376c40d 803 if (kvm_kernel_irqchip_required() && !dev) {
c29b77f9
MA
804 error_reportf_err(err,
805 "kernel_irqchip requested but unavailable: ");
fe656ebd 806 exit(1);
d85937e6
SW
807 }
808 }
809
810 if (!dev) {
03f04809 811 dev = ppce500_init_mpic_qemu(pms, irqs);
d85937e6
SW
812 }
813
d85937e6 814 s = SYS_BUS_DEVICE(dev);
82fc73b6
SW
815 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
816 s->mmio[0].memory);
817
c91c187f 818 return dev;
82fc73b6
SW
819}
820
016f7758
AG
821static void ppce500_power_off(void *opaque, int line, int on)
822{
823 if (on) {
cf83f140 824 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
016f7758
AG
825 }
826}
827
03f04809 828void ppce500_init(MachineState *machine)
1db09b84 829{
39186d8a 830 MemoryRegion *address_space_mem = get_system_memory();
03f04809
IM
831 PPCE500MachineState *pms = PPCE500_MACHINE(machine);
832 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine);
1db09b84 833 PCIBus *pci_bus;
e2684c0b 834 CPUPPCState *env = NULL;
3812c71f
AG
835 uint64_t loadaddr;
836 hwaddr kernel_base = -1LL;
837 int kernel_size = 0;
838 hwaddr dt_base = 0;
839 hwaddr initrd_base = 0;
840 int initrd_size = 0;
841 hwaddr cur_base = 0;
842 char *filename;
8d622594
DE
843 const char *payload_name;
844 bool kernel_as_payload;
3812c71f 845 hwaddr bios_entry = 0;
8d622594 846 target_long payload_size;
3812c71f
AG
847 struct boot_info *boot_info;
848 int dt_size;
82fc73b6 849 int i;
fe6b6346 850 unsigned int smp_cpus = machine->smp.cpus;
d575a6ce
BB
851 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
852 * 4 respectively */
853 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
2104d4f5 854 IrqLines *irqs;
c91c187f 855 DeviceState *dev, *mpicdev;
e2684c0b 856 CPUPPCState *firstenv = NULL;
3eddc1be 857 MemoryRegion *ccsr_addr_space;
dffb1dc2 858 SysBusDevice *s;
3eddc1be 859 PPCE500CCSRState *ccsr;
7abb479c 860 I2CBus *i2c;
1db09b84 861
2104d4f5 862 irqs = g_new0(IrqLines, smp_cpus);
e61c36d5 863 for (i = 0; i < smp_cpus; i++) {
397b457d 864 PowerPCCPU *cpu;
55e5c285 865 CPUState *cs;
e61c36d5 866 qemu_irq *input;
397b457d 867
59e816fd 868 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
397b457d 869 env = &cpu->env;
55e5c285 870 cs = CPU(cpu);
1db09b84 871
00469dc3 872 if (env->mmu_model != POWERPC_MMU_BOOKE206) {
6f76b817
AF
873 error_report("MMU model %i not supported by this machine",
874 env->mmu_model);
00469dc3
VP
875 exit(1);
876 }
877
e61c36d5
AG
878 if (!firstenv) {
879 firstenv = env;
880 }
1db09b84 881
a915249f 882 input = (qemu_irq *)env->irq_inputs;
2104d4f5
GK
883 irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
884 irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
6a450df9 885 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
03f04809 886 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
3b989d49 887
a34a92b9 888 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
e61c36d5
AG
889
890 /* Register reset handler */
5c145dac
AG
891 if (!i) {
892 /* Primary CPU */
893 struct boot_info *boot_info;
894 boot_info = g_malloc0(sizeof(struct boot_info));
b3305981 895 qemu_register_reset(ppce500_cpu_reset, cpu);
5c145dac
AG
896 env->load_info = boot_info;
897 } else {
898 /* Secondary CPUs */
b3305981 899 qemu_register_reset(ppce500_cpu_reset_sec, cpu);
5c145dac 900 }
e61c36d5 901 }
3b989d49 902
e61c36d5 903 env = firstenv;
3b989d49 904
3538e846
IM
905 if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) {
906 error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN);
907 exit(EXIT_FAILURE);
908 }
1db09b84
AJ
909
910 /* Register Memory */
97316645 911 memory_region_add_subregion(address_space_mem, 0, machine->ram);
1db09b84 912
3e80f690 913 dev = qdev_new("e500-ccsr");
3eddc1be 914 object_property_add_child(qdev_get_machine(), "e500-ccsr",
d2623129 915 OBJECT(dev));
3c6ef471 916 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
3eddc1be
BB
917 ccsr = CCSR(dev);
918 ccsr_addr_space = &ccsr->ccsr_space;
03f04809 919 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
3eddc1be 920 ccsr_addr_space);
dffb1dc2 921
03f04809 922 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs);
d0b72631 923
1db09b84 924 /* Serial */
9bca0edb 925 if (serial_hd(0)) {
3eddc1be 926 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
c91c187f 927 0, qdev_get_gpio_in(mpicdev, 42), 399193,
9bca0edb 928 serial_hd(0), DEVICE_BIG_ENDIAN);
2d48377a 929 }
1db09b84 930
9bca0edb 931 if (serial_hd(1)) {
3eddc1be 932 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
c91c187f 933 0, qdev_get_gpio_in(mpicdev, 42), 399193,
9bca0edb 934 serial_hd(1), DEVICE_BIG_ENDIAN);
2d48377a 935 }
7abb479c 936 /* I2C */
3e80f690 937 dev = qdev_new("mpc-i2c");
7abb479c 938 s = SYS_BUS_DEVICE(dev);
3c6ef471 939 sysbus_realize_and_unref(s, &error_fatal);
7abb479c
AR
940 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ));
941 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET,
942 sysbus_mmio_get_region(s, 0));
943 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
944 i2c_create_slave(i2c, "ds1338", RTC_REGS_OFFSET);
945
1db09b84 946
b0fb8423 947 /* General Utility device */
3e80f690 948 dev = qdev_new("mpc8544-guts");
dffb1dc2 949 s = SYS_BUS_DEVICE(dev);
3c6ef471 950 sysbus_realize_and_unref(s, &error_fatal);
3eddc1be 951 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
dffb1dc2 952 sysbus_mmio_get_region(s, 0));
b0fb8423 953
1db09b84 954 /* PCI */
3e80f690 955 dev = qdev_new("e500-pcihost");
d2623129 956 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev));
03f04809 957 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
3016dca0 958 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
dffb1dc2 959 s = SYS_BUS_DEVICE(dev);
3c6ef471 960 sysbus_realize_and_unref(s, &error_fatal);
d575a6ce 961 for (i = 0; i < PCI_NUM_PINS; i++) {
c91c187f 962 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
d575a6ce
BB
963 }
964
3eddc1be 965 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
dffb1dc2
BB
966 sysbus_mmio_get_region(s, 0));
967
d461e3b9 968 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
1db09b84
AJ
969 if (!pci_bus)
970 printf("couldn't create PCI controller!\n");
971
1db09b84 972 if (pci_bus) {
1db09b84
AJ
973 /* Register network interfaces. */
974 for (i = 0; i < nb_nics; i++) {
52310c3f 975 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL);
1db09b84
AJ
976 }
977 }
978
5c145dac 979 /* Register spinning region */
03f04809 980 sysbus_create_simple("e500-spin", pmc->spin_base, NULL);
5c145dac 981
03f04809 982 if (pmc->has_mpc8xxx_gpio) {
016f7758
AG
983 qemu_irq poweroff_irq;
984
3e80f690 985 dev = qdev_new("mpc8xxx_gpio");
b88e77f4 986 s = SYS_BUS_DEVICE(dev);
3c6ef471 987 sysbus_realize_and_unref(s, &error_fatal);
c91c187f 988 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
b88e77f4
AG
989 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
990 sysbus_mmio_get_region(s, 0));
016f7758
AG
991
992 /* Power Off GPIO at Pin 0 */
993 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0);
994 qdev_connect_gpio_out(dev, 0, poweroff_irq);
b88e77f4
AG
995 }
996
f7087343 997 /* Platform Bus Device */
03f04809 998 if (pmc->has_platform_bus) {
3e80f690 999 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
f7087343 1000 dev->id = TYPE_PLATFORM_BUS_DEVICE;
03f04809
IM
1001 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
1002 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
3c6ef471 1003 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
a3fc8396 1004 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
f7087343 1005
a3fc8396 1006 s = SYS_BUS_DEVICE(pms->pbus_dev);
03f04809
IM
1007 for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
1008 int irqn = pmc->platform_bus_first_irq + i;
c91c187f 1009 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
f7087343
AG
1010 }
1011
1012 memory_region_add_subregion(address_space_mem,
03f04809 1013 pmc->platform_bus_base,
f7087343
AG
1014 sysbus_mmio_get_region(s, 0));
1015 }
1016
8d622594
DE
1017 /*
1018 * Smart firmware defaults ahead!
1019 *
1020 * We follow the following table to select which payload we execute.
1021 *
1022 * -kernel | -bios | payload
1023 * ---------+-------+---------
1024 * N | Y | u-boot
1025 * N | N | u-boot
1026 * Y | Y | u-boot
1027 * Y | N | kernel
1028 *
1029 * This ensures backwards compatibility with how we used to expose
1030 * -kernel to users but allows them to run through u-boot as well.
1031 */
1032 kernel_as_payload = false;
1033 if (bios_name == NULL) {
1034 if (machine->kernel_filename) {
1035 payload_name = machine->kernel_filename;
1036 kernel_as_payload = true;
1037 } else {
1038 payload_name = "u-boot.e500";
1039 }
1040 } else {
1041 payload_name = bios_name;
1042 }
1043
1044 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name);
3b4f50bd
PM
1045 if (!filename) {
1046 error_report("could not find firmware/kernel file '%s'", payload_name);
1047 exit(1);
1048 }
8d622594 1049
4366e1db 1050 payload_size = load_elf(filename, NULL, NULL, NULL,
6cdda0ff 1051 &bios_entry, &loadaddr, NULL, NULL,
8d622594
DE
1052 1, PPC_ELF_MACHINE, 0, 0);
1053 if (payload_size < 0) {
1054 /*
1055 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
1056 * ePAPR compliant kernel
1057 */
f831f955 1058 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
8d622594
DE
1059 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL,
1060 NULL, NULL);
1061 if (payload_size < 0) {
371b74e2 1062 error_report("could not load firmware '%s'", filename);
8d622594
DE
1063 exit(1);
1064 }
1065 }
1066
1067 g_free(filename);
1068
1069 if (kernel_as_payload) {
1070 kernel_base = loadaddr;
1071 kernel_size = payload_size;
1072 }
1073
1074 cur_base = loadaddr + payload_size;
ab3dd749 1075 if (cur_base < 32 * MiB) {
b4a5f24a 1076 /* u-boot occupies memory up to 32MB, so load blobs above */
ab3dd749 1077 cur_base = 32 * MiB;
b4a5f24a 1078 }
8d622594
DE
1079
1080 /* Load bare kernel only if no bios/u-boot has been provided */
1081 if (machine->kernel_filename && !kernel_as_payload) {
3812c71f
AG
1082 kernel_base = cur_base;
1083 kernel_size = load_image_targphys(machine->kernel_filename,
1084 cur_base,
3538e846 1085 machine->ram_size - cur_base);
1db09b84 1086 if (kernel_size < 0) {
6f76b817
AF
1087 error_report("could not load kernel '%s'",
1088 machine->kernel_filename);
1db09b84
AJ
1089 exit(1);
1090 }
528e536e 1091
3812c71f 1092 cur_base += kernel_size;
1db09b84
AJ
1093 }
1094
1095 /* Load initrd. */
3ef96221 1096 if (machine->initrd_filename) {
528e536e 1097 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
3ef96221 1098 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
3538e846 1099 machine->ram_size - initrd_base);
1db09b84
AJ
1100
1101 if (initrd_size < 0) {
6f76b817
AF
1102 error_report("could not load initial ram disk '%s'",
1103 machine->initrd_filename);
1db09b84
AJ
1104 exit(1);
1105 }
528e536e
AG
1106
1107 cur_base = initrd_base + initrd_size;
1db09b84
AJ
1108 }
1109
3812c71f 1110 /*
8d622594
DE
1111 * Reserve space for dtb behind the kernel image because Linux has a bug
1112 * where it can only handle the dtb if it's within the first 64MB of where
1113 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD
1114 * ensures enough space between kernel and initrd.
3812c71f 1115 */
8d622594 1116 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
3538e846 1117 if (dt_base + DTB_MAX_SIZE > machine->ram_size) {
371b74e2 1118 error_report("not enough memory for device tree");
1db09b84 1119 exit(1);
3812c71f 1120 }
1db09b84 1121
03f04809 1122 dt_size = ppce500_prep_device_tree(pms, dt_base,
3812c71f
AG
1123 initrd_base, initrd_size,
1124 kernel_base, kernel_size);
1125 if (dt_size < 0) {
6f76b817 1126 error_report("couldn't load device tree");
3812c71f 1127 exit(1);
1db09b84 1128 }
3812c71f
AG
1129 assert(dt_size < DTB_MAX_SIZE);
1130
1131 boot_info = env->load_info;
1132 boot_info->entry = bios_entry;
1133 boot_info->dt_base = dt_base;
1134 boot_info->dt_size = dt_size;
1db09b84 1135}
3eddc1be 1136
d0c2b0d0 1137static void e500_ccsr_initfn(Object *obj)
3eddc1be 1138{
d0c2b0d0
XZ
1139 PPCE500CCSRState *ccsr = CCSR(obj);
1140 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
3eddc1be 1141 MPC8544_CCSRBAR_SIZE);
3eddc1be
BB
1142}
1143
1144static const TypeInfo e500_ccsr_info = {
1145 .name = TYPE_CCSR,
1146 .parent = TYPE_SYS_BUS_DEVICE,
1147 .instance_size = sizeof(PPCE500CCSRState),
d0c2b0d0 1148 .instance_init = e500_ccsr_initfn,
3eddc1be
BB
1149};
1150
03f04809
IM
1151static const TypeInfo ppce500_info = {
1152 .name = TYPE_PPCE500_MACHINE,
1153 .parent = TYPE_MACHINE,
1154 .abstract = true,
a3fc8396 1155 .instance_size = sizeof(PPCE500MachineState),
03f04809
IM
1156 .class_size = sizeof(PPCE500MachineClass),
1157};
1158
3eddc1be
BB
1159static void e500_register_types(void)
1160{
1161 type_register_static(&e500_ccsr_info);
03f04809 1162 type_register_static(&ppce500_info);
3eddc1be
BB
1163}
1164
1165type_init(e500_register_types)