[mirror_qemu.git] / hw / ppc / pnv_xscom.c

/*
 * QEMU PowerPC PowerNV XSCOM bus
 *
 * Copyright (c) 2016, IBM Corporation.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "sysemu/hw_accel.h"
#include "target/ppc/cpu.h"
#include "hw/sysbus.h"

#include "hw/ppc/fdt.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_xscom.h"

#include <libfdt.h>

/* PRD registers */
#define PRD_P8_IPOLL_REG_MASK           0x01020013
#define PRD_P8_IPOLL_REG_STATUS         0x01020014
#define PRD_P9_IPOLL_REG_MASK           0x000F0033
#define PRD_P9_IPOLL_REG_STATUS         0x000F0034

static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
{
    /*
     * TODO: When the read/write comes from the monitor, NULL is
     * passed for the cpu, and no CPU completion is generated.
     */
    if (cs) {
        PowerPCCPU *cpu = POWERPC_CPU(cs);
        CPUPPCState *env = &cpu->env;

        /*
         * TODO: Need a CPU helper to set HMER, also handle generation
         * of HMIs
         */
        cpu_synchronize_state(cs);
        env->spr[SPR_HMER] |= hmer_bits;
    }
}

static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
{
    addr &= (PNV_XSCOM_SIZE - 1);

    if (pnv_chip_is_power9(chip)) {
        return addr >> 3;
    } else {
        return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
    }
}

static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
{
    switch (pcba) {
    case 0xf000f:
        return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
    case 0x18002:       /* ECID2 */
        return 0;

    case 0x1010c00:     /* PIBAM FIR */
    case 0x1010c03:     /* PIBAM FIR MASK */

        /* PRD registers */
    case PRD_P8_IPOLL_REG_MASK:
    case PRD_P8_IPOLL_REG_STATUS:
    case PRD_P9_IPOLL_REG_MASK:
    case PRD_P9_IPOLL_REG_STATUS:

        /* P9 xscom reset */
    case 0x0090018:     /* Receive status reg */
    case 0x0090012:     /* log register */
    case 0x0090013:     /* error register */

        /* P8 xscom reset */
    case 0x2020007:     /* ADU stuff, log register */
    case 0x2020009:     /* ADU stuff, error register */
    case 0x202000f:     /* ADU stuff, receive status register*/
        return 0;
    case 0x2013f00:     /* PBA stuff */
    case 0x2013f01:     /* PBA stuff */
    case 0x2013f02:     /* PBA stuff */
    case 0x2013f03:     /* PBA stuff */
    case 0x2013f04:     /* PBA stuff */
    case 0x2013f05:     /* PBA stuff */
    case 0x2013f06:     /* PBA stuff */
    case 0x2013f07:     /* PBA stuff */
        return 0;
    case 0x2013028:     /* CAPP stuff */
    case 0x201302a:     /* CAPP stuff */
    case 0x2013801:     /* CAPP stuff */
    case 0x2013802:     /* CAPP stuff */
        return 0;
    default:
        return -1;
    }
}

static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
{
    /* We ignore writes to these */
    switch (pcba) {
    case 0xf000f:       /* chip id is RO */
    case 0x1010c00:     /* PIBAM FIR */
    case 0x1010c01:     /* PIBAM FIR */
    case 0x1010c02:     /* PIBAM FIR */
    case 0x1010c03:     /* PIBAM FIR MASK */
    case 0x1010c04:     /* PIBAM FIR MASK */
    case 0x1010c05:     /* PIBAM FIR MASK */
        /* P9 xscom reset */
    case 0x0090018:     /* Receive status reg */
    case 0x0090012:     /* log register */
    case 0x0090013:     /* error register */

        /* P8 xscom reset */
    case 0x2020007:     /* ADU stuff, log register */
    case 0x2020009:     /* ADU stuff, error register */
    case 0x202000f:     /* ADU stuff, receive status register*/

    case 0x2013028:     /* CAPP stuff */
    case 0x201302a:     /* CAPP stuff */
    case 0x2013801:     /* CAPP stuff */
    case 0x2013802:     /* CAPP stuff */

        /* P8 PRD registers */
    case PRD_P8_IPOLL_REG_MASK:
    case PRD_P8_IPOLL_REG_STATUS:
    case PRD_P9_IPOLL_REG_MASK:
    case PRD_P9_IPOLL_REG_STATUS:
        return true;
    default:
        return false;
    }
}

static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
{
    PnvChip *chip = opaque;
    uint32_t pcba = pnv_xscom_pcba(chip, addr);
    uint64_t val = 0;
    MemTxResult result;

    /* Handle some SCOMs here before dispatch */
    val = xscom_read_default(chip, pcba);
    if (val != -1) {
        goto complete;
    }

    val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
                            MEMTXATTRS_UNSPECIFIED, &result);
    if (result != MEMTX_OK) {
        qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
                      HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
        xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
        return 0;
    }

complete:
    xscom_complete(current_cpu, HMER_XSCOM_DONE);
    return val;
}

static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
                        unsigned width)
{
    PnvChip *chip = opaque;
    uint32_t pcba = pnv_xscom_pcba(chip, addr);
    MemTxResult result;

    /* Handle some SCOMs here before dispatch */
    if (xscom_write_default(chip, pcba, val)) {
        goto complete;
    }

    address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
                      MEMTXATTRS_UNSPECIFIED, &result);
    if (result != MEMTX_OK) {
        qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
                      HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
                      addr, pcba, val);
        xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
        return;
    }

complete:
    xscom_complete(current_cpu, HMER_XSCOM_DONE);
}

const MemoryRegionOps pnv_xscom_ops = {
    .read = xscom_read,
    .write = xscom_write,
    .valid.min_access_size = 8,
    .valid.max_access_size = 8,
    .impl.min_access_size = 8,
    .impl.max_access_size = 8,
    .endianness = DEVICE_BIG_ENDIAN,
};

void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(chip);
    char *name;

    name = g_strdup_printf("xscom-%x", chip->chip_id);
    memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
                          chip, name, size);
    sysbus_init_mmio(sbd, &chip->xscom_mmio);

    memory_region_init(&chip->xscom, OBJECT(chip), name, size);
    address_space_init(&chip->xscom_as, &chip->xscom, name);
    g_free(name);
}

static const TypeInfo pnv_xscom_interface_info = {
    .name = TYPE_PNV_XSCOM_INTERFACE,
    .parent = TYPE_INTERFACE,
    .class_size = sizeof(PnvXScomInterfaceClass),
};

static void pnv_xscom_register_types(void)
{
    type_register_static(&pnv_xscom_interface_info);
}

type_init(pnv_xscom_register_types)

typedef struct ForeachPopulateArgs {
    void *fdt;
    int xscom_offset;
} ForeachPopulateArgs;

static int xscom_dt_child(Object *child, void *opaque)
{
    if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
        ForeachPopulateArgs *args = opaque;
        PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
        PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);

        if (xc->dt_xscom) {
            _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
        }
    }
    return 0;
}

static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";

int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
{
    uint64_t reg[2];
    int xscom_offset;
    ForeachPopulateArgs args;
    char *name;

    if (pnv_chip_is_power9(chip)) {
        reg[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip));
        reg[1] = cpu_to_be64(PNV9_XSCOM_SIZE);
    } else {
        reg[0] = cpu_to_be64(PNV_XSCOM_BASE(chip));
        reg[1] = cpu_to_be64(PNV_XSCOM_SIZE);
    }

    name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
    xscom_offset = fdt_add_subnode(fdt, root_offset, name);
    _FDT(xscom_offset);
    g_free(name);
    _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
    _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
    _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
    _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));

    if (pnv_chip_is_power9(chip)) {
        _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9,
                          sizeof(compat_p9))));
    } else {
        _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8,
                          sizeof(compat_p8))));
    }

    _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));

    args.fdt = fdt;
    args.xscom_offset = xscom_offset;

    object_child_foreach(OBJECT(chip), xscom_dt_child, &args);
    return 0;
}

void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr)
{
    memory_region_add_subregion(&chip->xscom, offset << 3, mr);
}

void pnv_xscom_region_init(MemoryRegion *mr,
                           struct Object *owner,
                           const MemoryRegionOps *ops,
                           void *opaque,
                           const char *name,
                           uint64_t size)
{
    memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
}
Commit	Line	Data
967b7523 CLG	1	/*
	2	* QEMU PowerPC PowerNV XSCOM bus
	3	*
	4	* Copyright (c) 2016, IBM Corporation.
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
0b8fa32f	19
967b7523	20	#include "qemu/osdep.h"
967b7523 CLG	21	#include "hw/hw.h"
967b7523 CLG	22	#include "qemu/log.h"
0b8fa32f	23	#include "qemu/module.h"
b3946626	24	#include "sysemu/hw_accel.h"
fcf5ef2a	25	#include "target/ppc/cpu.h"
967b7523 CLG	26	#include "hw/sysbus.h"
	27
	28	#include "hw/ppc/fdt.h"
967b7523	29	#include "hw/ppc/pnv.h"
ec575aa0	30	#include "hw/ppc/pnv_xscom.h"
967b7523 CLG	31
	32	#include <libfdt.h>
	33
ce4b1b56 CLG	34	/* PRD registers */
	35	#define PRD_P8_IPOLL_REG_MASK 0x01020013
	36	#define PRD_P8_IPOLL_REG_STATUS 0x01020014
	37	#define PRD_P9_IPOLL_REG_MASK 0x000F0033
	38	#define PRD_P9_IPOLL_REG_STATUS 0x000F0034
	39
967b7523 CLG	40	static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
	41	{
	42	/*
	43	* TODO: When the read/write comes from the monitor, NULL is
	44	* passed for the cpu, and no CPU completion is generated.
	45	*/
	46	if (cs) {
	47	PowerPCCPU *cpu = POWERPC_CPU(cs);
	48	CPUPPCState *env = &cpu->env;
	49
	50	/*
	51	* TODO: Need a CPU helper to set HMER, also handle generation
	52	* of HMIs
	53	*/
	54	cpu_synchronize_state(cs);
	55	env->spr[SPR_HMER] \|= hmer_bits;
	56	}
	57	}
	58
	59	static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
	60	{
967b7523	61	addr &= (PNV_XSCOM_SIZE - 1);
b3b066e9 CLG	62
b3b066e9 CLG	63	if (pnv_chip_is_power9(chip)) {
967b7523 CLG	64	return addr >> 3;
	65	} else {
	66	return ((addr >> 4) & ~0xfull) \| ((addr >> 3) & 0xf);
	67	}
	68	}
	69
	70	static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
	71	{
	72	switch (pcba) {
	73	case 0xf000f:
	74	return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
bc565116 CLG	75	case 0x18002: /* ECID2 */
	76	return 0;
	77
967b7523 CLG	78	case 0x1010c00: /* PIBAM FIR */
967b7523 CLG	79	case 0x1010c03: /* PIBAM FIR MASK */
bc565116	80
ce4b1b56 CLG	81	/* PRD registers */
	82	case PRD_P8_IPOLL_REG_MASK:
	83	case PRD_P8_IPOLL_REG_STATUS:
	84	case PRD_P9_IPOLL_REG_MASK:
	85	case PRD_P9_IPOLL_REG_STATUS:
	86
bc565116 CLG	87	/* P9 xscom reset */
	88	case 0x0090018: /* Receive status reg */
	89	case 0x0090012: /* log register */
	90	case 0x0090013: /* error register */
	91
	92	/* P8 xscom reset */
	93	case 0x2020007: /* ADU stuff, log register */
	94	case 0x2020009: /* ADU stuff, error register */
	95	case 0x202000f: /* ADU stuff, receive status register*/
967b7523 CLG	96	return 0;
	97	case 0x2013f00: /* PBA stuff */
	98	case 0x2013f01: /* PBA stuff */
	99	case 0x2013f02: /* PBA stuff */
	100	case 0x2013f03: /* PBA stuff */
	101	case 0x2013f04: /* PBA stuff */
	102	case 0x2013f05: /* PBA stuff */
	103	case 0x2013f06: /* PBA stuff */
	104	case 0x2013f07: /* PBA stuff */
	105	return 0;
	106	case 0x2013028: /* CAPP stuff */
	107	case 0x201302a: /* CAPP stuff */
	108	case 0x2013801: /* CAPP stuff */
	109	case 0x2013802: /* CAPP stuff */
	110	return 0;
	111	default:
	112	return -1;
	113	}
	114	}
	115
	116	static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
	117	{
	118	/* We ignore writes to these */
	119	switch (pcba) {
	120	case 0xf000f: /* chip id is RO */
	121	case 0x1010c00: /* PIBAM FIR */
	122	case 0x1010c01: /* PIBAM FIR */
	123	case 0x1010c02: /* PIBAM FIR */
	124	case 0x1010c03: /* PIBAM FIR MASK */
	125	case 0x1010c04: /* PIBAM FIR MASK */
	126	case 0x1010c05: /* PIBAM FIR MASK */
bc565116 CLG	127	/* P9 xscom reset */
	128	case 0x0090018: /* Receive status reg */
	129	case 0x0090012: /* log register */
	130	case 0x0090013: /* error register */
	131
	132	/* P8 xscom reset */
	133	case 0x2020007: /* ADU stuff, log register */
	134	case 0x2020009: /* ADU stuff, error register */
	135	case 0x202000f: /* ADU stuff, receive status register*/
	136
	137	case 0x2013028: /* CAPP stuff */
	138	case 0x201302a: /* CAPP stuff */
	139	case 0x2013801: /* CAPP stuff */
	140	case 0x2013802: /* CAPP stuff */
ce4b1b56 CLG	141
	142	/* P8 PRD registers */
	143	case PRD_P8_IPOLL_REG_MASK:
	144	case PRD_P8_IPOLL_REG_STATUS:
	145	case PRD_P9_IPOLL_REG_MASK:
	146	case PRD_P9_IPOLL_REG_STATUS:
967b7523 CLG	147	return true;
	148	default:
	149	return false;
	150	}
	151	}
	152
	153	static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
	154	{
	155	PnvChip *chip = opaque;
	156	uint32_t pcba = pnv_xscom_pcba(chip, addr);
	157	uint64_t val = 0;
	158	MemTxResult result;
	159
	160	/* Handle some SCOMs here before dispatch */
	161	val = xscom_read_default(chip, pcba);
	162	if (val != -1) {
	163	goto complete;
	164	}
	165
f81e5512 CLG	166	val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
f81e5512 CLG	167	MEMTXATTRS_UNSPECIFIED, &result);
967b7523 CLG	168	if (result != MEMTX_OK) {
	169	qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
	170	HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
	171	xscom_complete(current_cpu, HMER_XSCOM_FAIL \| HMER_XSCOM_DONE);
	172	return 0;
	173	}
	174
	175	complete:
	176	xscom_complete(current_cpu, HMER_XSCOM_DONE);
	177	return val;
	178	}
	179
	180	static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
	181	unsigned width)
	182	{
	183	PnvChip *chip = opaque;
	184	uint32_t pcba = pnv_xscom_pcba(chip, addr);
	185	MemTxResult result;
	186
	187	/* Handle some SCOMs here before dispatch */
	188	if (xscom_write_default(chip, pcba, val)) {
	189	goto complete;
	190	}
	191
f81e5512 CLG	192	address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
f81e5512 CLG	193	MEMTXATTRS_UNSPECIFIED, &result);
967b7523 CLG	194	if (result != MEMTX_OK) {
	195	qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
	196	HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
	197	addr, pcba, val);
	198	xscom_complete(current_cpu, HMER_XSCOM_FAIL \| HMER_XSCOM_DONE);
	199	return;
	200	}
	201
	202	complete:
	203	xscom_complete(current_cpu, HMER_XSCOM_DONE);
	204	}
	205
	206	const MemoryRegionOps pnv_xscom_ops = {
	207	.read = xscom_read,
	208	.write = xscom_write,
	209	.valid.min_access_size = 8,
	210	.valid.max_access_size = 8,
	211	.impl.min_access_size = 8,
	212	.impl.max_access_size = 8,
	213	.endianness = DEVICE_BIG_ENDIAN,
	214	};
	215
709044fd	216	void pnv_xscom_realize(PnvChip chip, uint64_t size, Error *errp)
967b7523 CLG	217	{
	218	SysBusDevice *sbd = SYS_BUS_DEVICE(chip);
	219	char *name;
	220
	221	name = g_strdup_printf("xscom-%x", chip->chip_id);
	222	memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
709044fd	223	chip, name, size);
967b7523 CLG	224	sysbus_init_mmio(sbd, &chip->xscom_mmio);
967b7523 CLG	225
709044fd	226	memory_region_init(&chip->xscom, OBJECT(chip), name, size);
967b7523 CLG	227	address_space_init(&chip->xscom_as, &chip->xscom, name);
	228	g_free(name);
	229	}
	230
	231	static const TypeInfo pnv_xscom_interface_info = {
	232	.name = TYPE_PNV_XSCOM_INTERFACE,
	233	.parent = TYPE_INTERFACE,
	234	.class_size = sizeof(PnvXScomInterfaceClass),
	235	};
	236
	237	static void pnv_xscom_register_types(void)
	238	{
	239	type_register_static(&pnv_xscom_interface_info);
	240	}
	241
	242	type_init(pnv_xscom_register_types)
	243
	244	typedef struct ForeachPopulateArgs {
	245	void *fdt;
	246	int xscom_offset;
	247	} ForeachPopulateArgs;
	248
b168a138	249	static int xscom_dt_child(Object child, void opaque)
967b7523 CLG	250	{
	251	if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
	252	ForeachPopulateArgs *args = opaque;
	253	PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
	254	PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
	255
b168a138 CLG	256	if (xc->dt_xscom) {
b168a138 CLG	257	_FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
967b7523 CLG	258	}
	259	}
	260	return 0;
	261	}
	262
	263	static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
	264	static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";
	265
b168a138	266	int pnv_dt_xscom(PnvChip chip, void fdt, int root_offset)
967b7523	267	{
709044fd	268	uint64_t reg[2];
967b7523 CLG	269	int xscom_offset;
	270	ForeachPopulateArgs args;
	271	char *name;
967b7523	272
709044fd CLG	273	if (pnv_chip_is_power9(chip)) {
	274	reg[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip));
	275	reg[1] = cpu_to_be64(PNV9_XSCOM_SIZE);
	276	} else {
	277	reg[0] = cpu_to_be64(PNV_XSCOM_BASE(chip));
	278	reg[1] = cpu_to_be64(PNV_XSCOM_SIZE);
	279	}
	280
967b7523 CLG	281	name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
	282	xscom_offset = fdt_add_subnode(fdt, root_offset, name);
	283	_FDT(xscom_offset);
	284	g_free(name);
	285	_FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
	286	_FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
	287	_FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
	288	_FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
	289
b3b066e9	290	if (pnv_chip_is_power9(chip)) {
967b7523 CLG	291	_FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9,
	292	sizeof(compat_p9))));
	293	} else {
	294	_FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8,
	295	sizeof(compat_p8))));
	296	}
	297
	298	_FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));
	299
	300	args.fdt = fdt;
	301	args.xscom_offset = xscom_offset;
	302
b168a138	303	object_child_foreach(OBJECT(chip), xscom_dt_child, &args);
967b7523 CLG	304	return 0;
	305	}
	306
	307	void pnv_xscom_add_subregion(PnvChip chip, hwaddr offset, MemoryRegion mr)
	308	{
	309	memory_region_add_subregion(&chip->xscom, offset << 3, mr);
	310	}
	311
	312	void pnv_xscom_region_init(MemoryRegion *mr,
	313	struct Object *owner,
	314	const MemoryRegionOps *ops,
	315	void *opaque,
	316	const char *name,
	317	uint64_t size)
	318	{
	319	memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
	320	}