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CommitLineData
33face6b
DG
1/*
2 * QEMU PowerPC pSeries Logical Partition capabilities handling
3 *
4 * Copyright (c) 2017 David Gibson, Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
14a48c1d 24
33face6b 25#include "qemu/osdep.h"
be85537d 26#include "qemu/error-report.h"
33face6b
DG
27#include "qapi/error.h"
28#include "qapi/visitor.h"
ee76a09f 29#include "sysemu/hw_accel.h"
123eec65 30#include "exec/ram_addr.h"
ee76a09f 31#include "target/ppc/cpu.h"
2309832a 32#include "target/ppc/mmu-hash64.h"
ee76a09f
DG
33#include "cpu-models.h"
34#include "kvm_ppc.h"
d6454270 35#include "migration/vmstate.h"
006e9d36 36#include "sysemu/qtest.h"
14a48c1d 37#include "sysemu/tcg.h"
33face6b
DG
38
39#include "hw/ppc/spapr.h"
40
ce2918cb 41typedef struct SpaprCapPossible {
87175d1b
SJS
42 int num; /* size of vals array below */
43 const char *help; /* help text for vals */
44 /*
45 * Note:
46 * - because of the way compatibility is determined vals MUST be ordered
47 * such that later options are a superset of all preceding options.
48 * - the order of vals must be preserved, that is their index is important,
49 * however vals may be added to the end of the list so long as the above
50 * point is observed
51 */
52 const char *vals[];
ce2918cb 53} SpaprCapPossible;
87175d1b 54
ce2918cb 55typedef struct SpaprCapabilityInfo {
33face6b
DG
56 const char *name;
57 const char *description;
4e5fe368 58 int index;
33face6b 59
4e5fe368
SJS
60 /* Getter and Setter Function Pointers */
61 ObjectPropertyAccessor *get;
62 ObjectPropertyAccessor *set;
63 const char *type;
87175d1b 64 /* Possible values if this is a custom string type */
ce2918cb 65 SpaprCapPossible *possible;
33face6b 66 /* Make sure the virtual hardware can support this capability */
ce2918cb
DG
67 void (*apply)(SpaprMachineState *spapr, uint8_t val, Error **errp);
68 void (*cpu_apply)(SpaprMachineState *spapr, PowerPCCPU *cpu,
e2e4f641 69 uint8_t val, Error **errp);
3725ef1a 70 bool (*migrate_needed)(void *opaque);
ce2918cb 71} SpaprCapabilityInfo;
33face6b 72
4e5fe368
SJS
73static void spapr_cap_get_bool(Object *obj, Visitor *v, const char *name,
74 void *opaque, Error **errp)
75{
ce2918cb
DG
76 SpaprCapabilityInfo *cap = opaque;
77 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
4e5fe368
SJS
78 bool value = spapr_get_cap(spapr, cap->index) == SPAPR_CAP_ON;
79
80 visit_type_bool(v, name, &value, errp);
81}
82
83static void spapr_cap_set_bool(Object *obj, Visitor *v, const char *name,
84 void *opaque, Error **errp)
ee76a09f 85{
ce2918cb
DG
86 SpaprCapabilityInfo *cap = opaque;
87 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
4e5fe368 88 bool value;
4e5fe368 89
668f62ec 90 if (!visit_type_bool(v, name, &value, errp)) {
4e5fe368
SJS
91 return;
92 }
93
94 spapr->cmd_line_caps[cap->index] = true;
95 spapr->eff.caps[cap->index] = value ? SPAPR_CAP_ON : SPAPR_CAP_OFF;
96}
97
6898aed7 98
f27aa81e
SJS
99static void spapr_cap_get_string(Object *obj, Visitor *v, const char *name,
100 void *opaque, Error **errp)
87175d1b 101{
ce2918cb
DG
102 SpaprCapabilityInfo *cap = opaque;
103 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
87175d1b
SJS
104 char *val = NULL;
105 uint8_t value = spapr_get_cap(spapr, cap->index);
106
107 if (value >= cap->possible->num) {
108 error_setg(errp, "Invalid value (%d) for cap-%s", value, cap->name);
109 return;
110 }
111
112 val = g_strdup(cap->possible->vals[value]);
113
114 visit_type_str(v, name, &val, errp);
115 g_free(val);
116}
117
f27aa81e
SJS
118static void spapr_cap_set_string(Object *obj, Visitor *v, const char *name,
119 void *opaque, Error **errp)
87175d1b 120{
ce2918cb
DG
121 SpaprCapabilityInfo *cap = opaque;
122 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
87175d1b
SJS
123 uint8_t i;
124 char *val;
125
668f62ec 126 if (!visit_type_str(v, name, &val, errp)) {
87175d1b
SJS
127 return;
128 }
129
130 if (!strcmp(val, "?")) {
131 error_setg(errp, "%s", cap->possible->help);
132 goto out;
133 }
134 for (i = 0; i < cap->possible->num; i++) {
135 if (!strcasecmp(val, cap->possible->vals[i])) {
136 spapr->cmd_line_caps[cap->index] = true;
137 spapr->eff.caps[cap->index] = i;
138 goto out;
139 }
140 }
141
142 error_setg(errp, "Invalid capability mode \"%s\" for cap-%s", val,
143 cap->name);
144out:
145 g_free(val);
146}
147
2309832a
DG
148static void spapr_cap_get_pagesize(Object *obj, Visitor *v, const char *name,
149 void *opaque, Error **errp)
150{
ce2918cb
DG
151 SpaprCapabilityInfo *cap = opaque;
152 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
2309832a
DG
153 uint8_t val = spapr_get_cap(spapr, cap->index);
154 uint64_t pagesize = (1ULL << val);
155
156 visit_type_size(v, name, &pagesize, errp);
157}
158
159static void spapr_cap_set_pagesize(Object *obj, Visitor *v, const char *name,
160 void *opaque, Error **errp)
161{
ce2918cb
DG
162 SpaprCapabilityInfo *cap = opaque;
163 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
2309832a
DG
164 uint64_t pagesize;
165 uint8_t val;
2309832a 166
668f62ec 167 if (!visit_type_size(v, name, &pagesize, errp)) {
2309832a
DG
168 return;
169 }
170
171 if (!is_power_of_2(pagesize)) {
172 error_setg(errp, "cap-%s must be a power of 2", cap->name);
173 return;
174 }
175
176 val = ctz64(pagesize);
177 spapr->cmd_line_caps[cap->index] = true;
178 spapr->eff.caps[cap->index] = val;
179}
180
ce2918cb 181static void cap_htm_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
4e5fe368
SJS
182{
183 if (!val) {
184 /* TODO: We don't support disabling htm yet */
185 return;
186 }
ee76a09f
DG
187 if (tcg_enabled()) {
188 error_setg(errp,
f92be77f
DB
189 "No Transactional Memory support in TCG,"
190 " try appending -machine cap-htm=off");
ee76a09f
DG
191 } else if (kvm_enabled() && !kvmppc_has_cap_htm()) {
192 error_setg(errp,
f92be77f
DB
193"KVM implementation does not support Transactional Memory,"
194 " try appending -machine cap-htm=off"
ee76a09f
DG
195 );
196 }
197}
198
ce2918cb 199static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
29386642
DG
200{
201 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
202 CPUPPCState *env = &cpu->env;
203
4e5fe368
SJS
204 if (!val) {
205 /* TODO: We don't support disabling vsx yet */
206 return;
207 }
29386642
DG
208 /* Allowable CPUs in spapr_cpu_core.c should already have gotten
209 * rid of anything that doesn't do VMX */
210 g_assert(env->insns_flags & PPC_ALTIVEC);
211 if (!(env->insns_flags2 & PPC2_VSX)) {
f92be77f
DB
212 error_setg(errp, "VSX support not available,"
213 " try appending -machine cap-vsx=off");
29386642
DG
214 }
215}
216
ce2918cb 217static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
2d1fb9bc
DG
218{
219 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
220 CPUPPCState *env = &cpu->env;
221
4e5fe368
SJS
222 if (!val) {
223 /* TODO: We don't support disabling dfp yet */
224 return;
225 }
2d1fb9bc 226 if (!(env->insns_flags2 & PPC2_DFP)) {
f92be77f
DB
227 error_setg(errp, "DFP support not available,"
228 " try appending -machine cap-dfp=off");
2d1fb9bc
DG
229 }
230}
231
ce2918cb 232SpaprCapPossible cap_cfpc_possible = {
f27aa81e
SJS
233 .num = 3,
234 .vals = {"broken", "workaround", "fixed"},
235 .help = "broken - no protection, workaround - workaround available,"
236 " fixed - fixed in hardware",
237};
238
ce2918cb 239static void cap_safe_cache_apply(SpaprMachineState *spapr, uint8_t val,
8f38eaf8
SJS
240 Error **errp)
241{
f27aa81e
SJS
242 uint8_t kvm_val = kvmppc_get_cap_safe_cache();
243
8f38eaf8 244 if (tcg_enabled() && val) {
006e9d36 245 /* TCG only supports broken, allow other values and print a warning */
a816f2d6
GK
246 warn_report("TCG doesn't support requested feature, cap-cfpc=%s",
247 cap_cfpc_possible.vals[val]);
f27aa81e
SJS
248 } else if (kvm_enabled() && (val > kvm_val)) {
249 error_setg(errp,
f92be77f
DB
250 "Requested safe cache capability level not supported by kvm,"
251 " try appending -machine cap-cfpc=%s",
f27aa81e 252 cap_cfpc_possible.vals[kvm_val]);
8f38eaf8
SJS
253 }
254}
255
ce2918cb 256SpaprCapPossible cap_sbbc_possible = {
aaf265ff
SJS
257 .num = 3,
258 .vals = {"broken", "workaround", "fixed"},
259 .help = "broken - no protection, workaround - workaround available,"
260 " fixed - fixed in hardware",
261};
262
ce2918cb 263static void cap_safe_bounds_check_apply(SpaprMachineState *spapr, uint8_t val,
09114fd8
SJS
264 Error **errp)
265{
aaf265ff
SJS
266 uint8_t kvm_val = kvmppc_get_cap_safe_bounds_check();
267
09114fd8 268 if (tcg_enabled() && val) {
006e9d36 269 /* TCG only supports broken, allow other values and print a warning */
a816f2d6
GK
270 warn_report("TCG doesn't support requested feature, cap-sbbc=%s",
271 cap_sbbc_possible.vals[val]);
aaf265ff
SJS
272 } else if (kvm_enabled() && (val > kvm_val)) {
273 error_setg(errp,
f92be77f
DB
274"Requested safe bounds check capability level not supported by kvm,"
275 " try appending -machine cap-sbbc=%s",
aaf265ff 276 cap_sbbc_possible.vals[kvm_val]);
09114fd8
SJS
277 }
278}
279
ce2918cb 280SpaprCapPossible cap_ibs_possible = {
399b2896 281 .num = 5,
c76c0d30 282 /* Note workaround only maintained for compatibility */
399b2896
SJS
283 .vals = {"broken", "workaround", "fixed-ibs", "fixed-ccd", "fixed-na"},
284 .help = "broken - no protection, workaround - count cache flush"
285 ", fixed-ibs - indirect branch serialisation,"
286 " fixed-ccd - cache count disabled,"
287 " fixed-na - fixed in hardware (no longer applicable)",
c76c0d30
SJS
288};
289
ce2918cb 290static void cap_safe_indirect_branch_apply(SpaprMachineState *spapr,
4be8d4e7
SJS
291 uint8_t val, Error **errp)
292{
c76c0d30
SJS
293 uint8_t kvm_val = kvmppc_get_cap_safe_indirect_branch();
294
399b2896 295 if (tcg_enabled() && val) {
006e9d36 296 /* TCG only supports broken, allow other values and print a warning */
a816f2d6
GK
297 warn_report("TCG doesn't support requested feature, cap-ibs=%s",
298 cap_ibs_possible.vals[val]);
399b2896 299 } else if (kvm_enabled() && (val > kvm_val)) {
c76c0d30 300 error_setg(errp,
f92be77f
DB
301"Requested safe indirect branch capability level not supported by kvm,"
302 " try appending -machine cap-ibs=%s",
c76c0d30 303 cap_ibs_possible.vals[kvm_val]);
4be8d4e7
SJS
304 }
305}
306
8f38eaf8 307#define VALUE_DESC_TRISTATE " (broken, workaround, fixed)"
4e5fe368 308
ce2918cb 309void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
123eec65
DG
310 Error **errp)
311{
312 hwaddr maxpagesize = (1ULL << spapr->eff.caps[SPAPR_CAP_HPT_MAXPAGESIZE]);
313
314 if (!kvmppc_hpt_needs_host_contiguous_pages()) {
315 return;
316 }
317
318 if (maxpagesize > pagesize) {
319 error_setg(errp,
320 "Can't support %"HWADDR_PRIu" kiB guest pages with %"
321 HWADDR_PRIu" kiB host pages with this KVM implementation",
322 maxpagesize >> 10, pagesize >> 10);
323 }
324}
325
ce2918cb 326static void cap_hpt_maxpagesize_apply(SpaprMachineState *spapr,
2309832a
DG
327 uint8_t val, Error **errp)
328{
329 if (val < 12) {
330 error_setg(errp, "Require at least 4kiB hpt-max-page-size");
123eec65 331 return;
2309832a
DG
332 } else if (val < 16) {
333 warn_report("Many guests require at least 64kiB hpt-max-page-size");
334 }
123eec65 335
905b7ee4 336 spapr_check_pagesize(spapr, qemu_minrampagesize(), errp);
2309832a
DG
337}
338
3725ef1a
GK
339static bool cap_hpt_maxpagesize_migrate_needed(void *opaque)
340{
341 return !SPAPR_MACHINE_GET_CLASS(opaque)->pre_4_1_migration;
342}
343
9dceda5f
DG
344static bool spapr_pagesize_cb(void *opaque, uint32_t seg_pshift,
345 uint32_t pshift)
346{
347 unsigned maxshift = *((unsigned *)opaque);
348
349 assert(pshift >= seg_pshift);
350
351 /* Don't allow the guest to use pages bigger than the configured
352 * maximum size */
353 if (pshift > maxshift) {
354 return false;
355 }
356
357 /* For whatever reason, KVM doesn't allow multiple pagesizes
358 * within a segment, *except* for the case of 16M pages in a 4k or
359 * 64k segment. Always exclude other cases, so that TCG and KVM
360 * guests see a consistent environment */
361 if ((pshift != seg_pshift) && (pshift != 24)) {
362 return false;
363 }
364
365 return true;
366}
367
ce2918cb 368static void cap_hpt_maxpagesize_cpu_apply(SpaprMachineState *spapr,
9dceda5f
DG
369 PowerPCCPU *cpu,
370 uint8_t val, Error **errp)
371{
372 unsigned maxshift = val;
373
374 ppc_hash64_filter_pagesizes(cpu, spapr_pagesize_cb, &maxshift);
375}
376
ce2918cb 377static void cap_nested_kvm_hv_apply(SpaprMachineState *spapr,
b9a477b7
SJS
378 uint8_t val, Error **errp)
379{
380 if (!val) {
381 /* capability disabled by default */
382 return;
383 }
384
385 if (tcg_enabled()) {
386 error_setg(errp,
f92be77f
DB
387 "No Nested KVM-HV support in tcg,"
388 " try appending -machine cap-nested-hv=off");
b9a477b7
SJS
389 } else if (kvm_enabled()) {
390 if (!kvmppc_has_cap_nested_kvm_hv()) {
391 error_setg(errp,
f92be77f
DB
392"KVM implementation does not support Nested KVM-HV,"
393 " try appending -machine cap-nested-hv=off");
b9a477b7
SJS
394 } else if (kvmppc_set_cap_nested_kvm_hv(val) < 0) {
395 error_setg(errp,
396"Error enabling cap-nested-hv with KVM, try cap-nested-hv=off");
397 }
398 }
399}
400
ce2918cb 401static void cap_large_decr_apply(SpaprMachineState *spapr,
c982f5cf
SJS
402 uint8_t val, Error **errp)
403{
a8dafa52 404 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
7d050527 405 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
a8dafa52
SJS
406
407 if (!val) {
408 return; /* Disabled by default */
409 }
410
411 if (tcg_enabled()) {
412 if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
413 spapr->max_compat_pvr)) {
414 error_setg(errp,
415 "Large decrementer only supported on POWER9, try -cpu POWER9");
416 return;
417 }
7d050527
SJS
418 } else if (kvm_enabled()) {
419 int kvm_nr_bits = kvmppc_get_cap_large_decr();
420
421 if (!kvm_nr_bits) {
422 error_setg(errp,
f92be77f
DB
423 "No large decrementer support,"
424 " try appending -machine cap-large-decr=off");
7d050527
SJS
425 } else if (pcc->lrg_decr_bits != kvm_nr_bits) {
426 error_setg(errp,
f92be77f
DB
427"KVM large decrementer size (%d) differs to model (%d),"
428 " try appending -machine cap-large-decr=off",
7d050527
SJS
429 kvm_nr_bits, pcc->lrg_decr_bits);
430 }
a8dafa52
SJS
431 }
432}
433
ce2918cb 434static void cap_large_decr_cpu_apply(SpaprMachineState *spapr,
a8dafa52
SJS
435 PowerPCCPU *cpu,
436 uint8_t val, Error **errp)
437{
438 CPUPPCState *env = &cpu->env;
439 target_ulong lpcr = env->spr[SPR_LPCR];
440
7d050527
SJS
441 if (kvm_enabled()) {
442 if (kvmppc_enable_cap_large_decr(cpu, val)) {
443 error_setg(errp,
f92be77f
DB
444 "No large decrementer support,"
445 " try appending -machine cap-large-decr=off");
7d050527
SJS
446 }
447 }
448
a8dafa52
SJS
449 if (val) {
450 lpcr |= LPCR_LD;
451 } else {
452 lpcr &= ~LPCR_LD;
453 }
454 ppc_store_lpcr(cpu, lpcr);
c982f5cf
SJS
455}
456
ce2918cb 457static void cap_ccf_assist_apply(SpaprMachineState *spapr, uint8_t val,
8ff43ee4
SJS
458 Error **errp)
459{
460 uint8_t kvm_val = kvmppc_get_cap_count_cache_flush_assist();
461
462 if (tcg_enabled() && val) {
37965dfe
DG
463 /* TCG doesn't implement anything here, but allow with a warning */
464 warn_report("TCG doesn't support requested feature, cap-ccf-assist=on");
8ff43ee4 465 } else if (kvm_enabled() && (val > kvm_val)) {
37965dfe
DG
466 uint8_t kvm_ibs = kvmppc_get_cap_safe_indirect_branch();
467
468 if (kvm_ibs == SPAPR_CAP_FIXED_CCD) {
469 /*
470 * If we don't have CCF assist on the host, the assist
471 * instruction is a harmless no-op. It won't correctly
472 * implement the cache count flush *but* if we have
473 * count-cache-disabled in the host, that flush is
474 * unnnecessary. So, specifically allow this case. This
475 * allows us to have better performance on POWER9 DD2.3,
476 * while still working on POWER9 DD2.2 and POWER8 host
477 * cpus.
478 */
479 return;
480 }
8ff43ee4 481 error_setg(errp,
f92be77f
DB
482"Requested count cache flush assist capability level not supported by kvm,"
483 " try appending -machine cap-ccf-assist=off");
8ff43ee4
SJS
484 }
485}
486
8af7e1fe 487static void cap_fwnmi_apply(SpaprMachineState *spapr, uint8_t val,
9d953ce4
AP
488 Error **errp)
489{
490 if (!val) {
491 return; /* Disabled by default */
492 }
f03496bc 493
89ba4565 494 if (kvm_enabled()) {
ec010c00
NP
495 if (!kvmppc_get_fwnmi()) {
496 error_setg(errp,
497"Firmware Assisted Non-Maskable Interrupts(FWNMI) not supported by KVM.");
498 error_append_hint(errp, "Try appending -machine cap-fwnmi=off\n");
f03496bc
AP
499 }
500 }
9d953ce4
AP
501}
502
ce2918cb 503SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
4e5fe368 504 [SPAPR_CAP_HTM] = {
ee76a09f
DG
505 .name = "htm",
506 .description = "Allow Hardware Transactional Memory (HTM)",
4e5fe368
SJS
507 .index = SPAPR_CAP_HTM,
508 .get = spapr_cap_get_bool,
509 .set = spapr_cap_set_bool,
510 .type = "bool",
511 .apply = cap_htm_apply,
ee76a09f 512 },
4e5fe368 513 [SPAPR_CAP_VSX] = {
29386642
DG
514 .name = "vsx",
515 .description = "Allow Vector Scalar Extensions (VSX)",
4e5fe368
SJS
516 .index = SPAPR_CAP_VSX,
517 .get = spapr_cap_get_bool,
518 .set = spapr_cap_set_bool,
519 .type = "bool",
520 .apply = cap_vsx_apply,
29386642 521 },
4e5fe368 522 [SPAPR_CAP_DFP] = {
2d1fb9bc
DG
523 .name = "dfp",
524 .description = "Allow Decimal Floating Point (DFP)",
4e5fe368
SJS
525 .index = SPAPR_CAP_DFP,
526 .get = spapr_cap_get_bool,
527 .set = spapr_cap_set_bool,
528 .type = "bool",
529 .apply = cap_dfp_apply,
2d1fb9bc 530 },
8f38eaf8
SJS
531 [SPAPR_CAP_CFPC] = {
532 .name = "cfpc",
533 .description = "Cache Flush on Privilege Change" VALUE_DESC_TRISTATE,
534 .index = SPAPR_CAP_CFPC,
f27aa81e
SJS
535 .get = spapr_cap_get_string,
536 .set = spapr_cap_set_string,
8f38eaf8 537 .type = "string",
f27aa81e 538 .possible = &cap_cfpc_possible,
8f38eaf8
SJS
539 .apply = cap_safe_cache_apply,
540 },
09114fd8
SJS
541 [SPAPR_CAP_SBBC] = {
542 .name = "sbbc",
543 .description = "Speculation Barrier Bounds Checking" VALUE_DESC_TRISTATE,
544 .index = SPAPR_CAP_SBBC,
aaf265ff
SJS
545 .get = spapr_cap_get_string,
546 .set = spapr_cap_set_string,
09114fd8 547 .type = "string",
aaf265ff 548 .possible = &cap_sbbc_possible,
09114fd8
SJS
549 .apply = cap_safe_bounds_check_apply,
550 },
4be8d4e7
SJS
551 [SPAPR_CAP_IBS] = {
552 .name = "ibs",
c76c0d30 553 .description =
399b2896
SJS
554 "Indirect Branch Speculation (broken, workaround, fixed-ibs,"
555 "fixed-ccd, fixed-na)",
4be8d4e7 556 .index = SPAPR_CAP_IBS,
c76c0d30
SJS
557 .get = spapr_cap_get_string,
558 .set = spapr_cap_set_string,
4be8d4e7 559 .type = "string",
c76c0d30 560 .possible = &cap_ibs_possible,
4be8d4e7
SJS
561 .apply = cap_safe_indirect_branch_apply,
562 },
2309832a
DG
563 [SPAPR_CAP_HPT_MAXPAGESIZE] = {
564 .name = "hpt-max-page-size",
565 .description = "Maximum page size for Hash Page Table guests",
566 .index = SPAPR_CAP_HPT_MAXPAGESIZE,
567 .get = spapr_cap_get_pagesize,
568 .set = spapr_cap_set_pagesize,
569 .type = "int",
570 .apply = cap_hpt_maxpagesize_apply,
9dceda5f 571 .cpu_apply = cap_hpt_maxpagesize_cpu_apply,
3725ef1a 572 .migrate_needed = cap_hpt_maxpagesize_migrate_needed,
2309832a 573 },
b9a477b7
SJS
574 [SPAPR_CAP_NESTED_KVM_HV] = {
575 .name = "nested-hv",
576 .description = "Allow Nested KVM-HV",
577 .index = SPAPR_CAP_NESTED_KVM_HV,
578 .get = spapr_cap_get_bool,
579 .set = spapr_cap_set_bool,
580 .type = "bool",
581 .apply = cap_nested_kvm_hv_apply,
582 },
c982f5cf
SJS
583 [SPAPR_CAP_LARGE_DECREMENTER] = {
584 .name = "large-decr",
585 .description = "Allow Large Decrementer",
586 .index = SPAPR_CAP_LARGE_DECREMENTER,
587 .get = spapr_cap_get_bool,
588 .set = spapr_cap_set_bool,
589 .type = "bool",
590 .apply = cap_large_decr_apply,
a8dafa52 591 .cpu_apply = cap_large_decr_cpu_apply,
c982f5cf 592 },
8ff43ee4
SJS
593 [SPAPR_CAP_CCF_ASSIST] = {
594 .name = "ccf-assist",
595 .description = "Count Cache Flush Assist via HW Instruction",
596 .index = SPAPR_CAP_CCF_ASSIST,
597 .get = spapr_cap_get_bool,
598 .set = spapr_cap_set_bool,
599 .type = "bool",
600 .apply = cap_ccf_assist_apply,
601 },
8af7e1fe
NP
602 [SPAPR_CAP_FWNMI] = {
603 .name = "fwnmi",
604 .description = "Implements PAPR FWNMI option",
605 .index = SPAPR_CAP_FWNMI,
9d953ce4
AP
606 .get = spapr_cap_get_bool,
607 .set = spapr_cap_set_bool,
608 .type = "bool",
8af7e1fe 609 .apply = cap_fwnmi_apply,
9d953ce4 610 },
33face6b
DG
611};
612
ce2918cb 613static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr,
ad99d04c 614 const char *cputype)
33face6b 615{
ce2918cb
DG
616 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
617 SpaprCapabilities caps;
33face6b
DG
618
619 caps = smc->default_caps;
620
edaa7995
SJS
621 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_3_00,
622 0, spapr->max_compat_pvr)) {
623 caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF;
624 }
625
ad99d04c
DG
626 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_07,
627 0, spapr->max_compat_pvr)) {
4e5fe368 628 caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
b2540203 629 caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
ee76a09f 630 }
33face6b 631
ad99d04c
DG
632 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_06_PLUS,
633 0, spapr->max_compat_pvr)) {
813f3cf6
SJS
634 caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
635 }
636
ad99d04c
DG
637 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_06,
638 0, spapr->max_compat_pvr)) {
4e5fe368
SJS
639 caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_OFF;
640 caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_OFF;
813f3cf6 641 caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
29386642
DG
642 }
643
e8937295
GK
644 /* This is for pseries-2.12 and older */
645 if (smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] == 0) {
646 uint8_t mps;
647
648 if (kvmppc_hpt_needs_host_contiguous_pages()) {
905b7ee4 649 mps = ctz64(qemu_minrampagesize());
e8937295
GK
650 } else {
651 mps = 34; /* allow everything up to 16GiB, i.e. everything */
652 }
653
654 caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = mps;
655 }
656
33face6b
DG
657 return caps;
658}
659
4e5fe368 660int spapr_caps_pre_load(void *opaque)
be85537d 661{
ce2918cb 662 SpaprMachineState *spapr = opaque;
be85537d 663
4e5fe368
SJS
664 /* Set to default so we can tell if this came in with the migration */
665 spapr->mig = spapr->def;
666 return 0;
667}
668
669int spapr_caps_pre_save(void *opaque)
670{
ce2918cb 671 SpaprMachineState *spapr = opaque;
4e5fe368
SJS
672
673 spapr->mig = spapr->eff;
674 return 0;
be85537d
DG
675}
676
677/* This has to be called from the top-level spapr post_load, not the
678 * caps specific one. Otherwise it wouldn't be called when the source
679 * caps are all defaults, which could still conflict with overridden
680 * caps on the destination */
ce2918cb 681int spapr_caps_post_migration(SpaprMachineState *spapr)
be85537d 682{
be85537d
DG
683 int i;
684 bool ok = true;
ce2918cb
DG
685 SpaprCapabilities dstcaps = spapr->eff;
686 SpaprCapabilities srccaps;
be85537d 687
ad99d04c 688 srccaps = default_caps_with_cpu(spapr, MACHINE(spapr)->cpu_type);
4e5fe368
SJS
689 for (i = 0; i < SPAPR_CAP_NUM; i++) {
690 /* If not default value then assume came in with the migration */
691 if (spapr->mig.caps[i] != spapr->def.caps[i]) {
692 srccaps.caps[i] = spapr->mig.caps[i];
693 }
694 }
be85537d 695
4e5fe368 696 for (i = 0; i < SPAPR_CAP_NUM; i++) {
ce2918cb 697 SpaprCapabilityInfo *info = &capability_table[i];
be85537d 698
4e5fe368
SJS
699 if (srccaps.caps[i] > dstcaps.caps[i]) {
700 error_report("cap-%s higher level (%d) in incoming stream than on destination (%d)",
701 info->name, srccaps.caps[i], dstcaps.caps[i]);
be85537d
DG
702 ok = false;
703 }
704
4e5fe368
SJS
705 if (srccaps.caps[i] < dstcaps.caps[i]) {
706 warn_report("cap-%s lower level (%d) in incoming stream than on destination (%d)",
707 info->name, srccaps.caps[i], dstcaps.caps[i]);
be85537d
DG
708 }
709 }
710
be85537d
DG
711 return ok ? 0 : -EINVAL;
712}
713
1f63ebaa 714/* Used to generate the migration field and needed function for a spapr cap */
8c5909c4
SJS
715#define SPAPR_CAP_MIG_STATE(sname, cap) \
716static bool spapr_cap_##sname##_needed(void *opaque) \
1f63ebaa 717{ \
ce2918cb 718 SpaprMachineState *spapr = opaque; \
3725ef1a
GK
719 bool (*needed)(void *opaque) = \
720 capability_table[cap].migrate_needed; \
1f63ebaa 721 \
3725ef1a
GK
722 return needed ? needed(opaque) : true && \
723 spapr->cmd_line_caps[cap] && \
8c5909c4
SJS
724 (spapr->eff.caps[cap] != \
725 spapr->def.caps[cap]); \
1f63ebaa
SJS
726} \
727 \
8c5909c4
SJS
728const VMStateDescription vmstate_spapr_cap_##sname = { \
729 .name = "spapr/cap/" #sname, \
1f63ebaa
SJS
730 .version_id = 1, \
731 .minimum_version_id = 1, \
8c5909c4 732 .needed = spapr_cap_##sname##_needed, \
1f63ebaa 733 .fields = (VMStateField[]) { \
8c5909c4 734 VMSTATE_UINT8(mig.caps[cap], \
ce2918cb 735 SpaprMachineState), \
1f63ebaa
SJS
736 VMSTATE_END_OF_LIST() \
737 }, \
be85537d
DG
738}
739
8c5909c4
SJS
740SPAPR_CAP_MIG_STATE(htm, SPAPR_CAP_HTM);
741SPAPR_CAP_MIG_STATE(vsx, SPAPR_CAP_VSX);
742SPAPR_CAP_MIG_STATE(dfp, SPAPR_CAP_DFP);
743SPAPR_CAP_MIG_STATE(cfpc, SPAPR_CAP_CFPC);
744SPAPR_CAP_MIG_STATE(sbbc, SPAPR_CAP_SBBC);
745SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS);
64d4a534 746SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXPAGESIZE);
b9a477b7 747SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV);
c982f5cf 748SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER);
8ff43ee4 749SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST);
8af7e1fe 750SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI);
33face6b 751
ce2918cb 752void spapr_caps_init(SpaprMachineState *spapr)
33face6b 753{
ce2918cb 754 SpaprCapabilities default_caps;
33face6b
DG
755 int i;
756
9f6edd06 757 /* Compute the actual set of caps we should run with */
ad99d04c 758 default_caps = default_caps_with_cpu(spapr, MACHINE(spapr)->cpu_type);
4e5fe368
SJS
759
760 for (i = 0; i < SPAPR_CAP_NUM; i++) {
761 /* Store the defaults */
762 spapr->def.caps[i] = default_caps.caps[i];
763 /* If not set on the command line then apply the default value */
764 if (!spapr->cmd_line_caps[i]) {
765 spapr->eff.caps[i] = default_caps.caps[i];
766 }
33face6b 767 }
9f6edd06 768}
33face6b 769
ce2918cb 770void spapr_caps_apply(SpaprMachineState *spapr)
9f6edd06
DG
771{
772 int i;
4e5fe368
SJS
773
774 for (i = 0; i < SPAPR_CAP_NUM; i++) {
ce2918cb 775 SpaprCapabilityInfo *info = &capability_table[i];
33face6b 776
4e5fe368
SJS
777 /*
778 * If the apply function can't set the desired level and thinks it's
779 * fatal, it should cause that.
780 */
781 info->apply(spapr, spapr->eff.caps[i], &error_fatal);
33face6b 782 }
33face6b
DG
783}
784
ce2918cb 785void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu)
e2e4f641
DG
786{
787 int i;
788
789 for (i = 0; i < SPAPR_CAP_NUM; i++) {
ce2918cb 790 SpaprCapabilityInfo *info = &capability_table[i];
e2e4f641
DG
791
792 /*
793 * If the apply function can't set the desired level and thinks it's
794 * fatal, it should cause that.
795 */
796 if (info->cpu_apply) {
797 info->cpu_apply(spapr, cpu, spapr->eff.caps[i], &error_fatal);
798 }
799 }
800}
801
40c2281c 802void spapr_caps_add_properties(SpaprMachineClass *smc)
33face6b 803{
33face6b
DG
804 ObjectClass *klass = OBJECT_CLASS(smc);
805 int i;
806
807 for (i = 0; i < ARRAY_SIZE(capability_table); i++) {
ce2918cb 808 SpaprCapabilityInfo *cap = &capability_table[i];
d7588805 809 char *name = g_strdup_printf("cap-%s", cap->name);
4e5fe368 810 char *desc;
33face6b 811
4e5fe368
SJS
812 object_class_property_add(klass, name, cap->type,
813 cap->get, cap->set,
d2623129 814 NULL, cap);
33face6b 815
895d5cd6 816 desc = g_strdup_printf("%s", cap->description);
7eecec7d 817 object_class_property_set_description(klass, name, desc);
d7588805 818 g_free(name);
4e5fe368 819 g_free(desc);
33face6b
DG
820 }
821}