]> git.proxmox.com Git - mirror_qemu.git/blame - hw/ppc/spapr_drc.c
spapr: Call spapr_drc_reset() for all DRCs at CAS
[mirror_qemu.git] / hw / ppc / spapr_drc.c
CommitLineData
bbf5c878
MR
1/*
2 * QEMU SPAPR Dynamic Reconfiguration Connector Implementation
3 *
4 * Copyright IBM Corp. 2014
5 *
6 * Authors:
7 * Michael Roth <mdroth@linux.vnet.ibm.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
11 */
12
0d75590d 13#include "qemu/osdep.h"
da34e65c 14#include "qapi/error.h"
15280c36 15#include "qapi/qmp/qnull.h"
4771d756 16#include "cpu.h"
f348b6d1 17#include "qemu/cutils.h"
bbf5c878
MR
18#include "hw/ppc/spapr_drc.h"
19#include "qom/object.h"
d6454270 20#include "migration/vmstate.h"
bbf5c878
MR
21#include "qapi/visitor.h"
22#include "qemu/error-report.h"
0cb688d2 23#include "hw/ppc/spapr.h" /* for RTAS return codes */
31834723 24#include "hw/pci-host/spapr.h" /* spapr_phb_remove_pci_device_cb callback */
ee3a71e3 25#include "hw/ppc/spapr_nvdimm.h"
d9c95c71 26#include "sysemu/device_tree.h"
71e8a915 27#include "sysemu/reset.h"
24ac7755 28#include "trace.h"
bbf5c878
MR
29
30#define DRC_CONTAINER_PATH "/dr-connector"
31#define DRC_INDEX_TYPE_SHIFT 28
627c2ef7 32#define DRC_INDEX_ID_MASK ((1ULL << DRC_INDEX_TYPE_SHIFT) - 1)
bbf5c878 33
ce2918cb 34SpaprDrcType spapr_drc_type(SpaprDrc *drc)
2d335818 35{
ce2918cb 36 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2d335818
DG
37
38 return 1 << drck->typeshift;
39}
40
ce2918cb 41uint32_t spapr_drc_index(SpaprDrc *drc)
bbf5c878 42{
ce2918cb 43 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2d335818 44
bbf5c878
MR
45 /* no set format for a drc index: it only needs to be globally
46 * unique. this is how we encode the DRC type on bare-metal
47 * however, so might as well do that here
48 */
2d335818
DG
49 return (drck->typeshift << DRC_INDEX_TYPE_SHIFT)
50 | (drc->id & DRC_INDEX_ID_MASK);
bbf5c878
MR
51}
52
ce2918cb 53static uint32_t drc_isolate_physical(SpaprDrc *drc)
bbf5c878 54{
9d4c0f4f
DG
55 switch (drc->state) {
56 case SPAPR_DRC_STATE_PHYSICAL_POWERON:
57 return RTAS_OUT_SUCCESS; /* Nothing to do */
58 case SPAPR_DRC_STATE_PHYSICAL_CONFIGURED:
59 break; /* see below */
60 case SPAPR_DRC_STATE_PHYSICAL_UNISOLATE:
61 return RTAS_OUT_PARAM_ERROR; /* not allowed */
62 default:
63 g_assert_not_reached();
64 }
65
9d4c0f4f 66 drc->state = SPAPR_DRC_STATE_PHYSICAL_POWERON;
0dfabd39 67
f1c52354 68 if (drc->unplug_requested) {
0dfabd39 69 uint32_t drc_index = spapr_drc_index(drc);
9d4c0f4f
DG
70 trace_spapr_drc_set_isolation_state_finalizing(drc_index);
71 spapr_drc_detach(drc);
9d1852ce 72 }
0dfabd39
DG
73
74 return RTAS_OUT_SUCCESS;
75}
76
ce2918cb 77static uint32_t drc_unisolate_physical(SpaprDrc *drc)
0dfabd39 78{
9d4c0f4f
DG
79 switch (drc->state) {
80 case SPAPR_DRC_STATE_PHYSICAL_UNISOLATE:
81 case SPAPR_DRC_STATE_PHYSICAL_CONFIGURED:
82 return RTAS_OUT_SUCCESS; /* Nothing to do */
83 case SPAPR_DRC_STATE_PHYSICAL_POWERON:
84 break; /* see below */
85 default:
86 g_assert_not_reached();
87 }
88
0dfabd39
DG
89 /* cannot unisolate a non-existent resource, and, or resources
90 * which are in an 'UNUSABLE' allocation state. (PAPR 2.7,
91 * 13.5.3.5)
92 */
93 if (!drc->dev) {
94 return RTAS_OUT_NO_SUCH_INDICATOR;
95 }
96
9d4c0f4f 97 drc->state = SPAPR_DRC_STATE_PHYSICAL_UNISOLATE;
4445b1d2
DG
98 drc->ccs_offset = drc->fdt_start_offset;
99 drc->ccs_depth = 0;
0dfabd39
DG
100
101 return RTAS_OUT_SUCCESS;
102}
103
ce2918cb 104static uint32_t drc_isolate_logical(SpaprDrc *drc)
0dfabd39 105{
9d4c0f4f
DG
106 switch (drc->state) {
107 case SPAPR_DRC_STATE_LOGICAL_AVAILABLE:
108 case SPAPR_DRC_STATE_LOGICAL_UNUSABLE:
109 return RTAS_OUT_SUCCESS; /* Nothing to do */
110 case SPAPR_DRC_STATE_LOGICAL_CONFIGURED:
111 break; /* see below */
112 case SPAPR_DRC_STATE_LOGICAL_UNISOLATE:
113 return RTAS_OUT_PARAM_ERROR; /* not allowed */
114 default:
115 g_assert_not_reached();
116 }
117
cf632463
BR
118 /*
119 * Fail any requests to ISOLATE the LMB DRC if this LMB doesn't
120 * belong to a DIMM device that is marked for removal.
121 *
122 * Currently the guest userspace tool drmgr that drives the memory
123 * hotplug/unplug will just try to remove a set of 'removable' LMBs
124 * in response to a hot unplug request that is based on drc-count.
125 * If the LMB being removed doesn't belong to a DIMM device that is
126 * actually being unplugged, fail the isolation request here.
127 */
0dfabd39 128 if (spapr_drc_type(drc) == SPAPR_DR_CONNECTOR_TYPE_LMB
f1c52354 129 && !drc->unplug_requested) {
0dfabd39 130 return RTAS_OUT_HW_ERROR;
cf632463
BR
131 }
132
9d4c0f4f 133 drc->state = SPAPR_DRC_STATE_LOGICAL_AVAILABLE;
bbf5c878 134
0dfabd39
DG
135 /* if we're awaiting release, but still in an unconfigured state,
136 * it's likely the guest is still in the process of configuring
137 * the device and is transitioning the devices to an ISOLATED
138 * state as a part of that process. so we only complete the
139 * removal when this transition happens for a device in a
140 * configured state, as suggested by the state diagram from PAPR+
141 * 2.7, 13.4
142 */
f1c52354 143 if (drc->unplug_requested) {
0dfabd39 144 uint32_t drc_index = spapr_drc_index(drc);
9d4c0f4f
DG
145 trace_spapr_drc_set_isolation_state_finalizing(drc_index);
146 spapr_drc_detach(drc);
bbf5c878 147 }
0dfabd39
DG
148 return RTAS_OUT_SUCCESS;
149}
150
ce2918cb 151static uint32_t drc_unisolate_logical(SpaprDrc *drc)
0dfabd39 152{
9d4c0f4f
DG
153 switch (drc->state) {
154 case SPAPR_DRC_STATE_LOGICAL_UNISOLATE:
155 case SPAPR_DRC_STATE_LOGICAL_CONFIGURED:
156 return RTAS_OUT_SUCCESS; /* Nothing to do */
157 case SPAPR_DRC_STATE_LOGICAL_AVAILABLE:
158 break; /* see below */
159 case SPAPR_DRC_STATE_LOGICAL_UNUSABLE:
160 return RTAS_OUT_NO_SUCH_INDICATOR; /* not allowed */
161 default:
162 g_assert_not_reached();
0dfabd39
DG
163 }
164
9d4c0f4f
DG
165 /* Move to AVAILABLE state should have ensured device was present */
166 g_assert(drc->dev);
bbf5c878 167
9d4c0f4f 168 drc->state = SPAPR_DRC_STATE_LOGICAL_UNISOLATE;
4445b1d2
DG
169 drc->ccs_offset = drc->fdt_start_offset;
170 drc->ccs_depth = 0;
171
0cb688d2 172 return RTAS_OUT_SUCCESS;
bbf5c878
MR
173}
174
ce2918cb 175static uint32_t drc_set_usable(SpaprDrc *drc)
bbf5c878 176{
9d4c0f4f
DG
177 switch (drc->state) {
178 case SPAPR_DRC_STATE_LOGICAL_AVAILABLE:
179 case SPAPR_DRC_STATE_LOGICAL_UNISOLATE:
180 case SPAPR_DRC_STATE_LOGICAL_CONFIGURED:
181 return RTAS_OUT_SUCCESS; /* Nothing to do */
182 case SPAPR_DRC_STATE_LOGICAL_UNUSABLE:
183 break; /* see below */
184 default:
185 g_assert_not_reached();
186 }
187
61736732
DG
188 /* if there's no resource/device associated with the DRC, there's
189 * no way for us to put it in an allocation state consistent with
190 * being 'USABLE'. PAPR 2.7, 13.5.3.4 documents that this should
191 * result in an RTAS return code of -3 / "no such indicator"
192 */
193 if (!drc->dev) {
194 return RTAS_OUT_NO_SUCH_INDICATOR;
195 }
f1c52354 196 if (drc->unplug_requested) {
82a93a1d
DG
197 /* Don't allow the guest to move a device away from UNUSABLE
198 * state when we want to unplug it */
61736732 199 return RTAS_OUT_NO_SUCH_INDICATOR;
9d1852ce
MR
200 }
201
9d4c0f4f 202 drc->state = SPAPR_DRC_STATE_LOGICAL_AVAILABLE;
61736732
DG
203
204 return RTAS_OUT_SUCCESS;
205}
206
ce2918cb 207static uint32_t drc_set_unusable(SpaprDrc *drc)
61736732 208{
9d4c0f4f
DG
209 switch (drc->state) {
210 case SPAPR_DRC_STATE_LOGICAL_UNUSABLE:
211 return RTAS_OUT_SUCCESS; /* Nothing to do */
212 case SPAPR_DRC_STATE_LOGICAL_AVAILABLE:
213 break; /* see below */
214 case SPAPR_DRC_STATE_LOGICAL_UNISOLATE:
215 case SPAPR_DRC_STATE_LOGICAL_CONFIGURED:
216 return RTAS_OUT_NO_SUCH_INDICATOR; /* not allowed */
217 default:
218 g_assert_not_reached();
219 }
220
221 drc->state = SPAPR_DRC_STATE_LOGICAL_UNUSABLE;
f1c52354 222 if (drc->unplug_requested) {
61736732
DG
223 uint32_t drc_index = spapr_drc_index(drc);
224 trace_spapr_drc_set_allocation_state_finalizing(drc_index);
a8dc47fd 225 spapr_drc_detach(drc);
bbf5c878 226 }
61736732 227
0cb688d2 228 return RTAS_OUT_SUCCESS;
bbf5c878
MR
229}
230
dbd26f2f 231static char *spapr_drc_name(SpaprDrc *drc)
bbf5c878 232{
ce2918cb 233 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
79808336
DG
234
235 /* human-readable name for a DRC to encode into the DT
236 * description. this is mainly only used within a guest in place
237 * of the unique DRC index.
238 *
239 * in the case of VIO/PCI devices, it corresponds to a "location
240 * code" that maps a logical device/function (DRC index) to a
241 * physical (or virtual in the case of VIO) location in the system
242 * by chaining together the "location label" for each
243 * encapsulating component.
244 *
245 * since this is more to do with diagnosing physical hardware
246 * issues than guest compatibility, we choose location codes/DRC
247 * names that adhere to the documented format, but avoid encoding
248 * the entire topology information into the label/code, instead
249 * just using the location codes based on the labels for the
250 * endpoints (VIO/PCI adaptor connectors), which is basically just
251 * "C" followed by an integer ID.
252 *
253 * DRC names as documented by PAPR+ v2.7, 13.5.2.4
254 * location codes as documented by PAPR+ v2.7, 12.3.1.5
255 */
256 return g_strdup_printf("%s%d", drck->drc_name_prefix, drc->id);
bbf5c878
MR
257}
258
bbf5c878
MR
259/*
260 * dr-entity-sense sensor value
261 * returned via get-sensor-state RTAS calls
262 * as expected by state diagram in PAPR+ 2.7, 13.4
263 * based on the current allocation/indicator/power states
264 * for the DR connector.
265 */
ce2918cb 266static SpaprDREntitySense physical_entity_sense(SpaprDrc *drc)
bbf5c878 267{
f224d35b
DG
268 /* this assumes all PCI devices are assigned to a 'live insertion'
269 * power domain, where QEMU manages power state automatically as
270 * opposed to the guest. present, non-PCI resources are unaffected
271 * by power state.
272 */
273 return drc->dev ? SPAPR_DR_ENTITY_SENSE_PRESENT
274 : SPAPR_DR_ENTITY_SENSE_EMPTY;
275}
276
ce2918cb 277static SpaprDREntitySense logical_entity_sense(SpaprDrc *drc)
f224d35b 278{
9d4c0f4f
DG
279 switch (drc->state) {
280 case SPAPR_DRC_STATE_LOGICAL_UNUSABLE:
f224d35b 281 return SPAPR_DR_ENTITY_SENSE_UNUSABLE;
9d4c0f4f
DG
282 case SPAPR_DRC_STATE_LOGICAL_AVAILABLE:
283 case SPAPR_DRC_STATE_LOGICAL_UNISOLATE:
284 case SPAPR_DRC_STATE_LOGICAL_CONFIGURED:
285 g_assert(drc->dev);
286 return SPAPR_DR_ENTITY_SENSE_PRESENT;
287 default:
288 g_assert_not_reached();
bbf5c878 289 }
bbf5c878
MR
290}
291
d7bce999
EB
292static void prop_get_index(Object *obj, Visitor *v, const char *name,
293 void *opaque, Error **errp)
bbf5c878 294{
ce2918cb 295 SpaprDrc *drc = SPAPR_DR_CONNECTOR(obj);
0b55aa91 296 uint32_t value = spapr_drc_index(drc);
51e72bc1 297 visit_type_uint32(v, name, &value, errp);
bbf5c878
MR
298}
299
d7bce999
EB
300static void prop_get_fdt(Object *obj, Visitor *v, const char *name,
301 void *opaque, Error **errp)
bbf5c878 302{
ce2918cb 303 SpaprDrc *drc = SPAPR_DR_CONNECTOR(obj);
d2f95f4d 304 QNull *null = NULL;
bbf5c878
MR
305 int fdt_offset_next, fdt_offset, fdt_depth;
306 void *fdt;
307
308 if (!drc->fdt) {
d2f95f4d 309 visit_type_null(v, NULL, &null, errp);
cb3e7f08 310 qobject_unref(null);
bbf5c878
MR
311 return;
312 }
313
314 fdt = drc->fdt;
315 fdt_offset = drc->fdt_start_offset;
316 fdt_depth = 0;
317
318 do {
319 const char *name = NULL;
320 const struct fdt_property *prop = NULL;
321 int prop_len = 0, name_len = 0;
322 uint32_t tag;
ebd226d2 323 bool ok;
bbf5c878
MR
324
325 tag = fdt_next_tag(fdt, fdt_offset, &fdt_offset_next);
326 switch (tag) {
327 case FDT_BEGIN_NODE:
328 fdt_depth++;
329 name = fdt_get_name(fdt, fdt_offset, &name_len);
668f62ec 330 if (!visit_start_struct(v, name, NULL, 0, errp)) {
c75304a1
MA
331 return;
332 }
bbf5c878
MR
333 break;
334 case FDT_END_NODE:
335 /* shouldn't ever see an FDT_END_NODE before FDT_BEGIN_NODE */
336 g_assert(fdt_depth > 0);
ebd226d2 337 ok = visit_check_struct(v, errp);
1158bb2a 338 visit_end_struct(v, NULL);
ebd226d2 339 if (!ok) {
c75304a1
MA
340 return;
341 }
bbf5c878
MR
342 fdt_depth--;
343 break;
344 case FDT_PROP: {
345 int i;
346 prop = fdt_get_property_by_offset(fdt, fdt_offset, &prop_len);
347 name = fdt_string(fdt, fdt32_to_cpu(prop->nameoff));
668f62ec 348 if (!visit_start_list(v, name, NULL, 0, errp)) {
c75304a1
MA
349 return;
350 }
bbf5c878 351 for (i = 0; i < prop_len; i++) {
62a35aaa 352 if (!visit_type_uint8(v, NULL, (uint8_t *)&prop->data[i],
668f62ec 353 errp)) {
c75304a1
MA
354 return;
355 }
356 }
ebd226d2 357 ok = visit_check_list(v, errp);
1158bb2a 358 visit_end_list(v, NULL);
ebd226d2 359 if (!ok) {
a4a1c70d
MA
360 return;
361 }
bbf5c878
MR
362 break;
363 }
364 default:
e20c6314
PMD
365 error_report("device FDT in unexpected state: %d", tag);
366 abort();
bbf5c878
MR
367 }
368 fdt_offset = fdt_offset_next;
369 } while (fdt_depth != 0);
370}
371
bc370a65 372void spapr_drc_attach(SpaprDrc *drc, DeviceState *d)
bbf5c878 373{
0b55aa91 374 trace_spapr_drc_attach(spapr_drc_index(drc));
bbf5c878 375
bc370a65 376 g_assert(!drc->dev);
9d4c0f4f
DG
377 g_assert((drc->state == SPAPR_DRC_STATE_LOGICAL_UNUSABLE)
378 || (drc->state == SPAPR_DRC_STATE_PHYSICAL_POWERON));
bbf5c878 379
bbf5c878 380 drc->dev = d;
d9c95c71 381
bbf5c878
MR
382 object_property_add_link(OBJECT(drc), "device",
383 object_get_typename(OBJECT(drc->dev)),
384 (Object **)(&drc->dev),
d2623129 385 NULL, 0);
bbf5c878
MR
386}
387
ce2918cb 388static void spapr_drc_release(SpaprDrc *drc)
bbf5c878 389{
ce2918cb 390 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
6b762f29
DG
391
392 drck->release(drc->dev);
bbf5c878 393
f1c52354 394 drc->unplug_requested = false;
bbf5c878
MR
395 g_free(drc->fdt);
396 drc->fdt = NULL;
397 drc->fdt_start_offset = 0;
df4fe0b2 398 object_property_del(OBJECT(drc), "device");
bbf5c878 399 drc->dev = NULL;
bbf5c878
MR
400}
401
ce2918cb 402void spapr_drc_detach(SpaprDrc *drc)
9c914e53 403{
ce2918cb 404 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
9d4c0f4f 405
9c914e53
DG
406 trace_spapr_drc_detach(spapr_drc_index(drc));
407
9d4c0f4f 408 g_assert(drc->dev);
a8dc47fd 409
9d4c0f4f 410 drc->unplug_requested = true;
9c914e53 411
9d4c0f4f
DG
412 if (drc->state != drck->empty_state) {
413 trace_spapr_drc_awaiting_quiesce(spapr_drc_index(drc));
9c914e53
DG
414 return;
415 }
416
9c914e53
DG
417 spapr_drc_release(drc);
418}
419
ce2918cb 420void spapr_drc_reset(SpaprDrc *drc)
bbf5c878 421{
ce2918cb 422 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
9d4c0f4f 423
0b55aa91 424 trace_spapr_drc_reset(spapr_drc_index(drc));
b8fdd530 425
bbf5c878 426 /* immediately upon reset we can safely assume DRCs whose devices
4f9242fc 427 * are pending removal can be safely removed.
bbf5c878 428 */
f1c52354 429 if (drc->unplug_requested) {
4f9242fc
DG
430 spapr_drc_release(drc);
431 }
432
4f9242fc 433 if (drc->dev) {
9d4c0f4f
DG
434 /* A device present at reset is ready to go, same as coldplugged */
435 drc->state = drck->ready_state;
188bfe1b
BR
436 /*
437 * Ensure that we are able to send the FDT fragment again
438 * via configure-connector call if the guest requests.
439 */
440 drc->ccs_offset = drc->fdt_start_offset;
441 drc->ccs_depth = 0;
4f9242fc 442 } else {
9d4c0f4f 443 drc->state = drck->empty_state;
188bfe1b
BR
444 drc->ccs_offset = -1;
445 drc->ccs_depth = -1;
bbf5c878
MR
446 }
447}
448
ab858434
GK
449static bool spapr_drc_unplug_requested_needed(void *opaque)
450{
451 return spapr_drc_unplug_requested(opaque);
452}
453
454static const VMStateDescription vmstate_spapr_drc_unplug_requested = {
455 .name = "spapr_drc/unplug_requested",
456 .version_id = 1,
457 .minimum_version_id = 1,
458 .needed = spapr_drc_unplug_requested_needed,
459 .fields = (VMStateField []) {
460 VMSTATE_BOOL(unplug_requested, SpaprDrc),
461 VMSTATE_END_OF_LIST()
462 }
463};
464
cd725bd7 465static bool spapr_drc_needed(void *opaque)
a50919dd 466{
cd725bd7 467 SpaprDrc *drc = opaque;
ce2918cb 468 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
a50919dd 469
4b63db12
GK
470 /*
471 * If no dev is plugged in there is no need to migrate the DRC state
472 * nor to reset the DRC at CAS.
473 */
c618e300 474 if (!drc->dev) {
a50919dd
DHB
475 return false;
476 }
477
478 /*
4b63db12
GK
479 * We need to reset the DRC at CAS or to migrate the DRC state if it's
480 * not equal to the expected long-term state, which is the same as the
ab858434 481 * coldplugged initial state, or if an unplug request is pending.
4b63db12 482 */
ab858434
GK
483 return drc->state != drck->ready_state ||
484 spapr_drc_unplug_requested(drc);
a50919dd
DHB
485}
486
487static const VMStateDescription vmstate_spapr_drc = {
488 .name = "spapr_drc",
489 .version_id = 1,
490 .minimum_version_id = 1,
491 .needed = spapr_drc_needed,
492 .fields = (VMStateField []) {
ce2918cb 493 VMSTATE_UINT32(state, SpaprDrc),
a50919dd 494 VMSTATE_END_OF_LIST()
ab858434
GK
495 },
496 .subsections = (const VMStateDescription * []) {
497 &vmstate_spapr_drc_unplug_requested,
498 NULL
a50919dd
DHB
499 }
500};
501
bbf5c878
MR
502static void realize(DeviceState *d, Error **errp)
503{
ce2918cb 504 SpaprDrc *drc = SPAPR_DR_CONNECTOR(d);
bbf5c878 505 Object *root_container;
f5babeac 506 gchar *link_name;
7a309cc9 507 const char *child_name;
bbf5c878 508
0b55aa91 509 trace_spapr_drc_realize(spapr_drc_index(drc));
bbf5c878
MR
510 /* NOTE: we do this as part of realize/unrealize due to the fact
511 * that the guest will communicate with the DRC via RTAS calls
512 * referencing the global DRC index. By unlinking the DRC
513 * from DRC_CONTAINER_PATH/<drc_index> we effectively make it
514 * inaccessible by the guest, since lookups rely on this path
515 * existing in the composition tree
516 */
517 root_container = container_get(object_get_root(), DRC_CONTAINER_PATH);
f5babeac 518 link_name = g_strdup_printf("%x", spapr_drc_index(drc));
bbf5c878 519 child_name = object_get_canonical_path_component(OBJECT(drc));
0b55aa91 520 trace_spapr_drc_realize_child(spapr_drc_index(drc), child_name);
bbf5c878 521 object_property_add_alias(root_container, link_name,
d2623129 522 drc->owner, child_name);
f5babeac 523 g_free(link_name);
3cad405b 524 vmstate_register(VMSTATE_IF(drc), spapr_drc_index(drc), &vmstate_spapr_drc,
a50919dd 525 drc);
0b55aa91 526 trace_spapr_drc_realize_complete(spapr_drc_index(drc));
bbf5c878
MR
527}
528
b69c3c21 529static void unrealize(DeviceState *d)
bbf5c878 530{
ce2918cb 531 SpaprDrc *drc = SPAPR_DR_CONNECTOR(d);
bbf5c878 532 Object *root_container;
f5babeac 533 gchar *name;
bbf5c878 534
0b55aa91 535 trace_spapr_drc_unrealize(spapr_drc_index(drc));
3cad405b 536 vmstate_unregister(VMSTATE_IF(drc), &vmstate_spapr_drc, drc);
bbf5c878 537 root_container = container_get(object_get_root(), DRC_CONTAINER_PATH);
f5babeac 538 name = g_strdup_printf("%x", spapr_drc_index(drc));
df4fe0b2 539 object_property_del(root_container, name);
f5babeac 540 g_free(name);
bbf5c878
MR
541}
542
ce2918cb 543SpaprDrc *spapr_dr_connector_new(Object *owner, const char *type,
bbf5c878
MR
544 uint32_t id)
545{
ce2918cb 546 SpaprDrc *drc = SPAPR_DR_CONNECTOR(object_new(type));
94649d42 547 char *prop_name;
bbf5c878 548
bbf5c878
MR
549 drc->id = id;
550 drc->owner = owner;
0b55aa91
DG
551 prop_name = g_strdup_printf("dr-connector[%"PRIu32"]",
552 spapr_drc_index(drc));
d2623129 553 object_property_add_child(owner, prop_name, OBJECT(drc));
f3f41030 554 object_unref(OBJECT(drc));
ce189ab2 555 qdev_realize(DEVICE(drc), NULL, NULL);
94649d42 556 g_free(prop_name);
bbf5c878 557
bbf5c878
MR
558 return drc;
559}
560
561static void spapr_dr_connector_instance_init(Object *obj)
562{
ce2918cb
DG
563 SpaprDrc *drc = SPAPR_DR_CONNECTOR(obj);
564 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
bbf5c878 565
d2623129 566 object_property_add_uint32_ptr(obj, "id", &drc->id, OBJ_PROP_FLAG_READ);
bbf5c878 567 object_property_add(obj, "index", "uint32", prop_get_index,
d2623129 568 NULL, NULL, NULL);
bbf5c878 569 object_property_add(obj, "fdt", "struct", prop_get_fdt,
d2623129 570 NULL, NULL, NULL);
9d4c0f4f 571 drc->state = drck->empty_state;
bbf5c878
MR
572}
573
574static void spapr_dr_connector_class_init(ObjectClass *k, void *data)
575{
576 DeviceClass *dk = DEVICE_CLASS(k);
bbf5c878 577
bbf5c878
MR
578 dk->realize = realize;
579 dk->unrealize = unrealize;
c401ae8c 580 /*
eaf1ffbe
GK
581 * Reason: DR connector needs to be wired to either the machine or to a
582 * PHB in spapr_dr_connector_new().
c401ae8c 583 */
e90f2a8c 584 dk->user_creatable = false;
bbf5c878
MR
585}
586
67fea71b
DG
587static bool drc_physical_needed(void *opaque)
588{
ce2918cb
DG
589 SpaprDrcPhysical *drcp = (SpaprDrcPhysical *)opaque;
590 SpaprDrc *drc = SPAPR_DR_CONNECTOR(drcp);
67fea71b
DG
591
592 if ((drc->dev && (drcp->dr_indicator == SPAPR_DR_INDICATOR_ACTIVE))
593 || (!drc->dev && (drcp->dr_indicator == SPAPR_DR_INDICATOR_INACTIVE))) {
594 return false;
595 }
596 return true;
597}
598
599static const VMStateDescription vmstate_spapr_drc_physical = {
600 .name = "spapr_drc/physical",
601 .version_id = 1,
602 .minimum_version_id = 1,
603 .needed = drc_physical_needed,
604 .fields = (VMStateField []) {
ce2918cb 605 VMSTATE_UINT32(dr_indicator, SpaprDrcPhysical),
67fea71b
DG
606 VMSTATE_END_OF_LIST()
607 }
608};
609
610static void drc_physical_reset(void *opaque)
611{
ce2918cb
DG
612 SpaprDrc *drc = SPAPR_DR_CONNECTOR(opaque);
613 SpaprDrcPhysical *drcp = SPAPR_DRC_PHYSICAL(drc);
67fea71b
DG
614
615 if (drc->dev) {
616 drcp->dr_indicator = SPAPR_DR_INDICATOR_ACTIVE;
617 } else {
618 drcp->dr_indicator = SPAPR_DR_INDICATOR_INACTIVE;
619 }
620}
621
622static void realize_physical(DeviceState *d, Error **errp)
623{
ce2918cb 624 SpaprDrcPhysical *drcp = SPAPR_DRC_PHYSICAL(d);
67fea71b
DG
625 Error *local_err = NULL;
626
627 realize(d, &local_err);
628 if (local_err) {
629 error_propagate(errp, local_err);
630 return;
631 }
632
3cad405b
MAL
633 vmstate_register(VMSTATE_IF(drcp),
634 spapr_drc_index(SPAPR_DR_CONNECTOR(drcp)),
67fea71b
DG
635 &vmstate_spapr_drc_physical, drcp);
636 qemu_register_reset(drc_physical_reset, drcp);
637}
638
b69c3c21 639static void unrealize_physical(DeviceState *d)
379ae096 640{
ce2918cb 641 SpaprDrcPhysical *drcp = SPAPR_DRC_PHYSICAL(d);
379ae096 642
b69c3c21 643 unrealize(d);
3cad405b 644 vmstate_unregister(VMSTATE_IF(drcp), &vmstate_spapr_drc_physical, drcp);
379ae096
GK
645 qemu_unregister_reset(drc_physical_reset, drcp);
646}
647
f224d35b
DG
648static void spapr_drc_physical_class_init(ObjectClass *k, void *data)
649{
67fea71b 650 DeviceClass *dk = DEVICE_CLASS(k);
ce2918cb 651 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k);
f224d35b 652
67fea71b 653 dk->realize = realize_physical;
379ae096 654 dk->unrealize = unrealize_physical;
f224d35b 655 drck->dr_entity_sense = physical_entity_sense;
0dfabd39
DG
656 drck->isolate = drc_isolate_physical;
657 drck->unisolate = drc_unisolate_physical;
9d4c0f4f
DG
658 drck->ready_state = SPAPR_DRC_STATE_PHYSICAL_CONFIGURED;
659 drck->empty_state = SPAPR_DRC_STATE_PHYSICAL_POWERON;
f224d35b
DG
660}
661
662static void spapr_drc_logical_class_init(ObjectClass *k, void *data)
663{
ce2918cb 664 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k);
f224d35b
DG
665
666 drck->dr_entity_sense = logical_entity_sense;
0dfabd39
DG
667 drck->isolate = drc_isolate_logical;
668 drck->unisolate = drc_unisolate_logical;
9d4c0f4f
DG
669 drck->ready_state = SPAPR_DRC_STATE_LOGICAL_CONFIGURED;
670 drck->empty_state = SPAPR_DRC_STATE_LOGICAL_UNUSABLE;
f224d35b
DG
671}
672
2d335818
DG
673static void spapr_drc_cpu_class_init(ObjectClass *k, void *data)
674{
ce2918cb 675 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k);
2d335818
DG
676
677 drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_CPU;
1693ea16 678 drck->typename = "CPU";
79808336 679 drck->drc_name_prefix = "CPU ";
6b762f29 680 drck->release = spapr_core_release;
345b12b9 681 drck->dt_populate = spapr_core_dt_populate;
2d335818
DG
682}
683
684static void spapr_drc_pci_class_init(ObjectClass *k, void *data)
685{
ce2918cb 686 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k);
2d335818
DG
687
688 drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_PCI;
1693ea16 689 drck->typename = "28";
79808336 690 drck->drc_name_prefix = "C";
6b762f29 691 drck->release = spapr_phb_remove_pci_device_cb;
46fd0299 692 drck->dt_populate = spapr_pci_dt_populate;
2d335818
DG
693}
694
695static void spapr_drc_lmb_class_init(ObjectClass *k, void *data)
696{
ce2918cb 697 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k);
2d335818
DG
698
699 drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_LMB;
1693ea16 700 drck->typename = "MEM";
79808336 701 drck->drc_name_prefix = "LMB ";
6b762f29 702 drck->release = spapr_lmb_release;
62d38c9b 703 drck->dt_populate = spapr_lmb_dt_populate;
2d335818
DG
704}
705
962b6c36
MR
706static void spapr_drc_phb_class_init(ObjectClass *k, void *data)
707{
ce2918cb 708 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k);
962b6c36
MR
709
710 drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_PHB;
711 drck->typename = "PHB";
712 drck->drc_name_prefix = "PHB ";
bb2bdd81
GK
713 drck->release = spapr_phb_release;
714 drck->dt_populate = spapr_phb_dt_populate;
962b6c36
MR
715}
716
ee3a71e3
SB
717static void spapr_drc_pmem_class_init(ObjectClass *k, void *data)
718{
719 SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k);
720
721 drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_PMEM;
722 drck->typename = "PMEM";
723 drck->drc_name_prefix = "PMEM ";
724 drck->release = NULL;
725 drck->dt_populate = spapr_pmem_dt_populate;
726}
727
bbf5c878
MR
728static const TypeInfo spapr_dr_connector_info = {
729 .name = TYPE_SPAPR_DR_CONNECTOR,
730 .parent = TYPE_DEVICE,
ce2918cb 731 .instance_size = sizeof(SpaprDrc),
bbf5c878 732 .instance_init = spapr_dr_connector_instance_init,
ce2918cb 733 .class_size = sizeof(SpaprDrcClass),
bbf5c878 734 .class_init = spapr_dr_connector_class_init,
2d335818
DG
735 .abstract = true,
736};
737
738static const TypeInfo spapr_drc_physical_info = {
739 .name = TYPE_SPAPR_DRC_PHYSICAL,
740 .parent = TYPE_SPAPR_DR_CONNECTOR,
ce2918cb 741 .instance_size = sizeof(SpaprDrcPhysical),
f224d35b 742 .class_init = spapr_drc_physical_class_init,
2d335818
DG
743 .abstract = true,
744};
745
746static const TypeInfo spapr_drc_logical_info = {
747 .name = TYPE_SPAPR_DRC_LOGICAL,
748 .parent = TYPE_SPAPR_DR_CONNECTOR,
f224d35b 749 .class_init = spapr_drc_logical_class_init,
2d335818
DG
750 .abstract = true,
751};
752
753static const TypeInfo spapr_drc_cpu_info = {
754 .name = TYPE_SPAPR_DRC_CPU,
755 .parent = TYPE_SPAPR_DRC_LOGICAL,
2d335818
DG
756 .class_init = spapr_drc_cpu_class_init,
757};
758
759static const TypeInfo spapr_drc_pci_info = {
760 .name = TYPE_SPAPR_DRC_PCI,
761 .parent = TYPE_SPAPR_DRC_PHYSICAL,
2d335818
DG
762 .class_init = spapr_drc_pci_class_init,
763};
764
765static const TypeInfo spapr_drc_lmb_info = {
766 .name = TYPE_SPAPR_DRC_LMB,
767 .parent = TYPE_SPAPR_DRC_LOGICAL,
2d335818 768 .class_init = spapr_drc_lmb_class_init,
bbf5c878
MR
769};
770
962b6c36
MR
771static const TypeInfo spapr_drc_phb_info = {
772 .name = TYPE_SPAPR_DRC_PHB,
773 .parent = TYPE_SPAPR_DRC_LOGICAL,
ce2918cb 774 .instance_size = sizeof(SpaprDrc),
962b6c36
MR
775 .class_init = spapr_drc_phb_class_init,
776};
777
ee3a71e3
SB
778static const TypeInfo spapr_drc_pmem_info = {
779 .name = TYPE_SPAPR_DRC_PMEM,
780 .parent = TYPE_SPAPR_DRC_LOGICAL,
781 .class_init = spapr_drc_pmem_class_init,
782};
783
bbf5c878
MR
784/* helper functions for external users */
785
ce2918cb 786SpaprDrc *spapr_drc_by_index(uint32_t index)
bbf5c878
MR
787{
788 Object *obj;
f5babeac 789 gchar *name;
bbf5c878 790
f5babeac 791 name = g_strdup_printf("%s/%x", DRC_CONTAINER_PATH, index);
bbf5c878 792 obj = object_resolve_path(name, NULL);
f5babeac 793 g_free(name);
bbf5c878
MR
794
795 return !obj ? NULL : SPAPR_DR_CONNECTOR(obj);
796}
797
ce2918cb 798SpaprDrc *spapr_drc_by_id(const char *type, uint32_t id)
bbf5c878 799{
ce2918cb 800 SpaprDrcClass *drck
fbf55397
DG
801 = SPAPR_DR_CONNECTOR_CLASS(object_class_by_name(type));
802
803 return spapr_drc_by_index(drck->typeshift << DRC_INDEX_TYPE_SHIFT
804 | (id & DRC_INDEX_ID_MASK));
bbf5c878 805}
e4b798bb 806
e4b798bb 807/**
9e7d38e8 808 * spapr_dt_drc
e4b798bb
MR
809 *
810 * @fdt: libfdt device tree
811 * @path: path in the DT to generate properties
812 * @owner: parent Object/DeviceState for which to generate DRC
813 * descriptions for
ce2918cb 814 * @drc_type_mask: mask of SpaprDrcType values corresponding
e4b798bb
MR
815 * to the types of DRCs to generate entries for
816 *
817 * generate OF properties to describe DRC topology/indices to guests
818 *
819 * as documented in PAPR+ v2.1, 13.5.2
820 */
9e7d38e8 821int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask)
e4b798bb
MR
822{
823 Object *root_container;
824 ObjectProperty *prop;
7746abd8 825 ObjectPropertyIterator iter;
e4b798bb
MR
826 uint32_t drc_count = 0;
827 GArray *drc_indexes, *drc_power_domains;
828 GString *drc_names, *drc_types;
829 int ret;
830
776e887f
GK
831 /*
832 * This should really be only called once per node since it overwrites
833 * the OF properties if they already exist.
834 */
835 g_assert(!fdt_get_property(fdt, offset, "ibm,drc-indexes", NULL));
836
e4b798bb
MR
837 /* the first entry of each properties is a 32-bit integer encoding
838 * the number of elements in the array. we won't know this until
839 * we complete the iteration through all the matching DRCs, but
840 * reserve the space now and set the offsets accordingly so we
841 * can fill them in later.
842 */
843 drc_indexes = g_array_new(false, true, sizeof(uint32_t));
844 drc_indexes = g_array_set_size(drc_indexes, 1);
845 drc_power_domains = g_array_new(false, true, sizeof(uint32_t));
846 drc_power_domains = g_array_set_size(drc_power_domains, 1);
847 drc_names = g_string_set_size(g_string_new(NULL), sizeof(uint32_t));
848 drc_types = g_string_set_size(g_string_new(NULL), sizeof(uint32_t));
849
850 /* aliases for all DRConnector objects will be rooted in QOM
851 * composition tree at DRC_CONTAINER_PATH
852 */
853 root_container = container_get(object_get_root(), DRC_CONTAINER_PATH);
854
7746abd8
DB
855 object_property_iter_init(&iter, root_container);
856 while ((prop = object_property_iter_next(&iter))) {
e4b798bb 857 Object *obj;
ce2918cb
DG
858 SpaprDrc *drc;
859 SpaprDrcClass *drck;
dbd26f2f 860 char *drc_name = NULL;
e4b798bb
MR
861 uint32_t drc_index, drc_power_domain;
862
863 if (!strstart(prop->type, "link<", NULL)) {
864 continue;
865 }
866
552d7f49
MA
867 obj = object_property_get_link(root_container, prop->name,
868 &error_abort);
e4b798bb
MR
869 drc = SPAPR_DR_CONNECTOR(obj);
870 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
871
872 if (owner && (drc->owner != owner)) {
873 continue;
874 }
875
2d335818 876 if ((spapr_drc_type(drc) & drc_type_mask) == 0) {
e4b798bb
MR
877 continue;
878 }
879
880 drc_count++;
881
882 /* ibm,drc-indexes */
0b55aa91 883 drc_index = cpu_to_be32(spapr_drc_index(drc));
e4b798bb
MR
884 g_array_append_val(drc_indexes, drc_index);
885
886 /* ibm,drc-power-domains */
887 drc_power_domain = cpu_to_be32(-1);
888 g_array_append_val(drc_power_domains, drc_power_domain);
889
890 /* ibm,drc-names */
dbd26f2f
SB
891 drc_name = spapr_drc_name(drc);
892 drc_names = g_string_append(drc_names, drc_name);
e4b798bb 893 drc_names = g_string_insert_len(drc_names, -1, "\0", 1);
dbd26f2f 894 g_free(drc_name);
e4b798bb
MR
895
896 /* ibm,drc-types */
1693ea16 897 drc_types = g_string_append(drc_types, drck->typename);
e4b798bb
MR
898 drc_types = g_string_insert_len(drc_types, -1, "\0", 1);
899 }
900
901 /* now write the drc count into the space we reserved at the
902 * beginning of the arrays previously
903 */
904 *(uint32_t *)drc_indexes->data = cpu_to_be32(drc_count);
905 *(uint32_t *)drc_power_domains->data = cpu_to_be32(drc_count);
906 *(uint32_t *)drc_names->str = cpu_to_be32(drc_count);
907 *(uint32_t *)drc_types->str = cpu_to_be32(drc_count);
908
9e7d38e8 909 ret = fdt_setprop(fdt, offset, "ibm,drc-indexes",
e4b798bb
MR
910 drc_indexes->data,
911 drc_indexes->len * sizeof(uint32_t));
912 if (ret) {
ce9863b7 913 error_report("Couldn't create ibm,drc-indexes property");
e4b798bb
MR
914 goto out;
915 }
916
9e7d38e8 917 ret = fdt_setprop(fdt, offset, "ibm,drc-power-domains",
e4b798bb
MR
918 drc_power_domains->data,
919 drc_power_domains->len * sizeof(uint32_t));
920 if (ret) {
ce9863b7 921 error_report("Couldn't finalize ibm,drc-power-domains property");
e4b798bb
MR
922 goto out;
923 }
924
9e7d38e8 925 ret = fdt_setprop(fdt, offset, "ibm,drc-names",
e4b798bb
MR
926 drc_names->str, drc_names->len);
927 if (ret) {
ce9863b7 928 error_report("Couldn't finalize ibm,drc-names property");
e4b798bb
MR
929 goto out;
930 }
931
9e7d38e8 932 ret = fdt_setprop(fdt, offset, "ibm,drc-types",
e4b798bb
MR
933 drc_types->str, drc_types->len);
934 if (ret) {
ce9863b7 935 error_report("Couldn't finalize ibm,drc-types property");
e4b798bb
MR
936 goto out;
937 }
938
939out:
940 g_array_free(drc_indexes, true);
941 g_array_free(drc_power_domains, true);
942 g_string_free(drc_names, true);
943 g_string_free(drc_types, true);
944
945 return ret;
946}
b89b3d39
DG
947
948/*
949 * RTAS calls
950 */
951
7b7258f8 952static uint32_t rtas_set_isolation_state(uint32_t idx, uint32_t state)
b89b3d39 953{
ce2918cb
DG
954 SpaprDrc *drc = spapr_drc_by_index(idx);
955 SpaprDrcClass *drck;
7b7258f8
DG
956
957 if (!drc) {
0dfabd39 958 return RTAS_OUT_NO_SUCH_INDICATOR;
b89b3d39
DG
959 }
960
0dfabd39
DG
961 trace_spapr_drc_set_isolation_state(spapr_drc_index(drc), state);
962
7b7258f8 963 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
0dfabd39
DG
964
965 switch (state) {
966 case SPAPR_DR_ISOLATION_STATE_ISOLATED:
967 return drck->isolate(drc);
968
969 case SPAPR_DR_ISOLATION_STATE_UNISOLATED:
970 return drck->unisolate(drc);
971
972 default:
973 return RTAS_OUT_PARAM_ERROR;
974 }
b89b3d39
DG
975}
976
7b7258f8 977static uint32_t rtas_set_allocation_state(uint32_t idx, uint32_t state)
b89b3d39 978{
ce2918cb 979 SpaprDrc *drc = spapr_drc_by_index(idx);
b89b3d39 980
61736732
DG
981 if (!drc || !object_dynamic_cast(OBJECT(drc), TYPE_SPAPR_DRC_LOGICAL)) {
982 return RTAS_OUT_NO_SUCH_INDICATOR;
b89b3d39
DG
983 }
984
61736732
DG
985 trace_spapr_drc_set_allocation_state(spapr_drc_index(drc), state);
986
987 switch (state) {
988 case SPAPR_DR_ALLOCATION_STATE_USABLE:
989 return drc_set_usable(drc);
990
991 case SPAPR_DR_ALLOCATION_STATE_UNUSABLE:
992 return drc_set_unusable(drc);
993
994 default:
995 return RTAS_OUT_PARAM_ERROR;
996 }
7b7258f8 997}
b89b3d39 998
cd74d27e 999static uint32_t rtas_set_dr_indicator(uint32_t idx, uint32_t state)
7b7258f8 1000{
ce2918cb 1001 SpaprDrc *drc = spapr_drc_by_index(idx);
b89b3d39 1002
67fea71b
DG
1003 if (!drc || !object_dynamic_cast(OBJECT(drc), TYPE_SPAPR_DRC_PHYSICAL)) {
1004 return RTAS_OUT_NO_SUCH_INDICATOR;
1005 }
1006 if ((state != SPAPR_DR_INDICATOR_INACTIVE)
1007 && (state != SPAPR_DR_INDICATOR_ACTIVE)
1008 && (state != SPAPR_DR_INDICATOR_IDENTIFY)
1009 && (state != SPAPR_DR_INDICATOR_ACTION)) {
1010 return RTAS_OUT_PARAM_ERROR; /* bad state parameter */
7b7258f8
DG
1011 }
1012
cd74d27e 1013 trace_spapr_drc_set_dr_indicator(idx, state);
67fea71b 1014 SPAPR_DRC_PHYSICAL(drc)->dr_indicator = state;
cd74d27e 1015 return RTAS_OUT_SUCCESS;
7b7258f8
DG
1016}
1017
ce2918cb 1018static void rtas_set_indicator(PowerPCCPU *cpu, SpaprMachineState *spapr,
7b7258f8
DG
1019 uint32_t token,
1020 uint32_t nargs, target_ulong args,
1021 uint32_t nret, target_ulong rets)
1022{
1023 uint32_t type, idx, state;
1024 uint32_t ret = RTAS_OUT_SUCCESS;
1025
1026 if (nargs != 3 || nret != 1) {
b89b3d39
DG
1027 ret = RTAS_OUT_PARAM_ERROR;
1028 goto out;
1029 }
b89b3d39 1030
7b7258f8
DG
1031 type = rtas_ld(args, 0);
1032 idx = rtas_ld(args, 1);
1033 state = rtas_ld(args, 2);
1034
1035 switch (type) {
b89b3d39 1036 case RTAS_SENSOR_TYPE_ISOLATION_STATE:
7b7258f8 1037 ret = rtas_set_isolation_state(idx, state);
b89b3d39
DG
1038 break;
1039 case RTAS_SENSOR_TYPE_DR:
cd74d27e 1040 ret = rtas_set_dr_indicator(idx, state);
b89b3d39
DG
1041 break;
1042 case RTAS_SENSOR_TYPE_ALLOCATION_STATE:
7b7258f8 1043 ret = rtas_set_allocation_state(idx, state);
b89b3d39
DG
1044 break;
1045 default:
7b7258f8 1046 ret = RTAS_OUT_NOT_SUPPORTED;
b89b3d39
DG
1047 }
1048
1049out:
1050 rtas_st(rets, 0, ret);
b89b3d39
DG
1051}
1052
ce2918cb 1053static void rtas_get_sensor_state(PowerPCCPU *cpu, SpaprMachineState *spapr,
b89b3d39
DG
1054 uint32_t token, uint32_t nargs,
1055 target_ulong args, uint32_t nret,
1056 target_ulong rets)
1057{
1058 uint32_t sensor_type;
1059 uint32_t sensor_index;
1060 uint32_t sensor_state = 0;
ce2918cb
DG
1061 SpaprDrc *drc;
1062 SpaprDrcClass *drck;
b89b3d39
DG
1063 uint32_t ret = RTAS_OUT_SUCCESS;
1064
1065 if (nargs != 2 || nret != 2) {
1066 ret = RTAS_OUT_PARAM_ERROR;
1067 goto out;
1068 }
1069
1070 sensor_type = rtas_ld(args, 0);
1071 sensor_index = rtas_ld(args, 1);
1072
1073 if (sensor_type != RTAS_SENSOR_TYPE_ENTITY_SENSE) {
1074 /* currently only DR-related sensors are implemented */
1075 trace_spapr_rtas_get_sensor_state_not_supported(sensor_index,
1076 sensor_type);
1077 ret = RTAS_OUT_NOT_SUPPORTED;
1078 goto out;
1079 }
1080
fbf55397 1081 drc = spapr_drc_by_index(sensor_index);
b89b3d39
DG
1082 if (!drc) {
1083 trace_spapr_rtas_get_sensor_state_invalid(sensor_index);
1084 ret = RTAS_OUT_PARAM_ERROR;
1085 goto out;
1086 }
1087 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
f224d35b 1088 sensor_state = drck->dr_entity_sense(drc);
b89b3d39
DG
1089
1090out:
1091 rtas_st(rets, 0, ret);
1092 rtas_st(rets, 1, sensor_state);
1093}
1094
1095/* configure-connector work area offsets, int32_t units for field
1096 * indexes, bytes for field offset/len values.
1097 *
1098 * as documented by PAPR+ v2.7, 13.5.3.5
1099 */
1100#define CC_IDX_NODE_NAME_OFFSET 2
1101#define CC_IDX_PROP_NAME_OFFSET 2
1102#define CC_IDX_PROP_LEN 3
1103#define CC_IDX_PROP_DATA_OFFSET 4
1104#define CC_VAL_DATA_OFFSET ((CC_IDX_PROP_DATA_OFFSET + 1) * 4)
1105#define CC_WA_LEN 4096
1106
1107static void configure_connector_st(target_ulong addr, target_ulong offset,
1108 const void *buf, size_t len)
1109{
1110 cpu_physical_memory_write(ppc64_phys_to_real(addr + offset),
1111 buf, MIN(len, CC_WA_LEN - offset));
1112}
1113
b89b3d39 1114static void rtas_ibm_configure_connector(PowerPCCPU *cpu,
ce2918cb 1115 SpaprMachineState *spapr,
b89b3d39
DG
1116 uint32_t token, uint32_t nargs,
1117 target_ulong args, uint32_t nret,
1118 target_ulong rets)
1119{
1120 uint64_t wa_addr;
1121 uint64_t wa_offset;
1122 uint32_t drc_index;
ce2918cb
DG
1123 SpaprDrc *drc;
1124 SpaprDrcClass *drck;
1125 SpaprDRCCResponse resp = SPAPR_DR_CC_RESPONSE_CONTINUE;
b89b3d39 1126 int rc;
b89b3d39
DG
1127
1128 if (nargs != 2 || nret != 1) {
1129 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
1130 return;
1131 }
1132
1133 wa_addr = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 0);
1134
1135 drc_index = rtas_ld(wa_addr, 0);
fbf55397 1136 drc = spapr_drc_by_index(drc_index);
b89b3d39
DG
1137 if (!drc) {
1138 trace_spapr_rtas_ibm_configure_connector_invalid(drc_index);
1139 rc = RTAS_OUT_PARAM_ERROR;
1140 goto out;
1141 }
1142
9d4c0f4f 1143 if ((drc->state != SPAPR_DRC_STATE_LOGICAL_UNISOLATE)
188bfe1b
BR
1144 && (drc->state != SPAPR_DRC_STATE_PHYSICAL_UNISOLATE)
1145 && (drc->state != SPAPR_DRC_STATE_LOGICAL_CONFIGURED)
1146 && (drc->state != SPAPR_DRC_STATE_PHYSICAL_CONFIGURED)) {
1147 /*
1148 * Need to unisolate the device before configuring
1149 * or it should already be in configured state to
1150 * allow configure-connector be called repeatedly.
1151 */
b89b3d39
DG
1152 rc = SPAPR_DR_CC_RESPONSE_NOT_CONFIGURABLE;
1153 goto out;
1154 }
1155
9d4c0f4f
DG
1156 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
1157
d9c95c71 1158 if (!drc->fdt) {
d9c95c71
GK
1159 void *fdt;
1160 int fdt_size;
1161
1162 fdt = create_device_tree(&fdt_size);
1163
1164 if (drck->dt_populate(drc, spapr, fdt, &drc->fdt_start_offset,
9261ef5e 1165 NULL)) {
d9c95c71 1166 g_free(fdt);
d9c95c71
GK
1167 rc = SPAPR_DR_CC_RESPONSE_ERROR;
1168 goto out;
1169 }
1170
1171 drc->fdt = fdt;
1172 drc->ccs_offset = drc->fdt_start_offset;
1173 drc->ccs_depth = 0;
1174 }
1175
b89b3d39
DG
1176 do {
1177 uint32_t tag;
1178 const char *name;
1179 const struct fdt_property *prop;
1180 int fdt_offset_next, prop_len;
1181
4445b1d2 1182 tag = fdt_next_tag(drc->fdt, drc->ccs_offset, &fdt_offset_next);
b89b3d39
DG
1183
1184 switch (tag) {
1185 case FDT_BEGIN_NODE:
4445b1d2
DG
1186 drc->ccs_depth++;
1187 name = fdt_get_name(drc->fdt, drc->ccs_offset, NULL);
b89b3d39
DG
1188
1189 /* provide the name of the next OF node */
1190 wa_offset = CC_VAL_DATA_OFFSET;
1191 rtas_st(wa_addr, CC_IDX_NODE_NAME_OFFSET, wa_offset);
1192 configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1);
1193 resp = SPAPR_DR_CC_RESPONSE_NEXT_CHILD;
1194 break;
1195 case FDT_END_NODE:
4445b1d2
DG
1196 drc->ccs_depth--;
1197 if (drc->ccs_depth == 0) {
0b55aa91 1198 uint32_t drc_index = spapr_drc_index(drc);
9d4c0f4f
DG
1199
1200 /* done sending the device tree, move to configured state */
0b55aa91 1201 trace_spapr_drc_set_configured(drc_index);
9d4c0f4f 1202 drc->state = drck->ready_state;
188bfe1b
BR
1203 /*
1204 * Ensure that we are able to send the FDT fragment
1205 * again via configure-connector call if the guest requests.
1206 */
1207 drc->ccs_offset = drc->fdt_start_offset;
1208 drc->ccs_depth = 0;
1209 fdt_offset_next = drc->fdt_start_offset;
b89b3d39
DG
1210 resp = SPAPR_DR_CC_RESPONSE_SUCCESS;
1211 } else {
1212 resp = SPAPR_DR_CC_RESPONSE_PREV_PARENT;
1213 }
1214 break;
1215 case FDT_PROP:
4445b1d2 1216 prop = fdt_get_property_by_offset(drc->fdt, drc->ccs_offset,
b89b3d39 1217 &prop_len);
88af6ea5 1218 name = fdt_string(drc->fdt, fdt32_to_cpu(prop->nameoff));
b89b3d39
DG
1219
1220 /* provide the name of the next OF property */
1221 wa_offset = CC_VAL_DATA_OFFSET;
1222 rtas_st(wa_addr, CC_IDX_PROP_NAME_OFFSET, wa_offset);
1223 configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1);
1224
1225 /* provide the length and value of the OF property. data gets
1226 * placed immediately after NULL terminator of the OF property's
1227 * name string
1228 */
1229 wa_offset += strlen(name) + 1,
1230 rtas_st(wa_addr, CC_IDX_PROP_LEN, prop_len);
1231 rtas_st(wa_addr, CC_IDX_PROP_DATA_OFFSET, wa_offset);
1232 configure_connector_st(wa_addr, wa_offset, prop->data, prop_len);
1233 resp = SPAPR_DR_CC_RESPONSE_NEXT_PROPERTY;
1234 break;
1235 case FDT_END:
1236 resp = SPAPR_DR_CC_RESPONSE_ERROR;
1237 default:
1238 /* keep seeking for an actionable tag */
1239 break;
1240 }
4445b1d2
DG
1241 if (drc->ccs_offset >= 0) {
1242 drc->ccs_offset = fdt_offset_next;
b89b3d39
DG
1243 }
1244 } while (resp == SPAPR_DR_CC_RESPONSE_CONTINUE);
1245
1246 rc = resp;
1247out:
1248 rtas_st(rets, 0, rc);
1249}
1250
1251static void spapr_drc_register_types(void)
1252{
1253 type_register_static(&spapr_dr_connector_info);
2d335818
DG
1254 type_register_static(&spapr_drc_physical_info);
1255 type_register_static(&spapr_drc_logical_info);
1256 type_register_static(&spapr_drc_cpu_info);
1257 type_register_static(&spapr_drc_pci_info);
1258 type_register_static(&spapr_drc_lmb_info);
962b6c36 1259 type_register_static(&spapr_drc_phb_info);
ee3a71e3 1260 type_register_static(&spapr_drc_pmem_info);
b89b3d39
DG
1261
1262 spapr_rtas_register(RTAS_SET_INDICATOR, "set-indicator",
1263 rtas_set_indicator);
1264 spapr_rtas_register(RTAS_GET_SENSOR_STATE, "get-sensor-state",
1265 rtas_get_sensor_state);
1266 spapr_rtas_register(RTAS_IBM_CONFIGURE_CONNECTOR, "ibm,configure-connector",
1267 rtas_ibm_configure_connector);
1268}
1269type_init(spapr_drc_register_types)