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iommu: Add IOMMU index argument to translate method
[mirror_qemu.git] / hw / ppc / spapr_iommu.c
CommitLineData
ad0ebb91
DG
1/*
2 * QEMU sPAPR IOMMU (TCE) code
3 *
4 * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
0d75590d 19#include "qemu/osdep.h"
df7625d4 20#include "qemu/error-report.h"
83c9f4ca 21#include "hw/hw.h"
03dd024f 22#include "qemu/log.h"
9c17d615 23#include "sysemu/kvm.h"
83c9f4ca 24#include "hw/qdev.h"
ad0ebb91 25#include "kvm_ppc.h"
9c17d615 26#include "sysemu/dma.h"
022c62cb 27#include "exec/address-spaces.h"
7e472264 28#include "trace.h"
ad0ebb91 29
0d09e41a 30#include "hw/ppc/spapr.h"
ee9a569a 31#include "hw/ppc/spapr_vio.h"
ad0ebb91
DG
32
33#include <libfdt.h>
34
ad0ebb91
DG
35enum sPAPRTCEAccess {
36 SPAPR_TCE_FAULT = 0,
37 SPAPR_TCE_RO = 1,
38 SPAPR_TCE_WO = 2,
39 SPAPR_TCE_RW = 3,
40};
41
650f33ad
AK
42#define IOMMU_PAGE_SIZE(shift) (1ULL << (shift))
43#define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1))
44
6a0a70b0 45static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables;
ad0ebb91 46
f9ce8e0a 47sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn)
ad0ebb91
DG
48{
49 sPAPRTCETable *tcet;
50
d4261662
DG
51 if (liobn & 0xFFFFFFFF00000000ULL) {
52 hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
53 liobn);
54 return NULL;
55 }
56
ad0ebb91 57 QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
f9ce8e0a 58 if (tcet->liobn == (uint32_t)liobn) {
ad0ebb91
DG
59 return tcet;
60 }
61 }
62
63 return NULL;
64}
65
5709af3b
GK
66static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce)
67{
68 switch (tce & SPAPR_TCE_RW) {
69 case SPAPR_TCE_FAULT:
70 return IOMMU_NONE;
71 case SPAPR_TCE_RO:
72 return IOMMU_RO;
73 case SPAPR_TCE_WO:
74 return IOMMU_WO;
75 default: /* SPAPR_TCE_RW */
76 return IOMMU_RW;
77 }
78}
79
fec5d3a1
AK
80static uint64_t *spapr_tce_alloc_table(uint32_t liobn,
81 uint32_t page_shift,
d6ee2a7c 82 uint64_t bus_offset,
fec5d3a1
AK
83 uint32_t nb_table,
84 int *fd,
85 bool need_vfio)
86{
87 uint64_t *table = NULL;
fec5d3a1 88
d6ee2a7c
AK
89 if (kvm_enabled()) {
90 table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table,
91 fd, need_vfio);
fec5d3a1
AK
92 }
93
94 if (!table) {
95 *fd = -1;
96 table = g_malloc0(nb_table * sizeof(uint64_t));
97 }
98
99 trace_spapr_iommu_new_table(liobn, table, *fd);
100
101 return table;
102}
103
104static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table)
105{
106 if (!kvm_enabled() ||
107 (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) {
108 g_free(table);
109 }
110}
111
79e2b9ae 112/* Called from RCU critical section */
3df9d748
AK
113static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu,
114 hwaddr addr,
2c91bcf2
PM
115 IOMMUAccessFlags flag,
116 int iommu_idx)
ad0ebb91 117{
a84bb436 118 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
ad0ebb91 119 uint64_t tce;
7e472264
AK
120 IOMMUTLBEntry ret = {
121 .target_as = &address_space_memory,
122 .iova = 0,
123 .translated_addr = 0,
124 .addr_mask = ~(hwaddr)0,
125 .perm = IOMMU_NONE,
126 };
ad0ebb91 127
ee9a569a 128 if ((addr >> tcet->page_shift) < tcet->nb_table) {
7e472264 129 /* Check if we are in bound */
650f33ad
AK
130 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
131
132 tce = tcet->table[addr >> tcet->page_shift];
133 ret.iova = addr & page_mask;
134 ret.translated_addr = tce & page_mask;
135 ret.addr_mask = ~page_mask;
5709af3b 136 ret.perm = spapr_tce_iommu_access_flags(tce);
ad0ebb91 137 }
7e472264
AK
138 trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm,
139 ret.addr_mask);
ad0ebb91 140
7e472264 141 return ret;
a71bfbfe
PB
142}
143
44b1ff31 144static int spapr_tce_table_pre_save(void *opaque)
a26fdf39
AK
145{
146 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
147
148 tcet->mig_table = tcet->table;
149 tcet->mig_nb_table = tcet->nb_table;
150
151 trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table,
152 tcet->bus_offset, tcet->page_shift);
44b1ff31
DDAG
153
154 return 0;
a26fdf39
AK
155}
156
3df9d748 157static uint64_t spapr_tce_get_min_page_size(IOMMUMemoryRegion *iommu)
f682e9c2
AK
158{
159 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
160
161 return 1ULL << tcet->page_shift;
162}
163
9ded780c
AK
164static int spapr_tce_get_attr(IOMMUMemoryRegion *iommu,
165 enum IOMMUMemoryRegionAttr attr, void *data)
166{
167 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
168
169 if (attr == IOMMU_ATTR_SPAPR_TCE_FD && kvmppc_has_cap_spapr_vfio()) {
170 *(int *) data = tcet->fd;
171 return 0;
172 }
173
174 return -EINVAL;
175}
176
3df9d748 177static void spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu,
5bf3d319
PX
178 IOMMUNotifierFlag old,
179 IOMMUNotifierFlag new)
606b5498 180{
5bf3d319 181 struct sPAPRTCETable *tbl = container_of(iommu, sPAPRTCETable, iommu);
606b5498 182
5bf3d319
PX
183 if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) {
184 spapr_tce_set_need_vfio(tbl, true);
185 } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) {
186 spapr_tce_set_need_vfio(tbl, false);
187 }
606b5498
AK
188}
189
ee9a569a
AK
190static int spapr_tce_table_post_load(void *opaque, int version_id)
191{
192 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
a26fdf39
AK
193 uint32_t old_nb_table = tcet->nb_table;
194 uint64_t old_bus_offset = tcet->bus_offset;
195 uint32_t old_page_shift = tcet->page_shift;
ee9a569a
AK
196
197 if (tcet->vdev) {
198 spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
199 }
200
a26fdf39
AK
201 if (tcet->mig_nb_table != tcet->nb_table) {
202 spapr_tce_table_disable(tcet);
203 }
204
205 if (tcet->mig_nb_table) {
206 if (!tcet->nb_table) {
207 spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset,
208 tcet->mig_nb_table);
209 }
210
211 memcpy(tcet->table, tcet->mig_table,
212 tcet->nb_table * sizeof(tcet->table[0]));
213
214 free(tcet->mig_table);
215 tcet->mig_table = NULL;
216 }
217
218 trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table,
219 tcet->bus_offset, tcet->page_shift);
220
ee9a569a
AK
221 return 0;
222}
223
a26fdf39
AK
224static bool spapr_tce_table_ex_needed(void *opaque)
225{
226 sPAPRTCETable *tcet = opaque;
227
228 return tcet->bus_offset || tcet->page_shift != 0xC;
229}
230
231static const VMStateDescription vmstate_spapr_tce_table_ex = {
232 .name = "spapr_iommu_ex",
233 .version_id = 1,
234 .minimum_version_id = 1,
235 .needed = spapr_tce_table_ex_needed,
236 .fields = (VMStateField[]) {
237 VMSTATE_UINT64(bus_offset, sPAPRTCETable),
238 VMSTATE_UINT32(page_shift, sPAPRTCETable),
239 VMSTATE_END_OF_LIST()
240 },
241};
242
a83000f5
AL
243static const VMStateDescription vmstate_spapr_tce_table = {
244 .name = "spapr_iommu",
523e7b8a
AK
245 .version_id = 2,
246 .minimum_version_id = 2,
a26fdf39 247 .pre_save = spapr_tce_table_pre_save,
ee9a569a 248 .post_load = spapr_tce_table_post_load,
523e7b8a 249 .fields = (VMStateField []) {
a83000f5 250 /* Sanity check */
d2164ad3 251 VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable, NULL),
a83000f5
AL
252
253 /* IOMMU state */
a26fdf39 254 VMSTATE_UINT32(mig_nb_table, sPAPRTCETable),
a83000f5 255 VMSTATE_BOOL(bypass, sPAPRTCETable),
a26fdf39
AK
256 VMSTATE_VARRAY_UINT32_ALLOC(mig_table, sPAPRTCETable, mig_nb_table, 0,
257 vmstate_info_uint64, uint64_t),
a83000f5
AL
258
259 VMSTATE_END_OF_LIST()
260 },
a26fdf39
AK
261 .subsections = (const VMStateDescription*[]) {
262 &vmstate_spapr_tce_table_ex,
263 NULL
264 }
a83000f5
AL
265};
266
a931ad13 267static void spapr_tce_table_realize(DeviceState *dev, Error **errp)
ad0ebb91 268{
a83000f5 269 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
b4b6eb77 270 Object *tcetobj = OBJECT(tcet);
a205a053 271 gchar *tmp;
ad0ebb91 272
fec5d3a1 273 tcet->fd = -1;
df7625d4 274 tcet->need_vfio = false;
a205a053 275 tmp = g_strdup_printf("tce-root-%x", tcet->liobn);
b4b6eb77 276 memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX);
a205a053 277 g_free(tmp);
b4b6eb77 278
a205a053 279 tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn);
1221a474
AK
280 memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu),
281 TYPE_SPAPR_IOMMU_MEMORY_REGION,
282 tcetobj, tmp, 0);
a205a053 283 g_free(tmp);
a84bb436 284
ad0ebb91
DG
285 QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
286
00d4f525
AK
287 vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table,
288 tcet);
a83000f5
AL
289}
290
c10325d6
DG
291void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio)
292{
293 size_t table_size = tcet->nb_table * sizeof(uint64_t);
f5509b6b
AK
294 uint64_t *oldtable;
295 int newfd = -1;
c10325d6 296
f5509b6b 297 g_assert(need_vfio != tcet->need_vfio);
c10325d6 298
f5509b6b 299 tcet->need_vfio = need_vfio;
c10325d6 300
9ded780c
AK
301 if (!need_vfio || (tcet->fd != -1 && kvmppc_has_cap_spapr_vfio())) {
302 return;
303 }
304
f5509b6b 305 oldtable = tcet->table;
c10325d6 306
f5509b6b
AK
307 tcet->table = spapr_tce_alloc_table(tcet->liobn,
308 tcet->page_shift,
309 tcet->bus_offset,
310 tcet->nb_table,
311 &newfd,
312 need_vfio);
313 memcpy(tcet->table, oldtable, table_size);
c10325d6 314
f5509b6b 315 spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table);
c10325d6 316
f5509b6b 317 tcet->fd = newfd;
c10325d6
DG
318}
319
df7625d4 320sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
a83000f5
AL
321{
322 sPAPRTCETable *tcet;
a205a053 323 gchar *tmp;
a83000f5
AL
324
325 if (spapr_tce_find_by_liobn(liobn)) {
ce9863b7
CLG
326 error_report("Attempted to create TCE table with duplicate"
327 " LIOBN 0x%x", liobn);
a83000f5
AL
328 return NULL;
329 }
330
a83000f5
AL
331 tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
332 tcet->liobn = liobn;
a83000f5 333
a205a053 334 tmp = g_strdup_printf("tce-table-%x", liobn);
dea1b3ce 335 object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL);
a205a053 336 g_free(tmp);
8dc9785c 337 object_unref(OBJECT(tcet));
a83000f5 338
e4c35b78 339 object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
a83000f5 340
2b7dc949 341 return tcet;
ad0ebb91
DG
342}
343
df7625d4
AK
344void spapr_tce_table_enable(sPAPRTCETable *tcet,
345 uint32_t page_shift, uint64_t bus_offset,
346 uint32_t nb_table)
347{
348 if (tcet->nb_table) {
3dc6f869 349 warn_report("trying to enable already enabled TCE table");
df7625d4
AK
350 return;
351 }
352
353 tcet->bus_offset = bus_offset;
354 tcet->page_shift = page_shift;
355 tcet->nb_table = nb_table;
356 tcet->table = spapr_tce_alloc_table(tcet->liobn,
357 tcet->page_shift,
d6ee2a7c 358 tcet->bus_offset,
df7625d4
AK
359 tcet->nb_table,
360 &tcet->fd,
361 tcet->need_vfio);
362
3df9d748 363 memory_region_set_size(MEMORY_REGION(&tcet->iommu),
df7625d4 364 (uint64_t)tcet->nb_table << tcet->page_shift);
3df9d748
AK
365 memory_region_add_subregion(&tcet->root, tcet->bus_offset,
366 MEMORY_REGION(&tcet->iommu));
df7625d4
AK
367}
368
a26fdf39 369void spapr_tce_table_disable(sPAPRTCETable *tcet)
df7625d4
AK
370{
371 if (!tcet->nb_table) {
372 return;
373 }
374
3df9d748
AK
375 memory_region_del_subregion(&tcet->root, MEMORY_REGION(&tcet->iommu));
376 memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0);
df7625d4
AK
377
378 spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table);
379 tcet->fd = -1;
380 tcet->table = NULL;
381 tcet->bus_offset = 0;
382 tcet->page_shift = 0;
383 tcet->nb_table = 0;
384}
385
5f9490de 386static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
ad0ebb91 387{
5f9490de 388 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
a83000f5 389
ea359d20
GK
390 vmstate_unregister(DEVICE(tcet), &vmstate_spapr_tce_table, tcet);
391
2b7dc949 392 QLIST_REMOVE(tcet, list);
ad0ebb91 393
df7625d4 394 spapr_tce_table_disable(tcet);
ad0ebb91
DG
395}
396
a84bb436
PB
397MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet)
398{
b4b6eb77 399 return &tcet->root;
a84bb436
PB
400}
401
a83000f5 402static void spapr_tce_reset(DeviceState *dev)
eddeed26 403{
a83000f5 404 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
523e7b8a 405 size_t table_size = tcet->nb_table * sizeof(uint64_t);
eddeed26 406
57c0eb1e
DG
407 if (tcet->nb_table) {
408 memset(tcet->table, 0, table_size);
409 }
eddeed26
DG
410}
411
edded454
DG
412static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
413 target_ulong tce)
414{
a84bb436 415 IOMMUTLBEntry entry;
650f33ad 416 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
1b8eceee 417 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
edded454 418
1b8eceee 419 if (index >= tcet->nb_table) {
b55519a0 420 hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
edded454
DG
421 TARGET_FMT_lx "\n", ioba);
422 return H_PARAMETER;
423 }
424
1b8eceee 425 tcet->table[index] = tce;
edded454 426
a84bb436 427 entry.target_as = &address_space_memory,
d78c19b5 428 entry.iova = (ioba - tcet->bus_offset) & page_mask;
650f33ad
AK
429 entry.translated_addr = tce & page_mask;
430 entry.addr_mask = ~page_mask;
5709af3b 431 entry.perm = spapr_tce_iommu_access_flags(tce);
cb1efcf4 432 memory_region_notify_iommu(&tcet->iommu, 0, entry);
a84bb436 433
edded454
DG
434 return H_SUCCESS;
435}
ad0ebb91 436
da95324e 437static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
28e02042 438 sPAPRMachineState *spapr,
da95324e
AK
439 target_ulong opcode, target_ulong *args)
440{
441 int i;
442 target_ulong liobn = args[0];
443 target_ulong ioba = args[1];
444 target_ulong ioba1 = ioba;
445 target_ulong tce_list = args[2];
446 target_ulong npages = args[3];
f1215ea7 447 target_ulong ret = H_PARAMETER, tce = 0;
da95324e
AK
448 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
449 CPUState *cs = CPU(cpu);
650f33ad 450 hwaddr page_mask, page_size;
da95324e
AK
451
452 if (!tcet) {
453 return H_PARAMETER;
454 }
455
650f33ad 456 if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
da95324e
AK
457 return H_PARAMETER;
458 }
459
650f33ad
AK
460 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
461 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
462 ioba &= page_mask;
463
464 for (i = 0; i < npages; ++i, ioba += page_size) {
4d9ab7d4 465 tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
da95324e 466
da95324e
AK
467 ret = put_tce_emu(tcet, ioba, tce);
468 if (ret) {
469 break;
470 }
471 }
472
473 /* Trace last successful or the first problematic entry */
474 i = i ? (i - 1) : 0;
d9d96a3c
AK
475 if (SPAPR_IS_PCI_LIOBN(liobn)) {
476 trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
477 } else {
478 trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
479 }
da95324e
AK
480 return ret;
481}
482
28e02042 483static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
da95324e
AK
484 target_ulong opcode, target_ulong *args)
485{
486 int i;
487 target_ulong liobn = args[0];
488 target_ulong ioba = args[1];
489 target_ulong tce_value = args[2];
490 target_ulong npages = args[3];
491 target_ulong ret = H_PARAMETER;
492 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
650f33ad 493 hwaddr page_mask, page_size;
da95324e
AK
494
495 if (!tcet) {
496 return H_PARAMETER;
497 }
498
499 if (npages > tcet->nb_table) {
500 return H_PARAMETER;
501 }
502
650f33ad
AK
503 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
504 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
505 ioba &= page_mask;
da95324e 506
650f33ad 507 for (i = 0; i < npages; ++i, ioba += page_size) {
da95324e
AK
508 ret = put_tce_emu(tcet, ioba, tce_value);
509 if (ret) {
510 break;
511 }
512 }
d9d96a3c
AK
513 if (SPAPR_IS_PCI_LIOBN(liobn)) {
514 trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
515 } else {
516 trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
517 }
da95324e
AK
518
519 return ret;
520}
521
28e02042 522static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
ad0ebb91
DG
523 target_ulong opcode, target_ulong *args)
524{
525 target_ulong liobn = args[0];
526 target_ulong ioba = args[1];
527 target_ulong tce = args[2];
7e472264 528 target_ulong ret = H_PARAMETER;
ad0ebb91 529 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
ad0ebb91 530
edded454 531 if (tcet) {
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532 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
533
534 ioba &= page_mask;
535
7e472264 536 ret = put_tce_emu(tcet, ioba, tce);
edded454 537 }
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538 if (SPAPR_IS_PCI_LIOBN(liobn)) {
539 trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
540 } else {
541 trace_spapr_iommu_put(liobn, ioba, tce, ret);
542 }
ad0ebb91 543
7e472264 544 return ret;
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DG
545}
546
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547static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
548 target_ulong *tce)
549{
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550 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
551
552 if (index >= tcet->nb_table) {
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553 hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
554 TARGET_FMT_lx "\n", ioba);
555 return H_PARAMETER;
556 }
557
1b8eceee 558 *tce = tcet->table[index];
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LD
559
560 return H_SUCCESS;
561}
562
28e02042 563static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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LD
564 target_ulong opcode, target_ulong *args)
565{
566 target_ulong liobn = args[0];
567 target_ulong ioba = args[1];
568 target_ulong tce = 0;
569 target_ulong ret = H_PARAMETER;
570 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
571
a0fcac9c 572 if (tcet) {
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573 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
574
575 ioba &= page_mask;
576
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577 ret = get_tce_emu(tcet, ioba, &tce);
578 if (!ret) {
579 args[0] = tce;
580 }
581 }
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582 if (SPAPR_IS_PCI_LIOBN(liobn)) {
583 trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
584 } else {
585 trace_spapr_iommu_get(liobn, ioba, ret, tce);
586 }
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587
588 return ret;
589}
590
ad0ebb91 591int spapr_dma_dt(void *fdt, int node_off, const char *propname,
5c4cbcf2 592 uint32_t liobn, uint64_t window, uint32_t size)
ad0ebb91 593{
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594 uint32_t dma_prop[5];
595 int ret;
596
597 dma_prop[0] = cpu_to_be32(liobn);
598 dma_prop[1] = cpu_to_be32(window >> 32);
599 dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
600 dma_prop[3] = 0; /* window size is 32 bits */
601 dma_prop[4] = cpu_to_be32(size);
602
603 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
604 if (ret < 0) {
605 return ret;
606 }
ad0ebb91 607
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608 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
609 if (ret < 0) {
610 return ret;
611 }
ad0ebb91 612
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613 ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
614 if (ret < 0) {
615 return ret;
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616 }
617
618 return 0;
619}
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620
621int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
2b7dc949 622 sPAPRTCETable *tcet)
5c4cbcf2 623{
2b7dc949 624 if (!tcet) {
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625 return 0;
626 }
627
2b7dc949 628 return spapr_dma_dt(fdt, node_off, propname,
650f33ad 629 tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
5c4cbcf2 630}
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AL
631
632static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
633{
634 DeviceClass *dc = DEVICE_CLASS(klass);
a931ad13 635 dc->realize = spapr_tce_table_realize;
a83000f5 636 dc->reset = spapr_tce_reset;
5f9490de 637 dc->unrealize = spapr_tce_table_unrealize;
1f98e553
TH
638 /* Reason: This is just an internal device for handling the hypercalls */
639 dc->user_creatable = false;
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AL
640
641 QLIST_INIT(&spapr_tce_tables);
642
643 /* hcall-tce */
644 spapr_register_hypercall(H_PUT_TCE, h_put_tce);
a0fcac9c 645 spapr_register_hypercall(H_GET_TCE, h_get_tce);
da95324e
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646 spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
647 spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
a83000f5
AL
648}
649
650static TypeInfo spapr_tce_table_info = {
651 .name = TYPE_SPAPR_TCE_TABLE,
652 .parent = TYPE_DEVICE,
653 .instance_size = sizeof(sPAPRTCETable),
654 .class_init = spapr_tce_table_class_init,
a83000f5
AL
655};
656
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657static void spapr_iommu_memory_region_class_init(ObjectClass *klass, void *data)
658{
659 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
660
661 imrc->translate = spapr_tce_translate_iommu;
662 imrc->get_min_page_size = spapr_tce_get_min_page_size;
663 imrc->notify_flag_changed = spapr_tce_notify_flag_changed;
9ded780c 664 imrc->get_attr = spapr_tce_get_attr;
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AK
665}
666
667static const TypeInfo spapr_iommu_memory_region_info = {
668 .parent = TYPE_IOMMU_MEMORY_REGION,
669 .name = TYPE_SPAPR_IOMMU_MEMORY_REGION,
670 .class_init = spapr_iommu_memory_region_class_init,
671};
672
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AL
673static void register_types(void)
674{
675 type_register_static(&spapr_tce_table_info);
1221a474 676 type_register_static(&spapr_iommu_memory_region_info);
a83000f5
AL
677}
678
679type_init(register_types);