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Commit | Line | Data |
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3384f95c DG |
1 | /* |
2 | * QEMU sPAPR PCI host originated from Uninorth PCI host | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. | |
5 | * Copyright (C) 2011 David Gibson, IBM Corporation. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
0b8fa32f | 25 | |
0d75590d | 26 | #include "qemu/osdep.h" |
da34e65c | 27 | #include "qapi/error.h" |
4771d756 | 28 | #include "cpu.h" |
64552b6b | 29 | #include "hw/irq.h" |
1d2d9742 | 30 | #include "hw/sysbus.h" |
d6454270 | 31 | #include "migration/vmstate.h" |
83c9f4ca PB |
32 | #include "hw/pci/pci.h" |
33 | #include "hw/pci/msi.h" | |
34 | #include "hw/pci/msix.h" | |
35 | #include "hw/pci/pci_host.h" | |
0d09e41a PB |
36 | #include "hw/ppc/spapr.h" |
37 | #include "hw/pci-host/spapr.h" | |
022c62cb | 38 | #include "exec/address-spaces.h" |
ae4de14c | 39 | #include "exec/ram_addr.h" |
3384f95c | 40 | #include <libfdt.h> |
a2950fb6 | 41 | #include "trace.h" |
295d51aa | 42 | #include "qemu/error-report.h" |
0b8fa32f | 43 | #include "qemu/module.h" |
7454c7af | 44 | #include "qapi/qmp/qerror.h" |
99372e78 | 45 | #include "hw/ppc/fdt.h" |
1d2d9742 | 46 | #include "hw/pci/pci_bridge.h" |
06aac7bd | 47 | #include "hw/pci/pci_bus.h" |
2530a1a5 | 48 | #include "hw/pci/pci_ids.h" |
62083979 | 49 | #include "hw/ppc/spapr_drc.h" |
a27bd6c7 | 50 | #include "hw/qdev-properties.h" |
7454c7af | 51 | #include "sysemu/device_tree.h" |
77ac58dd | 52 | #include "sysemu/kvm.h" |
ae4de14c | 53 | #include "sysemu/hostmem.h" |
4814401f | 54 | #include "sysemu/numa.h" |
3384f95c | 55 | |
0ee2c058 AK |
56 | /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ |
57 | #define RTAS_QUERY_FN 0 | |
58 | #define RTAS_CHANGE_FN 1 | |
59 | #define RTAS_RESET_FN 2 | |
60 | #define RTAS_CHANGE_MSI_FN 3 | |
61 | #define RTAS_CHANGE_MSIX_FN 4 | |
62 | ||
63 | /* Interrupt types to return on RTAS_CHANGE_* */ | |
64 | #define RTAS_TYPE_MSI 1 | |
65 | #define RTAS_TYPE_MSIX 2 | |
66 | ||
ce2918cb | 67 | SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid) |
3384f95c | 68 | { |
ce2918cb | 69 | SpaprPhbState *sphb; |
3384f95c | 70 | |
8c9f64df AF |
71 | QLIST_FOREACH(sphb, &spapr->phbs, list) { |
72 | if (sphb->buid != buid) { | |
3384f95c DG |
73 | continue; |
74 | } | |
8c9f64df | 75 | return sphb; |
9894c5d4 AK |
76 | } |
77 | ||
78 | return NULL; | |
79 | } | |
80 | ||
ce2918cb | 81 | PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid, |
46c5874e | 82 | uint32_t config_addr) |
9894c5d4 | 83 | { |
ce2918cb | 84 | SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid); |
8558d942 | 85 | PCIHostState *phb = PCI_HOST_BRIDGE(sphb); |
5dac82ce | 86 | int bus_num = (config_addr >> 16) & 0xFF; |
9894c5d4 AK |
87 | int devfn = (config_addr >> 8) & 0xFF; |
88 | ||
89 | if (!phb) { | |
90 | return NULL; | |
91 | } | |
3384f95c | 92 | |
5dac82ce | 93 | return pci_find_device(phb->bus, bus_num, devfn); |
3384f95c DG |
94 | } |
95 | ||
3f7565c9 BH |
96 | static uint32_t rtas_pci_cfgaddr(uint32_t arg) |
97 | { | |
92615a5a | 98 | /* This handles the encoding of extended config space addresses */ |
3f7565c9 BH |
99 | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
100 | } | |
101 | ||
ce2918cb | 102 | static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid, |
92615a5a DG |
103 | uint32_t addr, uint32_t size, |
104 | target_ulong rets) | |
88045ac5 | 105 | { |
92615a5a DG |
106 | PCIDevice *pci_dev; |
107 | uint32_t val; | |
108 | ||
109 | if ((size != 1) && (size != 2) && (size != 4)) { | |
110 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 111 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 112 | return; |
88045ac5 | 113 | } |
88045ac5 | 114 | |
46c5874e | 115 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
116 | addr = rtas_pci_cfgaddr(addr); |
117 | ||
118 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
119 | /* Access must be to a valid device, within bounds and | |
120 | * naturally aligned */ | |
a64d325d | 121 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a | 122 | return; |
88045ac5 | 123 | } |
92615a5a DG |
124 | |
125 | val = pci_host_config_read_common(pci_dev, addr, | |
126 | pci_config_size(pci_dev), size); | |
127 | ||
a64d325d | 128 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
92615a5a | 129 | rtas_st(rets, 1, val); |
88045ac5 AG |
130 | } |
131 | ||
ce2918cb | 132 | static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, |
3384f95c DG |
133 | uint32_t token, uint32_t nargs, |
134 | target_ulong args, | |
135 | uint32_t nret, target_ulong rets) | |
136 | { | |
92615a5a DG |
137 | uint64_t buid; |
138 | uint32_t size, addr; | |
3384f95c | 139 | |
92615a5a | 140 | if ((nargs != 4) || (nret != 2)) { |
a64d325d | 141 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
142 | return; |
143 | } | |
92615a5a | 144 | |
a14aa92b | 145 | buid = rtas_ldq(args, 1); |
3384f95c | 146 | size = rtas_ld(args, 3); |
92615a5a DG |
147 | addr = rtas_ld(args, 0); |
148 | ||
149 | finish_read_pci_config(spapr, buid, addr, size, rets); | |
3384f95c DG |
150 | } |
151 | ||
ce2918cb | 152 | static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, |
3384f95c DG |
153 | uint32_t token, uint32_t nargs, |
154 | target_ulong args, | |
155 | uint32_t nret, target_ulong rets) | |
156 | { | |
92615a5a | 157 | uint32_t size, addr; |
3384f95c | 158 | |
92615a5a | 159 | if ((nargs != 2) || (nret != 2)) { |
a64d325d | 160 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
161 | return; |
162 | } | |
92615a5a | 163 | |
3384f95c | 164 | size = rtas_ld(args, 1); |
92615a5a DG |
165 | addr = rtas_ld(args, 0); |
166 | ||
167 | finish_read_pci_config(spapr, 0, addr, size, rets); | |
168 | } | |
169 | ||
ce2918cb | 170 | static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid, |
92615a5a DG |
171 | uint32_t addr, uint32_t size, |
172 | uint32_t val, target_ulong rets) | |
173 | { | |
174 | PCIDevice *pci_dev; | |
175 | ||
176 | if ((size != 1) && (size != 2) && (size != 4)) { | |
177 | /* access must be 1, 2 or 4 bytes */ | |
a64d325d | 178 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
179 | return; |
180 | } | |
181 | ||
46c5874e | 182 | pci_dev = spapr_pci_find_dev(spapr, buid, addr); |
92615a5a DG |
183 | addr = rtas_pci_cfgaddr(addr); |
184 | ||
185 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
186 | /* Access must be to a valid device, within bounds and | |
187 | * naturally aligned */ | |
a64d325d | 188 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
92615a5a DG |
189 | return; |
190 | } | |
191 | ||
192 | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), | |
193 | val, size); | |
194 | ||
a64d325d | 195 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
3384f95c DG |
196 | } |
197 | ||
ce2918cb | 198 | static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, |
3384f95c DG |
199 | uint32_t token, uint32_t nargs, |
200 | target_ulong args, | |
201 | uint32_t nret, target_ulong rets) | |
202 | { | |
92615a5a | 203 | uint64_t buid; |
3384f95c | 204 | uint32_t val, size, addr; |
3384f95c | 205 | |
92615a5a | 206 | if ((nargs != 5) || (nret != 1)) { |
a64d325d | 207 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
208 | return; |
209 | } | |
92615a5a | 210 | |
a14aa92b | 211 | buid = rtas_ldq(args, 1); |
3384f95c DG |
212 | val = rtas_ld(args, 4); |
213 | size = rtas_ld(args, 3); | |
92615a5a DG |
214 | addr = rtas_ld(args, 0); |
215 | ||
216 | finish_write_pci_config(spapr, buid, addr, size, val, rets); | |
3384f95c DG |
217 | } |
218 | ||
ce2918cb | 219 | static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, |
3384f95c DG |
220 | uint32_t token, uint32_t nargs, |
221 | target_ulong args, | |
222 | uint32_t nret, target_ulong rets) | |
223 | { | |
224 | uint32_t val, size, addr; | |
3384f95c | 225 | |
92615a5a | 226 | if ((nargs != 3) || (nret != 1)) { |
a64d325d | 227 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
3384f95c DG |
228 | return; |
229 | } | |
92615a5a DG |
230 | |
231 | ||
3384f95c DG |
232 | val = rtas_ld(args, 2); |
233 | size = rtas_ld(args, 1); | |
92615a5a DG |
234 | addr = rtas_ld(args, 0); |
235 | ||
236 | finish_write_pci_config(spapr, 0, addr, size, val, rets); | |
3384f95c DG |
237 | } |
238 | ||
0ee2c058 AK |
239 | /* |
240 | * Set MSI/MSIX message data. | |
241 | * This is required for msi_notify()/msix_notify() which | |
242 | * will write at the addresses via spapr_msi_write(). | |
9a321e92 AK |
243 | * |
244 | * If hwaddr == 0, all entries will have .data == first_irq i.e. | |
245 | * table will be reset. | |
0ee2c058 | 246 | */ |
f1c2dc7c AK |
247 | static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, |
248 | unsigned first_irq, unsigned req_num) | |
0ee2c058 AK |
249 | { |
250 | unsigned i; | |
f1c2dc7c | 251 | MSIMessage msg = { .address = addr, .data = first_irq }; |
0ee2c058 AK |
252 | |
253 | if (!msix) { | |
254 | msi_set_message(pdev, msg); | |
255 | trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); | |
256 | return; | |
257 | } | |
258 | ||
9a321e92 | 259 | for (i = 0; i < req_num; ++i) { |
0ee2c058 AK |
260 | msix_set_message(pdev, i, msg); |
261 | trace_spapr_pci_msi_setup(pdev->name, i, msg.address); | |
9a321e92 AK |
262 | if (addr) { |
263 | ++msg.data; | |
264 | } | |
0ee2c058 AK |
265 | } |
266 | } | |
267 | ||
ce2918cb | 268 | static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr, |
0ee2c058 AK |
269 | uint32_t token, uint32_t nargs, |
270 | target_ulong args, uint32_t nret, | |
271 | target_ulong rets) | |
272 | { | |
ce2918cb | 273 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
0ee2c058 | 274 | uint32_t config_addr = rtas_ld(args, 0); |
a14aa92b | 275 | uint64_t buid = rtas_ldq(args, 1); |
0ee2c058 AK |
276 | unsigned int func = rtas_ld(args, 3); |
277 | unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ | |
278 | unsigned int seq_num = rtas_ld(args, 5); | |
279 | unsigned int ret_intr_type; | |
d4a63ac8 | 280 | unsigned int irq, max_irqs = 0; |
ce2918cb | 281 | SpaprPhbState *phb = NULL; |
0ee2c058 | 282 | PCIDevice *pdev = NULL; |
572ebd08 | 283 | SpaprPciMsi *msi; |
9a321e92 | 284 | int *config_addr_key; |
a005b3ef | 285 | Error *err = NULL; |
4fe75a8c | 286 | int i; |
0ee2c058 | 287 | |
ce2918cb | 288 | /* Fins SpaprPhbState */ |
9cbe305b GK |
289 | phb = spapr_pci_find_phb(spapr, buid); |
290 | if (phb) { | |
291 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); | |
292 | } | |
293 | if (!phb || !pdev) { | |
294 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
295 | return; | |
296 | } | |
297 | ||
0ee2c058 | 298 | switch (func) { |
0ee2c058 | 299 | case RTAS_CHANGE_FN: |
9cbe305b GK |
300 | if (msi_present(pdev)) { |
301 | ret_intr_type = RTAS_TYPE_MSI; | |
302 | } else if (msix_present(pdev)) { | |
303 | ret_intr_type = RTAS_TYPE_MSIX; | |
304 | } else { | |
305 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
306 | return; | |
307 | } | |
308 | break; | |
309 | case RTAS_CHANGE_MSI_FN: | |
310 | if (msi_present(pdev)) { | |
311 | ret_intr_type = RTAS_TYPE_MSI; | |
312 | } else { | |
313 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
314 | return; | |
315 | } | |
0ee2c058 AK |
316 | break; |
317 | case RTAS_CHANGE_MSIX_FN: | |
9cbe305b GK |
318 | if (msix_present(pdev)) { |
319 | ret_intr_type = RTAS_TYPE_MSIX; | |
320 | } else { | |
321 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
322 | return; | |
323 | } | |
0ee2c058 AK |
324 | break; |
325 | default: | |
295d51aa | 326 | error_report("rtas_ibm_change_msi(%u) is not implemented", func); |
a64d325d | 327 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
328 | return; |
329 | } | |
330 | ||
572ebd08 | 331 | msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); |
ce266b75 | 332 | |
0ee2c058 AK |
333 | /* Releasing MSIs */ |
334 | if (!req_num) { | |
9a321e92 AK |
335 | if (!msi) { |
336 | trace_spapr_pci_msi("Releasing wrong config", config_addr); | |
a64d325d | 337 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
338 | return; |
339 | } | |
9a321e92 | 340 | |
32420522 | 341 | if (msi_present(pdev)) { |
d4a63ac8 | 342 | spapr_msi_setmsg(pdev, 0, false, 0, 0); |
32420522 AK |
343 | } |
344 | if (msix_present(pdev)) { | |
d4a63ac8 | 345 | spapr_msi_setmsg(pdev, 0, true, 0, 0); |
32420522 | 346 | } |
9a321e92 AK |
347 | g_hash_table_remove(phb->msi, &config_addr); |
348 | ||
349 | trace_spapr_pci_msi("Released MSIs", config_addr); | |
a64d325d | 350 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
351 | rtas_st(rets, 1, 0); |
352 | return; | |
353 | } | |
354 | ||
355 | /* Enabling MSI */ | |
356 | ||
28668b5f AK |
357 | /* Check if the device supports as many IRQs as requested */ |
358 | if (ret_intr_type == RTAS_TYPE_MSI) { | |
359 | max_irqs = msi_nr_vectors_allocated(pdev); | |
360 | } else if (ret_intr_type == RTAS_TYPE_MSIX) { | |
361 | max_irqs = pdev->msix_entries_nr; | |
362 | } | |
363 | if (!max_irqs) { | |
9a321e92 AK |
364 | error_report("Requested interrupt type %d is not enabled for device %x", |
365 | ret_intr_type, config_addr); | |
28668b5f AK |
366 | rtas_st(rets, 0, -1); /* Hardware error */ |
367 | return; | |
368 | } | |
369 | /* Correct the number if the guest asked for too many */ | |
370 | if (req_num > max_irqs) { | |
9a321e92 | 371 | trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); |
28668b5f | 372 | req_num = max_irqs; |
9a321e92 AK |
373 | irq = 0; /* to avoid misleading trace */ |
374 | goto out; | |
28668b5f AK |
375 | } |
376 | ||
9a321e92 | 377 | /* Allocate MSIs */ |
2c88b098 | 378 | if (smc->legacy_irq_allocation) { |
82cffa2e CLG |
379 | irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI, |
380 | &err); | |
381 | } else { | |
382 | irq = spapr_irq_msi_alloc(spapr, req_num, | |
383 | ret_intr_type == RTAS_TYPE_MSI, &err); | |
384 | } | |
a005b3ef GK |
385 | if (err) { |
386 | error_reportf_err(err, "Can't allocate MSIs for device %x: ", | |
387 | config_addr); | |
a64d325d | 388 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
389 | return; |
390 | } | |
391 | ||
4fe75a8c CLG |
392 | for (i = 0; i < req_num; i++) { |
393 | spapr_irq_claim(spapr, irq + i, false, &err); | |
394 | if (err) { | |
925969c3 GK |
395 | if (i) { |
396 | spapr_irq_free(spapr, irq, i); | |
397 | } | |
398 | if (!smc->legacy_irq_allocation) { | |
399 | spapr_irq_msi_free(spapr, irq, req_num); | |
400 | } | |
4fe75a8c CLG |
401 | error_reportf_err(err, "Can't allocate MSIs for device %x: ", |
402 | config_addr); | |
403 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); | |
404 | return; | |
405 | } | |
406 | } | |
407 | ||
ce266b75 GK |
408 | /* Release previous MSIs */ |
409 | if (msi) { | |
ce266b75 GK |
410 | g_hash_table_remove(phb->msi, &config_addr); |
411 | } | |
412 | ||
0ee2c058 | 413 | /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ |
8c46f7ec | 414 | spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, |
9a321e92 | 415 | irq, req_num); |
0ee2c058 | 416 | |
9a321e92 | 417 | /* Add MSI device to cache */ |
572ebd08 | 418 | msi = g_new(SpaprPciMsi, 1); |
9a321e92 AK |
419 | msi->first_irq = irq; |
420 | msi->num = req_num; | |
421 | config_addr_key = g_new(int, 1); | |
422 | *config_addr_key = config_addr; | |
423 | g_hash_table_insert(phb->msi, config_addr_key, msi); | |
424 | ||
425 | out: | |
a64d325d | 426 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
427 | rtas_st(rets, 1, req_num); |
428 | rtas_st(rets, 2, ++seq_num); | |
b359bd6a SB |
429 | if (nret > 3) { |
430 | rtas_st(rets, 3, ret_intr_type); | |
431 | } | |
0ee2c058 | 432 | |
9a321e92 | 433 | trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); |
0ee2c058 AK |
434 | } |
435 | ||
210b580b | 436 | static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, |
ce2918cb | 437 | SpaprMachineState *spapr, |
0ee2c058 AK |
438 | uint32_t token, |
439 | uint32_t nargs, | |
440 | target_ulong args, | |
441 | uint32_t nret, | |
442 | target_ulong rets) | |
443 | { | |
444 | uint32_t config_addr = rtas_ld(args, 0); | |
a14aa92b | 445 | uint64_t buid = rtas_ldq(args, 1); |
0ee2c058 | 446 | unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); |
ce2918cb | 447 | SpaprPhbState *phb = NULL; |
9a321e92 | 448 | PCIDevice *pdev = NULL; |
572ebd08 | 449 | SpaprPciMsi *msi; |
0ee2c058 | 450 | |
ce2918cb | 451 | /* Find SpaprPhbState */ |
46c5874e | 452 | phb = spapr_pci_find_phb(spapr, buid); |
9a321e92 | 453 | if (phb) { |
46c5874e | 454 | pdev = spapr_pci_find_dev(spapr, buid, config_addr); |
9a321e92 AK |
455 | } |
456 | if (!phb || !pdev) { | |
a64d325d | 457 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
0ee2c058 AK |
458 | return; |
459 | } | |
460 | ||
461 | /* Find device descriptor and start IRQ */ | |
572ebd08 | 462 | msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); |
9a321e92 AK |
463 | if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { |
464 | trace_spapr_pci_msi("Failed to return vector", config_addr); | |
a64d325d | 465 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
0ee2c058 AK |
466 | return; |
467 | } | |
9a321e92 | 468 | intr_src_num = msi->first_irq + ioa_intr_num; |
0ee2c058 AK |
469 | trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, |
470 | intr_src_num); | |
471 | ||
a64d325d | 472 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
0ee2c058 AK |
473 | rtas_st(rets, 1, intr_src_num); |
474 | rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ | |
475 | } | |
476 | ||
ee954280 | 477 | static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, |
ce2918cb | 478 | SpaprMachineState *spapr, |
ee954280 GS |
479 | uint32_t token, uint32_t nargs, |
480 | target_ulong args, uint32_t nret, | |
481 | target_ulong rets) | |
482 | { | |
ce2918cb | 483 | SpaprPhbState *sphb; |
ee954280 GS |
484 | uint32_t addr, option; |
485 | uint64_t buid; | |
486 | int ret; | |
487 | ||
488 | if ((nargs != 4) || (nret != 1)) { | |
489 | goto param_error_exit; | |
490 | } | |
491 | ||
a14aa92b | 492 | buid = rtas_ldq(args, 1); |
ee954280 GS |
493 | addr = rtas_ld(args, 0); |
494 | option = rtas_ld(args, 3); | |
495 | ||
46c5874e | 496 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
497 | if (!sphb) { |
498 | goto param_error_exit; | |
499 | } | |
500 | ||
fbb4e983 | 501 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
502 | goto param_error_exit; |
503 | } | |
504 | ||
fbb4e983 | 505 | ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option); |
ee954280 GS |
506 | rtas_st(rets, 0, ret); |
507 | return; | |
508 | ||
509 | param_error_exit: | |
510 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
511 | } | |
512 | ||
513 | static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, | |
ce2918cb | 514 | SpaprMachineState *spapr, |
ee954280 GS |
515 | uint32_t token, uint32_t nargs, |
516 | target_ulong args, uint32_t nret, | |
517 | target_ulong rets) | |
518 | { | |
ce2918cb | 519 | SpaprPhbState *sphb; |
ee954280 GS |
520 | PCIDevice *pdev; |
521 | uint32_t addr, option; | |
522 | uint64_t buid; | |
523 | ||
524 | if ((nargs != 4) || (nret != 2)) { | |
525 | goto param_error_exit; | |
526 | } | |
527 | ||
a14aa92b | 528 | buid = rtas_ldq(args, 1); |
46c5874e | 529 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
530 | if (!sphb) { |
531 | goto param_error_exit; | |
532 | } | |
533 | ||
fbb4e983 | 534 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
535 | goto param_error_exit; |
536 | } | |
537 | ||
538 | /* | |
539 | * We always have PE address of form "00BB0001". "BB" | |
540 | * represents the bus number of PE's primary bus. | |
541 | */ | |
542 | option = rtas_ld(args, 3); | |
543 | switch (option) { | |
544 | case RTAS_GET_PE_ADDR: | |
545 | addr = rtas_ld(args, 0); | |
46c5874e | 546 | pdev = spapr_pci_find_dev(spapr, buid, addr); |
ee954280 GS |
547 | if (!pdev) { |
548 | goto param_error_exit; | |
549 | } | |
550 | ||
fd56e061 | 551 | rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1); |
ee954280 GS |
552 | break; |
553 | case RTAS_GET_PE_MODE: | |
554 | rtas_st(rets, 1, RTAS_PE_MODE_SHARED); | |
555 | break; | |
556 | default: | |
557 | goto param_error_exit; | |
558 | } | |
559 | ||
560 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
561 | return; | |
562 | ||
563 | param_error_exit: | |
564 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
565 | } | |
566 | ||
567 | static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, | |
ce2918cb | 568 | SpaprMachineState *spapr, |
ee954280 GS |
569 | uint32_t token, uint32_t nargs, |
570 | target_ulong args, uint32_t nret, | |
571 | target_ulong rets) | |
572 | { | |
ce2918cb | 573 | SpaprPhbState *sphb; |
ee954280 GS |
574 | uint64_t buid; |
575 | int state, ret; | |
576 | ||
577 | if ((nargs != 3) || (nret != 4 && nret != 5)) { | |
578 | goto param_error_exit; | |
579 | } | |
580 | ||
a14aa92b | 581 | buid = rtas_ldq(args, 1); |
46c5874e | 582 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
583 | if (!sphb) { |
584 | goto param_error_exit; | |
585 | } | |
586 | ||
fbb4e983 | 587 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
588 | goto param_error_exit; |
589 | } | |
590 | ||
fbb4e983 | 591 | ret = spapr_phb_vfio_eeh_get_state(sphb, &state); |
ee954280 GS |
592 | rtas_st(rets, 0, ret); |
593 | if (ret != RTAS_OUT_SUCCESS) { | |
594 | return; | |
595 | } | |
596 | ||
597 | rtas_st(rets, 1, state); | |
598 | rtas_st(rets, 2, RTAS_EEH_SUPPORT); | |
599 | rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); | |
600 | if (nret >= 5) { | |
601 | rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); | |
602 | } | |
603 | return; | |
604 | ||
605 | param_error_exit: | |
606 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
607 | } | |
608 | ||
609 | static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, | |
ce2918cb | 610 | SpaprMachineState *spapr, |
ee954280 GS |
611 | uint32_t token, uint32_t nargs, |
612 | target_ulong args, uint32_t nret, | |
613 | target_ulong rets) | |
614 | { | |
ce2918cb | 615 | SpaprPhbState *sphb; |
ee954280 GS |
616 | uint32_t option; |
617 | uint64_t buid; | |
618 | int ret; | |
619 | ||
620 | if ((nargs != 4) || (nret != 1)) { | |
621 | goto param_error_exit; | |
622 | } | |
623 | ||
a14aa92b | 624 | buid = rtas_ldq(args, 1); |
ee954280 | 625 | option = rtas_ld(args, 3); |
46c5874e | 626 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
627 | if (!sphb) { |
628 | goto param_error_exit; | |
629 | } | |
630 | ||
fbb4e983 | 631 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
632 | goto param_error_exit; |
633 | } | |
634 | ||
fbb4e983 | 635 | ret = spapr_phb_vfio_eeh_reset(sphb, option); |
ee954280 GS |
636 | rtas_st(rets, 0, ret); |
637 | return; | |
638 | ||
639 | param_error_exit: | |
640 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
641 | } | |
642 | ||
643 | static void rtas_ibm_configure_pe(PowerPCCPU *cpu, | |
ce2918cb | 644 | SpaprMachineState *spapr, |
ee954280 GS |
645 | uint32_t token, uint32_t nargs, |
646 | target_ulong args, uint32_t nret, | |
647 | target_ulong rets) | |
648 | { | |
ce2918cb | 649 | SpaprPhbState *sphb; |
ee954280 GS |
650 | uint64_t buid; |
651 | int ret; | |
652 | ||
653 | if ((nargs != 3) || (nret != 1)) { | |
654 | goto param_error_exit; | |
655 | } | |
656 | ||
a14aa92b | 657 | buid = rtas_ldq(args, 1); |
46c5874e | 658 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
659 | if (!sphb) { |
660 | goto param_error_exit; | |
661 | } | |
662 | ||
fbb4e983 | 663 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
664 | goto param_error_exit; |
665 | } | |
666 | ||
fbb4e983 | 667 | ret = spapr_phb_vfio_eeh_configure(sphb); |
ee954280 GS |
668 | rtas_st(rets, 0, ret); |
669 | return; | |
670 | ||
671 | param_error_exit: | |
672 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
673 | } | |
674 | ||
675 | /* To support it later */ | |
676 | static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, | |
ce2918cb | 677 | SpaprMachineState *spapr, |
ee954280 GS |
678 | uint32_t token, uint32_t nargs, |
679 | target_ulong args, uint32_t nret, | |
680 | target_ulong rets) | |
681 | { | |
ce2918cb | 682 | SpaprPhbState *sphb; |
ee954280 GS |
683 | int option; |
684 | uint64_t buid; | |
685 | ||
686 | if ((nargs != 8) || (nret != 1)) { | |
687 | goto param_error_exit; | |
688 | } | |
689 | ||
a14aa92b | 690 | buid = rtas_ldq(args, 1); |
46c5874e | 691 | sphb = spapr_pci_find_phb(spapr, buid); |
ee954280 GS |
692 | if (!sphb) { |
693 | goto param_error_exit; | |
694 | } | |
695 | ||
fbb4e983 | 696 | if (!spapr_phb_eeh_available(sphb)) { |
ee954280 GS |
697 | goto param_error_exit; |
698 | } | |
699 | ||
700 | option = rtas_ld(args, 7); | |
701 | switch (option) { | |
702 | case RTAS_SLOT_TEMP_ERR_LOG: | |
703 | case RTAS_SLOT_PERM_ERR_LOG: | |
704 | break; | |
705 | default: | |
706 | goto param_error_exit; | |
707 | } | |
708 | ||
709 | /* We don't have error log yet */ | |
710 | rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); | |
711 | return; | |
712 | ||
713 | param_error_exit: | |
714 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
715 | } | |
716 | ||
3384f95c DG |
717 | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) |
718 | { | |
719 | /* | |
e8ec4adf | 720 | * Here we use the number returned by pci_swizzle_map_irq_fn to find a |
3384f95c DG |
721 | * corresponding qemu_irq. |
722 | */ | |
ce2918cb | 723 | SpaprPhbState *phb = opaque; |
258aa5ce | 724 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
3384f95c | 725 | |
caae58cb | 726 | trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); |
258aa5ce | 727 | qemu_set_irq(spapr_qirq(spapr, phb->lsi_table[irq_num].irq), level); |
3384f95c DG |
728 | } |
729 | ||
5cc7a967 AK |
730 | static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) |
731 | { | |
ce2918cb | 732 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); |
5cc7a967 AK |
733 | PCIINTxRoute route; |
734 | ||
735 | route.mode = PCI_INTX_ENABLED; | |
736 | route.irq = sphb->lsi_table[pin].irq; | |
737 | ||
738 | return route; | |
739 | } | |
740 | ||
0ee2c058 AK |
741 | /* |
742 | * MSI/MSIX memory region implementation. | |
743 | * The handler handles both MSI and MSIX. | |
18f2330e | 744 | * The vector number is encoded in least bits in data. |
0ee2c058 | 745 | */ |
a8170e5e | 746 | static void spapr_msi_write(void *opaque, hwaddr addr, |
0ee2c058 AK |
747 | uint64_t data, unsigned size) |
748 | { | |
ce2918cb | 749 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
f1c2dc7c | 750 | uint32_t irq = data; |
0ee2c058 AK |
751 | |
752 | trace_spapr_pci_msi_write(addr, data, irq); | |
753 | ||
77183755 | 754 | qemu_irq_pulse(spapr_qirq(spapr, irq)); |
0ee2c058 AK |
755 | } |
756 | ||
757 | static const MemoryRegionOps spapr_msi_ops = { | |
758 | /* There is no .read as the read result is undefined by PCI spec */ | |
759 | .read = NULL, | |
760 | .write = spapr_msi_write, | |
761 | .endianness = DEVICE_LITTLE_ENDIAN | |
762 | }; | |
763 | ||
298a9710 DG |
764 | /* |
765 | * PHB PCI device | |
766 | */ | |
e00387d5 | 767 | static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
edded454 | 768 | { |
ce2918cb | 769 | SpaprPhbState *phb = opaque; |
edded454 | 770 | |
e00387d5 | 771 | return &phb->iommu_as; |
edded454 DG |
772 | } |
773 | ||
ce2918cb | 774 | static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) |
16b0ea1d ND |
775 | { |
776 | char *path = NULL, *buf = NULL, *host = NULL; | |
777 | ||
778 | /* Get the PCI VFIO host id */ | |
779 | host = object_property_get_str(OBJECT(pdev), "host", NULL); | |
780 | if (!host) { | |
781 | goto err_out; | |
782 | } | |
783 | ||
784 | /* Construct the path of the file that will give us the DT location */ | |
785 | path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); | |
786 | g_free(host); | |
8f687605 | 787 | if (!g_file_get_contents(path, &buf, NULL, NULL)) { |
16b0ea1d ND |
788 | goto err_out; |
789 | } | |
790 | g_free(path); | |
791 | ||
792 | /* Construct and read from host device tree the loc-code */ | |
793 | path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); | |
794 | g_free(buf); | |
8f687605 | 795 | if (!g_file_get_contents(path, &buf, NULL, NULL)) { |
16b0ea1d ND |
796 | goto err_out; |
797 | } | |
798 | return buf; | |
799 | ||
800 | err_out: | |
801 | g_free(path); | |
802 | return NULL; | |
803 | } | |
804 | ||
ce2918cb | 805 | static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) |
16b0ea1d ND |
806 | { |
807 | char *buf; | |
808 | const char *devtype = "qemu"; | |
809 | uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); | |
810 | ||
811 | if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { | |
812 | buf = spapr_phb_vfio_get_loc_code(sphb, pdev); | |
813 | if (buf) { | |
814 | return buf; | |
815 | } | |
816 | devtype = "vfio"; | |
817 | } | |
818 | /* | |
819 | * For emulated devices and VFIO-failure case, make up | |
820 | * the loc-code. | |
821 | */ | |
822 | buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", | |
823 | devtype, pdev->name, sphb->index, busnr, | |
824 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
825 | return buf; | |
826 | } | |
827 | ||
7454c7af MR |
828 | /* Macros to operate with address in OF binding to PCI */ |
829 | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) | |
830 | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ | |
831 | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ | |
832 | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ | |
833 | #define b_ss(x) b_x((x), 24, 2) /* the space code */ | |
834 | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ | |
835 | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ | |
836 | #define b_fff(x) b_x((x), 8, 3) /* function number */ | |
837 | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ | |
838 | ||
c4ec08ab | 839 | /* for 'reg' OF properties */ |
7454c7af MR |
840 | #define RESOURCE_CELLS_SIZE 2 |
841 | #define RESOURCE_CELLS_ADDRESS 3 | |
842 | ||
843 | typedef struct ResourceFields { | |
844 | uint32_t phys_hi; | |
845 | uint32_t phys_mid; | |
846 | uint32_t phys_lo; | |
847 | uint32_t size_hi; | |
848 | uint32_t size_lo; | |
849 | } QEMU_PACKED ResourceFields; | |
850 | ||
851 | typedef struct ResourceProps { | |
852 | ResourceFields reg[8]; | |
7454c7af | 853 | uint32_t reg_len; |
7454c7af MR |
854 | } ResourceProps; |
855 | ||
c4ec08ab | 856 | /* fill in the 'reg' OF properties for |
7454c7af | 857 | * a PCI device. 'reg' describes resource requirements for a |
c4ec08ab | 858 | * device's IO/MEM regions. |
7454c7af | 859 | * |
c4ec08ab | 860 | * the property is an array of ('phys-addr', 'size') pairs describing |
7454c7af MR |
861 | * the addressable regions of the PCI device, where 'phys-addr' is a |
862 | * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to | |
863 | * (phys.hi, phys.mid, phys.lo), and 'size' is a | |
864 | * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). | |
865 | * | |
866 | * phys.hi = 0xYYXXXXZZ, where: | |
867 | * 0xYY = npt000ss | |
868 | * ||| | | |
72187935 ND |
869 | * ||| +-- space code |
870 | * ||| | | |
871 | * ||| + 00 if configuration space | |
872 | * ||| + 01 if IO region, | |
873 | * ||| + 10 if 32-bit MEM region | |
874 | * ||| + 11 if 64-bit MEM region | |
875 | * ||| | |
7454c7af MR |
876 | * ||+------ for non-relocatable IO: 1 if aliased |
877 | * || for relocatable IO: 1 if below 64KB | |
878 | * || for MEM: 1 if below 1MB | |
879 | * |+------- 1 if region is prefetchable | |
880 | * +-------- 1 if region is non-relocatable | |
881 | * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function | |
882 | * bits respectively | |
883 | * 0xZZ = rrrrrrrr, the register number of the BAR corresponding | |
884 | * to the region | |
885 | * | |
886 | * phys.mid and phys.lo correspond respectively to the hi/lo portions | |
887 | * of the actual address of the region. | |
888 | * | |
c4ec08ab | 889 | * note also that addresses defined in this property are, at least |
7454c7af MR |
890 | * for PAPR guests, relative to the PHBs IO/MEM windows, and |
891 | * correspond directly to the addresses in the BARs. | |
892 | * | |
893 | * in accordance with PCI Bus Binding to Open Firmware, | |
894 | * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, | |
895 | * Appendix C. | |
896 | */ | |
897 | static void populate_resource_props(PCIDevice *d, ResourceProps *rp) | |
898 | { | |
899 | int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); | |
900 | uint32_t dev_id = (b_bbbbbbbb(bus_num) | | |
901 | b_ddddd(PCI_SLOT(d->devfn)) | | |
902 | b_fff(PCI_FUNC(d->devfn))); | |
c4ec08ab AK |
903 | ResourceFields *reg; |
904 | int i, reg_idx = 0; | |
7454c7af MR |
905 | |
906 | /* config space region */ | |
907 | reg = &rp->reg[reg_idx++]; | |
908 | reg->phys_hi = cpu_to_be32(dev_id); | |
909 | reg->phys_mid = 0; | |
910 | reg->phys_lo = 0; | |
911 | reg->size_hi = 0; | |
912 | reg->size_lo = 0; | |
913 | ||
914 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
915 | if (!d->io_regions[i].size) { | |
916 | continue; | |
917 | } | |
918 | ||
919 | reg = &rp->reg[reg_idx++]; | |
920 | ||
921 | reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); | |
922 | if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { | |
923 | reg->phys_hi |= cpu_to_be32(b_ss(1)); | |
72187935 ND |
924 | } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
925 | reg->phys_hi |= cpu_to_be32(b_ss(3)); | |
7454c7af MR |
926 | } else { |
927 | reg->phys_hi |= cpu_to_be32(b_ss(2)); | |
928 | } | |
929 | reg->phys_mid = 0; | |
930 | reg->phys_lo = 0; | |
931 | reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); | |
932 | reg->size_lo = cpu_to_be32(d->io_regions[i].size); | |
7454c7af MR |
933 | } |
934 | ||
935 | rp->reg_len = reg_idx * sizeof(ResourceFields); | |
7454c7af MR |
936 | } |
937 | ||
2530a1a5 LV |
938 | typedef struct PCIClass PCIClass; |
939 | typedef struct PCISubClass PCISubClass; | |
940 | typedef struct PCIIFace PCIIFace; | |
941 | ||
942 | struct PCIIFace { | |
943 | int iface; | |
944 | const char *name; | |
945 | }; | |
946 | ||
947 | struct PCISubClass { | |
948 | int subclass; | |
949 | const char *name; | |
950 | const PCIIFace *iface; | |
951 | }; | |
952 | ||
953 | struct PCIClass { | |
954 | const char *name; | |
955 | const PCISubClass *subc; | |
956 | }; | |
957 | ||
958 | static const PCISubClass undef_subclass[] = { | |
959 | { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL }, | |
960 | { 0xFF, NULL, NULL }, | |
961 | }; | |
962 | ||
963 | static const PCISubClass mass_subclass[] = { | |
964 | { PCI_CLASS_STORAGE_SCSI, "scsi", NULL }, | |
965 | { PCI_CLASS_STORAGE_IDE, "ide", NULL }, | |
966 | { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL }, | |
967 | { PCI_CLASS_STORAGE_IPI, "ipi", NULL }, | |
968 | { PCI_CLASS_STORAGE_RAID, "raid", NULL }, | |
969 | { PCI_CLASS_STORAGE_ATA, "ata", NULL }, | |
970 | { PCI_CLASS_STORAGE_SATA, "sata", NULL }, | |
971 | { PCI_CLASS_STORAGE_SAS, "sas", NULL }, | |
972 | { 0xFF, NULL, NULL }, | |
973 | }; | |
974 | ||
975 | static const PCISubClass net_subclass[] = { | |
976 | { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL }, | |
977 | { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL }, | |
978 | { PCI_CLASS_NETWORK_FDDI, "fddi", NULL }, | |
979 | { PCI_CLASS_NETWORK_ATM, "atm", NULL }, | |
980 | { PCI_CLASS_NETWORK_ISDN, "isdn", NULL }, | |
981 | { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL }, | |
982 | { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL }, | |
983 | { 0xFF, NULL, NULL }, | |
984 | }; | |
985 | ||
986 | static const PCISubClass displ_subclass[] = { | |
987 | { PCI_CLASS_DISPLAY_VGA, "vga", NULL }, | |
988 | { PCI_CLASS_DISPLAY_XGA, "xga", NULL }, | |
989 | { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL }, | |
990 | { 0xFF, NULL, NULL }, | |
991 | }; | |
992 | ||
993 | static const PCISubClass media_subclass[] = { | |
994 | { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL }, | |
995 | { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL }, | |
996 | { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL }, | |
997 | { 0xFF, NULL, NULL }, | |
998 | }; | |
999 | ||
1000 | static const PCISubClass mem_subclass[] = { | |
1001 | { PCI_CLASS_MEMORY_RAM, "memory", NULL }, | |
1002 | { PCI_CLASS_MEMORY_FLASH, "flash", NULL }, | |
1003 | { 0xFF, NULL, NULL }, | |
1004 | }; | |
1005 | ||
1006 | static const PCISubClass bridg_subclass[] = { | |
1007 | { PCI_CLASS_BRIDGE_HOST, "host", NULL }, | |
1008 | { PCI_CLASS_BRIDGE_ISA, "isa", NULL }, | |
1009 | { PCI_CLASS_BRIDGE_EISA, "eisa", NULL }, | |
1010 | { PCI_CLASS_BRIDGE_MC, "mca", NULL }, | |
1011 | { PCI_CLASS_BRIDGE_PCI, "pci", NULL }, | |
1012 | { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL }, | |
1013 | { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL }, | |
1014 | { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL }, | |
1015 | { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL }, | |
1016 | { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL }, | |
1017 | { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL }, | |
1018 | { 0xFF, NULL, NULL }, | |
1019 | }; | |
1020 | ||
1021 | static const PCISubClass comm_subclass[] = { | |
1022 | { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL }, | |
1023 | { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL }, | |
1024 | { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL }, | |
1025 | { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL }, | |
1026 | { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL }, | |
1027 | { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL }, | |
1028 | { 0xFF, NULL, NULL, }, | |
1029 | }; | |
1030 | ||
1031 | static const PCIIFace pic_iface[] = { | |
1032 | { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" }, | |
1033 | { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" }, | |
1034 | { 0xFF, NULL }, | |
1035 | }; | |
1036 | ||
1037 | static const PCISubClass sys_subclass[] = { | |
1038 | { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface }, | |
1039 | { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL }, | |
1040 | { PCI_CLASS_SYSTEM_TIMER, "timer", NULL }, | |
1041 | { PCI_CLASS_SYSTEM_RTC, "rtc", NULL }, | |
1042 | { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL }, | |
1043 | { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL }, | |
1044 | { 0xFF, NULL, NULL }, | |
1045 | }; | |
1046 | ||
1047 | static const PCISubClass inp_subclass[] = { | |
1048 | { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL }, | |
1049 | { PCI_CLASS_INPUT_PEN, "pen", NULL }, | |
1050 | { PCI_CLASS_INPUT_MOUSE, "mouse", NULL }, | |
1051 | { PCI_CLASS_INPUT_SCANNER, "scanner", NULL }, | |
1052 | { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL }, | |
1053 | { 0xFF, NULL, NULL }, | |
1054 | }; | |
1055 | ||
1056 | static const PCISubClass dock_subclass[] = { | |
1057 | { PCI_CLASS_DOCKING_GENERIC, "dock", NULL }, | |
1058 | { 0xFF, NULL, NULL }, | |
1059 | }; | |
1060 | ||
1061 | static const PCISubClass cpu_subclass[] = { | |
1062 | { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL }, | |
1063 | { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL }, | |
1064 | { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL }, | |
1065 | { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL }, | |
1066 | { 0xFF, NULL, NULL }, | |
1067 | }; | |
1068 | ||
1069 | static const PCIIFace usb_iface[] = { | |
1070 | { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" }, | |
1071 | { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", }, | |
1072 | { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" }, | |
1073 | { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" }, | |
1074 | { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" }, | |
1075 | { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" }, | |
1076 | { 0xFF, NULL }, | |
1077 | }; | |
1078 | ||
1079 | static const PCISubClass ser_subclass[] = { | |
1080 | { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL }, | |
1081 | { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL }, | |
1082 | { PCI_CLASS_SERIAL_SSA, "ssa", NULL }, | |
1083 | { PCI_CLASS_SERIAL_USB, "usb", usb_iface }, | |
1084 | { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL }, | |
1085 | { PCI_CLASS_SERIAL_SMBUS, "smb", NULL }, | |
1086 | { PCI_CLASS_SERIAL_IB, "infiniband", NULL }, | |
1087 | { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL }, | |
1088 | { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL }, | |
1089 | { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL }, | |
1090 | { 0xFF, NULL, NULL }, | |
1091 | }; | |
1092 | ||
1093 | static const PCISubClass wrl_subclass[] = { | |
1094 | { PCI_CLASS_WIRELESS_IRDA, "irda", NULL }, | |
1095 | { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL }, | |
1096 | { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL }, | |
1097 | { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL }, | |
1098 | { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL }, | |
1099 | { 0xFF, NULL, NULL }, | |
1100 | }; | |
1101 | ||
1102 | static const PCISubClass sat_subclass[] = { | |
1103 | { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL }, | |
1104 | { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL }, | |
1105 | { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL }, | |
1106 | { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL }, | |
1107 | { 0xFF, NULL, NULL }, | |
1108 | }; | |
1109 | ||
1110 | static const PCISubClass crypt_subclass[] = { | |
1111 | { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL }, | |
1112 | { PCI_CLASS_CRYPT_ENTERTAINMENT, | |
1113 | "entertainment-encryption", NULL }, | |
1114 | { 0xFF, NULL, NULL }, | |
1115 | }; | |
1116 | ||
1117 | static const PCISubClass spc_subclass[] = { | |
1118 | { PCI_CLASS_SP_DPIO, "dpio", NULL }, | |
1119 | { PCI_CLASS_SP_PERF, "counter", NULL }, | |
1120 | { PCI_CLASS_SP_SYNCH, "measurement", NULL }, | |
1121 | { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL }, | |
1122 | { 0xFF, NULL, NULL }, | |
1123 | }; | |
1124 | ||
1125 | static const PCIClass pci_classes[] = { | |
1126 | { "legacy-device", undef_subclass }, | |
1127 | { "mass-storage", mass_subclass }, | |
1128 | { "network", net_subclass }, | |
1129 | { "display", displ_subclass, }, | |
1130 | { "multimedia-device", media_subclass }, | |
1131 | { "memory-controller", mem_subclass }, | |
1132 | { "unknown-bridge", bridg_subclass }, | |
1133 | { "communication-controller", comm_subclass}, | |
1134 | { "system-peripheral", sys_subclass }, | |
1135 | { "input-controller", inp_subclass }, | |
1136 | { "docking-station", dock_subclass }, | |
1137 | { "cpu", cpu_subclass }, | |
1138 | { "serial-bus", ser_subclass }, | |
1139 | { "wireless-controller", wrl_subclass }, | |
1140 | { "intelligent-io", NULL }, | |
1141 | { "satellite-device", sat_subclass }, | |
1142 | { "encryption", crypt_subclass }, | |
1143 | { "data-processing-controller", spc_subclass }, | |
1144 | }; | |
1145 | ||
4782a8bb DG |
1146 | static const char *dt_name_from_class(uint8_t class, uint8_t subclass, |
1147 | uint8_t iface) | |
2530a1a5 LV |
1148 | { |
1149 | const PCIClass *pclass; | |
1150 | const PCISubClass *psubclass; | |
1151 | const PCIIFace *piface; | |
1152 | const char *name; | |
1153 | ||
1154 | if (class >= ARRAY_SIZE(pci_classes)) { | |
1155 | return "pci"; | |
1156 | } | |
1157 | ||
1158 | pclass = pci_classes + class; | |
1159 | name = pclass->name; | |
1160 | ||
1161 | if (pclass->subc == NULL) { | |
1162 | return name; | |
1163 | } | |
1164 | ||
1165 | psubclass = pclass->subc; | |
1166 | while ((psubclass->subclass & 0xff) != 0xff) { | |
1167 | if ((psubclass->subclass & 0xff) == subclass) { | |
1168 | name = psubclass->name; | |
1169 | break; | |
1170 | } | |
1171 | psubclass++; | |
1172 | } | |
1173 | ||
1174 | piface = psubclass->iface; | |
1175 | if (piface == NULL) { | |
1176 | return name; | |
1177 | } | |
1178 | while ((piface->iface & 0xff) != 0xff) { | |
1179 | if ((piface->iface & 0xff) == iface) { | |
1180 | name = piface->name; | |
1181 | break; | |
1182 | } | |
1183 | piface++; | |
1184 | } | |
1185 | ||
1186 | return name; | |
1187 | } | |
1188 | ||
a1ec25b2 DG |
1189 | /* |
1190 | * DRC helper functions | |
1191 | */ | |
1192 | ||
1193 | static uint32_t drc_id_from_devfn(SpaprPhbState *phb, | |
05929a6c | 1194 | uint8_t chassis, int32_t devfn) |
2530a1a5 | 1195 | { |
05929a6c | 1196 | return (phb->index << 16) | (chassis << 8) | devfn; |
a1ec25b2 | 1197 | } |
2530a1a5 | 1198 | |
a1ec25b2 | 1199 | static SpaprDrc *drc_from_devfn(SpaprPhbState *phb, |
05929a6c | 1200 | uint8_t chassis, int32_t devfn) |
a1ec25b2 DG |
1201 | { |
1202 | return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI, | |
05929a6c DG |
1203 | drc_id_from_devfn(phb, chassis, devfn)); |
1204 | } | |
2530a1a5 | 1205 | |
05929a6c DG |
1206 | static uint8_t chassis_from_bus(PCIBus *bus, Error **errp) |
1207 | { | |
1208 | if (pci_bus_is_root(bus)) { | |
1209 | return 0; | |
1210 | } else { | |
1211 | PCIDevice *bridge = pci_bridge_get_device(bus); | |
1212 | ||
1213 | return object_property_get_uint(OBJECT(bridge), "chassis_nr", errp); | |
1214 | } | |
a1ec25b2 DG |
1215 | } |
1216 | ||
1217 | static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev) | |
1218 | { | |
05929a6c DG |
1219 | Error *local_err = NULL; |
1220 | uint8_t chassis = chassis_from_bus(pci_get_bus(dev), &local_err); | |
1221 | ||
1222 | if (local_err) { | |
1223 | error_report_err(local_err); | |
1224 | return NULL; | |
1225 | } | |
1226 | ||
1227 | return drc_from_devfn(phb, chassis, dev->devfn); | |
a1ec25b2 DG |
1228 | } |
1229 | ||
14e71490 | 1230 | static void add_drcs(SpaprPhbState *phb, PCIBus *bus, Error **errp) |
a1ec25b2 | 1231 | { |
14e71490 | 1232 | Object *owner; |
a1ec25b2 | 1233 | int i; |
14e71490 DG |
1234 | uint8_t chassis; |
1235 | Error *local_err = NULL; | |
a1ec25b2 DG |
1236 | |
1237 | if (!phb->dr_enabled) { | |
1238 | return; | |
1239 | } | |
1240 | ||
14e71490 DG |
1241 | chassis = chassis_from_bus(bus, &local_err); |
1242 | if (local_err) { | |
1243 | error_propagate(errp, local_err); | |
1244 | return; | |
1245 | } | |
1246 | ||
1247 | if (pci_bus_is_root(bus)) { | |
1248 | owner = OBJECT(phb); | |
2530a1a5 | 1249 | } else { |
14e71490 DG |
1250 | owner = OBJECT(pci_bridge_get_device(bus)); |
1251 | } | |
1252 | ||
a1ec25b2 | 1253 | for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) { |
14e71490 DG |
1254 | spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI, |
1255 | drc_id_from_devfn(phb, chassis, i)); | |
a1ec25b2 DG |
1256 | } |
1257 | } | |
1258 | ||
14e71490 | 1259 | static void remove_drcs(SpaprPhbState *phb, PCIBus *bus, Error **errp) |
a1ec25b2 DG |
1260 | { |
1261 | int i; | |
14e71490 DG |
1262 | uint8_t chassis; |
1263 | Error *local_err = NULL; | |
a1ec25b2 DG |
1264 | |
1265 | if (!phb->dr_enabled) { | |
1266 | return; | |
1267 | } | |
1268 | ||
14e71490 DG |
1269 | chassis = chassis_from_bus(bus, &local_err); |
1270 | if (local_err) { | |
1271 | error_propagate(errp, local_err); | |
1272 | return; | |
1273 | } | |
1274 | ||
a1ec25b2 | 1275 | for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) { |
14e71490 | 1276 | SpaprDrc *drc = drc_from_devfn(phb, chassis, i); |
a1ec25b2 DG |
1277 | |
1278 | if (drc) { | |
1279 | object_unparent(OBJECT(drc)); | |
1280 | } | |
2530a1a5 LV |
1281 | } |
1282 | } | |
1283 | ||
466e8831 DG |
1284 | typedef struct PciWalkFdt { |
1285 | void *fdt; | |
1286 | int offset; | |
1287 | SpaprPhbState *sphb; | |
1288 | int err; | |
1289 | } PciWalkFdt; | |
1290 | ||
1291 | static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, | |
1292 | void *fdt, int parent_offset); | |
1293 | ||
1294 | static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev, | |
1295 | void *opaque) | |
1296 | { | |
1297 | PciWalkFdt *p = opaque; | |
1298 | int err; | |
1299 | ||
1300 | if (p->err) { | |
1301 | /* Something's already broken, don't keep going */ | |
1302 | return; | |
1303 | } | |
1304 | ||
1305 | err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset); | |
1306 | if (err < 0) { | |
1307 | p->err = err; | |
1308 | } | |
1309 | } | |
1310 | ||
1311 | /* Augment PCI device node with bridge specific information */ | |
1312 | static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus, | |
1313 | void *fdt, int offset) | |
1314 | { | |
7e10b57d | 1315 | Object *owner; |
466e8831 DG |
1316 | PciWalkFdt cbinfo = { |
1317 | .fdt = fdt, | |
1318 | .offset = offset, | |
1319 | .sphb = sphb, | |
1320 | .err = 0, | |
1321 | }; | |
14e71490 | 1322 | int ret; |
466e8831 DG |
1323 | |
1324 | _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", | |
1325 | RESOURCE_CELLS_ADDRESS)); | |
1326 | _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", | |
1327 | RESOURCE_CELLS_SIZE)); | |
1328 | ||
740a1931 PMD |
1329 | assert(bus); |
1330 | pci_for_each_device_reverse(bus, pci_bus_num(bus), | |
1331 | spapr_dt_pci_device_cb, &cbinfo); | |
1332 | if (cbinfo.err) { | |
1333 | return cbinfo.err; | |
466e8831 DG |
1334 | } |
1335 | ||
7e10b57d GK |
1336 | if (pci_bus_is_root(bus)) { |
1337 | owner = OBJECT(sphb); | |
1338 | } else { | |
1339 | owner = OBJECT(pci_bridge_get_device(bus)); | |
1340 | } | |
1341 | ||
1342 | ret = spapr_dt_drc(fdt, offset, owner, | |
14e71490 DG |
1343 | SPAPR_DR_CONNECTOR_TYPE_PCI); |
1344 | if (ret) { | |
1345 | return ret; | |
1346 | } | |
1347 | ||
466e8831 DG |
1348 | return offset; |
1349 | } | |
e634b89c | 1350 | |
9d2134d8 DG |
1351 | /* create OF node for pci device and required OF DT properties */ |
1352 | static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, | |
1353 | void *fdt, int parent_offset) | |
7454c7af | 1354 | { |
9d2134d8 DG |
1355 | int offset; |
1356 | const gchar *basename; | |
1357 | gchar *nodename; | |
1358 | int slot = PCI_SLOT(dev->devfn); | |
1359 | int func = PCI_FUNC(dev->devfn); | |
466e8831 | 1360 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
7454c7af | 1361 | ResourceProps rp; |
a1ec25b2 | 1362 | SpaprDrc *drc = drc_from_dev(sphb, dev); |
9d2134d8 DG |
1363 | uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2); |
1364 | uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2); | |
1365 | uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1); | |
2530a1a5 | 1366 | uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); |
9d2134d8 DG |
1367 | uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1); |
1368 | uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2); | |
1369 | uint32_t subsystem_vendor_id = | |
1370 | pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2); | |
1371 | uint32_t cache_line_size = | |
1372 | pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1); | |
1373 | uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2); | |
1374 | gchar *loc_code; | |
7454c7af | 1375 | |
9d2134d8 DG |
1376 | basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff, |
1377 | ccode & 0xff); | |
7454c7af | 1378 | |
9d2134d8 DG |
1379 | if (func != 0) { |
1380 | nodename = g_strdup_printf("%s@%x,%x", basename, slot, func); | |
1381 | } else { | |
1382 | nodename = g_strdup_printf("%s@%x", basename, slot); | |
7454c7af MR |
1383 | } |
1384 | ||
9d2134d8 DG |
1385 | _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename)); |
1386 | ||
1387 | g_free(nodename); | |
1388 | ||
7454c7af | 1389 | /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ |
9d2134d8 DG |
1390 | _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id)); |
1391 | _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id)); | |
1392 | _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id)); | |
7454c7af | 1393 | |
2530a1a5 | 1394 | _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode)); |
9d2134d8 DG |
1395 | if (irq_pin) { |
1396 | _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin)); | |
7454c7af MR |
1397 | } |
1398 | ||
9d2134d8 DG |
1399 | if (subsystem_id) { |
1400 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id)); | |
7454c7af MR |
1401 | } |
1402 | ||
9d2134d8 | 1403 | if (subsystem_vendor_id) { |
7454c7af | 1404 | _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", |
9d2134d8 | 1405 | subsystem_vendor_id)); |
7454c7af MR |
1406 | } |
1407 | ||
9d2134d8 DG |
1408 | _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size)); |
1409 | ||
7454c7af MR |
1410 | |
1411 | /* the following fdt cells are masked off the pci status register */ | |
7454c7af MR |
1412 | _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", |
1413 | PCI_STATUS_DEVSEL_MASK & pci_status)); | |
1414 | ||
1415 | if (pci_status & PCI_STATUS_FAST_BACK) { | |
1416 | _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); | |
1417 | } | |
1418 | if (pci_status & PCI_STATUS_66MHZ) { | |
1419 | _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); | |
1420 | } | |
1421 | if (pci_status & PCI_STATUS_UDF) { | |
1422 | _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); | |
1423 | } | |
1424 | ||
9d2134d8 DG |
1425 | loc_code = spapr_phb_get_loc_code(sphb, dev); |
1426 | _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code)); | |
1427 | g_free(loc_code); | |
16b0ea1d | 1428 | |
a1ec25b2 DG |
1429 | if (drc) { |
1430 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", | |
1431 | spapr_drc_index(drc))); | |
e634b89c | 1432 | } |
7454c7af | 1433 | |
9cbe305b | 1434 | if (msi_present(dev)) { |
9d2134d8 | 1435 | uint32_t max_msi = msi_nr_vectors_allocated(dev); |
9cbe305b GK |
1436 | if (max_msi) { |
1437 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); | |
1438 | } | |
a8ad731a | 1439 | } |
9cbe305b | 1440 | if (msix_present(dev)) { |
9d2134d8 | 1441 | uint32_t max_msix = dev->msix_entries_nr; |
9cbe305b GK |
1442 | if (max_msix) { |
1443 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); | |
1444 | } | |
a8ad731a | 1445 | } |
7454c7af MR |
1446 | |
1447 | populate_resource_props(dev, &rp); | |
1448 | _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); | |
7454c7af | 1449 | |
82516263 | 1450 | if (sphb->pcie_ecs && pci_is_express(dev)) { |
bb998645 DG |
1451 | _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1)); |
1452 | } | |
ec132efa AK |
1453 | |
1454 | spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb); | |
7454c7af | 1455 | |
466e8831 DG |
1456 | if (!pc->is_bridge) { |
1457 | /* Properties only for non-bridges */ | |
1458 | uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1); | |
1459 | uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1); | |
1460 | _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant)); | |
1461 | _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency)); | |
1462 | return offset; | |
1463 | } else { | |
1464 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); | |
e634b89c | 1465 | |
466e8831 DG |
1466 | return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset); |
1467 | } | |
7454c7af MR |
1468 | } |
1469 | ||
31834723 DHB |
1470 | /* Callback to be called during DRC release. */ |
1471 | void spapr_phb_remove_pci_device_cb(DeviceState *dev) | |
7454c7af | 1472 | { |
27c1da51 DH |
1473 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); |
1474 | ||
1475 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); | |
07578b0a | 1476 | object_unparent(OBJECT(dev)); |
7454c7af MR |
1477 | } |
1478 | ||
ce2918cb | 1479 | int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
46fd0299 GK |
1480 | void *fdt, int *fdt_start_offset, Error **errp) |
1481 | { | |
1482 | HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev); | |
ce2918cb | 1483 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler); |
46fd0299 GK |
1484 | PCIDevice *pdev = PCI_DEVICE(drc->dev); |
1485 | ||
9d2134d8 | 1486 | *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0); |
46fd0299 GK |
1487 | return 0; |
1488 | } | |
1489 | ||
14e71490 DG |
1490 | static void spapr_pci_bridge_plug(SpaprPhbState *phb, |
1491 | PCIBridge *bridge, | |
1492 | Error **errp) | |
1493 | { | |
1494 | Error *local_err = NULL; | |
1495 | PCIBus *bus = pci_bridge_get_sec_bus(bridge); | |
1496 | ||
1497 | add_drcs(phb, bus, &local_err); | |
1498 | if (local_err) { | |
1499 | error_propagate(errp, local_err); | |
1500 | return; | |
1501 | } | |
1502 | } | |
1503 | ||
3340e5c4 DG |
1504 | static void spapr_pci_plug(HotplugHandler *plug_handler, |
1505 | DeviceState *plugged_dev, Error **errp) | |
7454c7af | 1506 | { |
ce2918cb | 1507 | SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); |
7454c7af | 1508 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); |
14e71490 | 1509 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); |
a1ec25b2 | 1510 | SpaprDrc *drc = drc_from_dev(phb, pdev); |
7454c7af | 1511 | Error *local_err = NULL; |
788d2599 MR |
1512 | PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); |
1513 | uint32_t slotnr = PCI_SLOT(pdev->devfn); | |
7454c7af MR |
1514 | |
1515 | /* if DR is disabled we don't need to do anything in the case of | |
1516 | * hotplug or coldplug callbacks | |
1517 | */ | |
1518 | if (!phb->dr_enabled) { | |
1519 | /* if this is a hotplug operation initiated by the user | |
1520 | * we need to let them know it's not enabled | |
1521 | */ | |
1522 | if (plugged_dev->hotplugged) { | |
6304fd27 | 1523 | error_setg(&local_err, QERR_BUS_NO_HOTPLUG, |
c6bd8c70 | 1524 | object_get_typename(OBJECT(phb))); |
7454c7af | 1525 | } |
6304fd27 | 1526 | goto out; |
7454c7af MR |
1527 | } |
1528 | ||
1529 | g_assert(drc); | |
1530 | ||
14e71490 DG |
1531 | if (pc->is_bridge) { |
1532 | spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev), &local_err); | |
1533 | if (local_err) { | |
1534 | error_propagate(errp, local_err); | |
1535 | return; | |
1536 | } | |
1537 | } | |
1538 | ||
788d2599 MR |
1539 | /* Following the QEMU convention used for PCIe multifunction |
1540 | * hotplug, we do not allow functions to be hotplugged to a | |
1541 | * slot that already has function 0 present | |
1542 | */ | |
1543 | if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] && | |
1544 | PCI_FUNC(pdev->devfn) != 0) { | |
6304fd27 | 1545 | error_setg(&local_err, "PCI: slot %d function 0 already ocuppied by %s," |
788d2599 MR |
1546 | " additional functions can no longer be exposed to guest.", |
1547 | slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name); | |
6304fd27 DG |
1548 | goto out; |
1549 | } | |
1550 | ||
09d876ce | 1551 | spapr_drc_attach(drc, DEVICE(pdev), &local_err); |
7454c7af | 1552 | if (local_err) { |
6304fd27 | 1553 | goto out; |
7454c7af | 1554 | } |
788d2599 MR |
1555 | |
1556 | /* If this is function 0, signal hotplug for all the device functions. | |
1557 | * Otherwise defer sending the hotplug event. | |
1558 | */ | |
94fd9cba LV |
1559 | if (!spapr_drc_hotplugged(plugged_dev)) { |
1560 | spapr_drc_reset(drc); | |
1561 | } else if (PCI_FUNC(pdev->devfn) == 0) { | |
788d2599 | 1562 | int i; |
05929a6c DG |
1563 | uint8_t chassis = chassis_from_bus(pci_get_bus(pdev), &local_err); |
1564 | ||
1565 | if (local_err) { | |
1566 | error_propagate(errp, local_err); | |
1567 | return; | |
1568 | } | |
788d2599 MR |
1569 | |
1570 | for (i = 0; i < 8; i++) { | |
ce2918cb DG |
1571 | SpaprDrc *func_drc; |
1572 | SpaprDrcClass *func_drck; | |
1573 | SpaprDREntitySense state; | |
788d2599 | 1574 | |
05929a6c | 1575 | func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); |
788d2599 | 1576 | func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); |
f224d35b | 1577 | state = func_drck->dr_entity_sense(func_drc); |
788d2599 MR |
1578 | |
1579 | if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { | |
1580 | spapr_hotplug_req_add_by_index(func_drc); | |
1581 | } | |
1582 | } | |
c5bc152b | 1583 | } |
6304fd27 DG |
1584 | |
1585 | out: | |
e366d181 | 1586 | error_propagate(errp, local_err); |
7454c7af MR |
1587 | } |
1588 | ||
14e71490 DG |
1589 | static void spapr_pci_bridge_unplug(SpaprPhbState *phb, |
1590 | PCIBridge *bridge, | |
1591 | Error **errp) | |
1592 | { | |
1593 | Error *local_err = NULL; | |
1594 | PCIBus *bus = pci_bridge_get_sec_bus(bridge); | |
1595 | ||
1596 | remove_drcs(phb, bus, &local_err); | |
1597 | if (local_err) { | |
1598 | error_propagate(errp, local_err); | |
1599 | return; | |
1600 | } | |
1601 | } | |
1602 | ||
27c1da51 DH |
1603 | static void spapr_pci_unplug(HotplugHandler *plug_handler, |
1604 | DeviceState *plugged_dev, Error **errp) | |
1605 | { | |
14e71490 DG |
1606 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); |
1607 | SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); | |
1608 | ||
27c1da51 DH |
1609 | /* some version guests do not wait for completion of a device |
1610 | * cleanup (generally done asynchronously by the kernel) before | |
1611 | * signaling to QEMU that the device is safe, but instead sleep | |
1612 | * for some 'safe' period of time. unfortunately on a busy host | |
1613 | * this sleep isn't guaranteed to be long enough, resulting in | |
1614 | * bad things like IRQ lines being left asserted during final | |
1615 | * device removal. to deal with this we call reset just prior | |
1616 | * to finalizing the device, which will put the device back into | |
1617 | * an 'idle' state, as the device cleanup code expects. | |
1618 | */ | |
1619 | pci_device_reset(PCI_DEVICE(plugged_dev)); | |
14e71490 DG |
1620 | |
1621 | if (pc->is_bridge) { | |
1622 | Error *local_err = NULL; | |
1623 | spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev), &local_err); | |
1624 | if (local_err) { | |
1625 | error_propagate(errp, local_err); | |
1626 | } | |
1627 | return; | |
1628 | } | |
1629 | ||
07578b0a | 1630 | object_property_set_bool(OBJECT(plugged_dev), false, "realized", NULL); |
27c1da51 DH |
1631 | } |
1632 | ||
3340e5c4 DG |
1633 | static void spapr_pci_unplug_request(HotplugHandler *plug_handler, |
1634 | DeviceState *plugged_dev, Error **errp) | |
7454c7af | 1635 | { |
ce2918cb | 1636 | SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); |
7454c7af | 1637 | PCIDevice *pdev = PCI_DEVICE(plugged_dev); |
a1ec25b2 | 1638 | SpaprDrc *drc = drc_from_dev(phb, pdev); |
7454c7af MR |
1639 | |
1640 | if (!phb->dr_enabled) { | |
c6bd8c70 MA |
1641 | error_setg(errp, QERR_BUS_NO_HOTPLUG, |
1642 | object_get_typename(OBJECT(phb))); | |
7454c7af MR |
1643 | return; |
1644 | } | |
1645 | ||
1646 | g_assert(drc); | |
3340e5c4 | 1647 | g_assert(drc->dev == plugged_dev); |
7454c7af | 1648 | |
f1c52354 | 1649 | if (!spapr_drc_unplug_requested(drc)) { |
14e71490 | 1650 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); |
788d2599 | 1651 | uint32_t slotnr = PCI_SLOT(pdev->devfn); |
ce2918cb DG |
1652 | SpaprDrc *func_drc; |
1653 | SpaprDrcClass *func_drck; | |
1654 | SpaprDREntitySense state; | |
788d2599 | 1655 | int i; |
05929a6c DG |
1656 | Error *local_err = NULL; |
1657 | uint8_t chassis = chassis_from_bus(pci_get_bus(pdev), &local_err); | |
1658 | ||
1659 | if (local_err) { | |
1660 | error_propagate(errp, local_err); | |
1661 | return; | |
1662 | } | |
788d2599 | 1663 | |
14e71490 DG |
1664 | if (pc->is_bridge) { |
1665 | error_setg(errp, "PCI: Hot unplug of PCI bridges not supported"); | |
1666 | } | |
788d2599 MR |
1667 | |
1668 | /* ensure any other present functions are pending unplug */ | |
1669 | if (PCI_FUNC(pdev->devfn) == 0) { | |
1670 | for (i = 1; i < 8; i++) { | |
05929a6c | 1671 | func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); |
788d2599 | 1672 | func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); |
f224d35b | 1673 | state = func_drck->dr_entity_sense(func_drc); |
788d2599 | 1674 | if (state == SPAPR_DR_ENTITY_SENSE_PRESENT |
f1c52354 | 1675 | && !spapr_drc_unplug_requested(func_drc)) { |
02a1536e DHB |
1676 | /* |
1677 | * Attempting to remove function 0 of a multifunction | |
1678 | * device will will cascade into removing all child | |
1679 | * functions, even if their unplug weren't requested | |
1680 | * beforehand. | |
1681 | */ | |
1682 | spapr_drc_detach(func_drc); | |
788d2599 MR |
1683 | } |
1684 | } | |
1685 | } | |
1686 | ||
a8dc47fd | 1687 | spapr_drc_detach(drc); |
788d2599 MR |
1688 | |
1689 | /* if this isn't func 0, defer unplug event. otherwise signal removal | |
1690 | * for all present functions | |
1691 | */ | |
1692 | if (PCI_FUNC(pdev->devfn) == 0) { | |
1693 | for (i = 7; i >= 0; i--) { | |
05929a6c | 1694 | func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); |
788d2599 | 1695 | func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); |
f224d35b | 1696 | state = func_drck->dr_entity_sense(func_drc); |
788d2599 MR |
1697 | if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { |
1698 | spapr_hotplug_req_remove_by_index(func_drc); | |
1699 | } | |
1700 | } | |
1701 | } | |
7454c7af MR |
1702 | } |
1703 | } | |
1704 | ||
ef28b98d GK |
1705 | static void spapr_phb_finalizefn(Object *obj) |
1706 | { | |
ce2918cb | 1707 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj); |
ef28b98d GK |
1708 | |
1709 | g_free(sphb->dtbusname); | |
1710 | sphb->dtbusname = NULL; | |
1711 | } | |
1712 | ||
1713 | static void spapr_phb_unrealize(DeviceState *dev, Error **errp) | |
1714 | { | |
ce2918cb | 1715 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
ef28b98d GK |
1716 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
1717 | PCIHostState *phb = PCI_HOST_BRIDGE(s); | |
ce2918cb DG |
1718 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb); |
1719 | SpaprTceTable *tcet; | |
ef28b98d GK |
1720 | int i; |
1721 | const unsigned windows_supported = spapr_phb_windows_supported(sphb); | |
14e71490 | 1722 | Error *local_err = NULL; |
ef28b98d | 1723 | |
ec132efa AK |
1724 | spapr_phb_nvgpu_free(sphb); |
1725 | ||
ef28b98d GK |
1726 | if (sphb->msi) { |
1727 | g_hash_table_unref(sphb->msi); | |
1728 | sphb->msi = NULL; | |
1729 | } | |
1730 | ||
1731 | /* | |
1732 | * Remove IO/MMIO subregions and aliases, rest should get cleaned | |
1733 | * via PHB's unrealize->object_finalize | |
1734 | */ | |
1735 | for (i = windows_supported - 1; i >= 0; i--) { | |
1736 | tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); | |
1737 | if (tcet) { | |
1738 | memory_region_del_subregion(&sphb->iommu_root, | |
1739 | spapr_tce_get_iommu(tcet)); | |
1740 | } | |
1741 | } | |
1742 | ||
14e71490 DG |
1743 | remove_drcs(sphb, phb->bus, &local_err); |
1744 | if (local_err) { | |
1745 | error_propagate(errp, local_err); | |
1746 | return; | |
ef28b98d GK |
1747 | } |
1748 | ||
1749 | for (i = PCI_NUM_PINS - 1; i >= 0; i--) { | |
1750 | if (sphb->lsi_table[i].irq) { | |
1751 | spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1); | |
1752 | sphb->lsi_table[i].irq = 0; | |
1753 | } | |
1754 | } | |
1755 | ||
1756 | QLIST_REMOVE(sphb, list); | |
1757 | ||
1758 | memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow); | |
1759 | ||
a2166410 GK |
1760 | /* |
1761 | * An attached PCI device may have memory listeners, eg. VFIO PCI. We have | |
1762 | * unmapped all sections. Remove the listeners now, before destroying the | |
1763 | * address space. | |
1764 | */ | |
1765 | address_space_remove_listeners(&sphb->iommu_as); | |
ef28b98d GK |
1766 | address_space_destroy(&sphb->iommu_as); |
1767 | ||
1768 | qbus_set_hotplug_handler(BUS(phb->bus), NULL, &error_abort); | |
1769 | pci_unregister_root_bus(phb->bus); | |
1770 | ||
1771 | memory_region_del_subregion(get_system_memory(), &sphb->iowindow); | |
1772 | if (sphb->mem64_win_pciaddr != (hwaddr)-1) { | |
1773 | memory_region_del_subregion(get_system_memory(), &sphb->mem64window); | |
1774 | } | |
1775 | memory_region_del_subregion(get_system_memory(), &sphb->mem32window); | |
1776 | } | |
1777 | ||
078eb6b0 GK |
1778 | static void spapr_phb_destroy_msi(gpointer opaque) |
1779 | { | |
1780 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); | |
1781 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
572ebd08 | 1782 | SpaprPciMsi *msi = opaque; |
078eb6b0 GK |
1783 | |
1784 | if (!smc->legacy_irq_allocation) { | |
1785 | spapr_irq_msi_free(spapr, msi->first_irq, msi->num); | |
1786 | } | |
1787 | spapr_irq_free(spapr, msi->first_irq, msi->num); | |
1788 | g_free(msi); | |
1789 | } | |
1790 | ||
c6ba42f6 | 1791 | static void spapr_phb_realize(DeviceState *dev, Error **errp) |
3384f95c | 1792 | { |
f7d6bfcd GK |
1793 | /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user |
1794 | * tries to add a sPAPR PHB to a non-pseries machine. | |
1795 | */ | |
ce2918cb DG |
1796 | SpaprMachineState *spapr = |
1797 | (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), | |
f7d6bfcd | 1798 | TYPE_SPAPR_MACHINE); |
ce2918cb | 1799 | SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL; |
c6ba42f6 | 1800 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
ce2918cb | 1801 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s); |
8558d942 | 1802 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
7e721e7b | 1803 | MachineState *ms = MACHINE(spapr); |
298a9710 DG |
1804 | char *namebuf; |
1805 | int i; | |
3384f95c | 1806 | PCIBus *bus; |
8c46f7ec | 1807 | uint64_t msi_window_size = 4096; |
ce2918cb | 1808 | SpaprTceTable *tcet; |
ef28b98d | 1809 | const unsigned windows_supported = spapr_phb_windows_supported(sphb); |
14e71490 | 1810 | Error *local_err = NULL; |
3384f95c | 1811 | |
f7d6bfcd GK |
1812 | if (!spapr) { |
1813 | error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine"); | |
1814 | return; | |
1815 | } | |
1816 | ||
bb2bdd81 | 1817 | assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */ |
caae58cb | 1818 | |
daa23699 | 1819 | if (sphb->mem64_win_size != 0) { |
daa23699 DG |
1820 | if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { |
1821 | error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx | |
1822 | " (max 2 GiB)", sphb->mem_win_size); | |
1823 | return; | |
1824 | } | |
1825 | ||
30b3bc5a GK |
1826 | /* 64-bit window defaults to identity mapping */ |
1827 | sphb->mem64_win_pciaddr = sphb->mem64_win_addr; | |
daa23699 DG |
1828 | } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { |
1829 | /* | |
1830 | * For compatibility with old configuration, if no 64-bit MMIO | |
1831 | * window is specified, but the ordinary (32-bit) memory | |
1832 | * window is specified as > 2GiB, we treat it as a 2GiB 32-bit | |
1833 | * window, with a 64-bit MMIO window following on immediately | |
1834 | * afterwards | |
1835 | */ | |
1836 | sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; | |
1837 | sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; | |
1838 | sphb->mem64_win_pciaddr = | |
1839 | SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; | |
1840 | sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; | |
1841 | } | |
1842 | ||
46c5874e | 1843 | if (spapr_pci_find_phb(spapr, sphb->buid)) { |
70282930 GK |
1844 | SpaprPhbState *s; |
1845 | ||
1846 | error_setg(errp, "PCI host bridges must have unique indexes"); | |
1847 | error_append_hint(errp, "The following indexes are already in use:"); | |
1848 | QLIST_FOREACH(s, &spapr->phbs, list) { | |
1849 | error_append_hint(errp, " %d", s->index); | |
1850 | } | |
1851 | error_append_hint(errp, "\nTry another value for the index property\n"); | |
c6ba42f6 | 1852 | return; |
caae58cb DG |
1853 | } |
1854 | ||
4bcfa56c | 1855 | if (sphb->numa_node != -1 && |
7e721e7b TX |
1856 | (sphb->numa_node >= MAX_NODES || |
1857 | !ms->numa_state->nodes[sphb->numa_node].present)) { | |
4bcfa56c MR |
1858 | error_setg(errp, "Invalid NUMA node ID for PCI host bridge"); |
1859 | return; | |
1860 | } | |
1861 | ||
8c9f64df | 1862 | sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); |
caae58cb | 1863 | |
298a9710 | 1864 | /* Initialize memory regions */ |
1d36da76 | 1865 | namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname); |
92b8e39c | 1866 | memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); |
1d36da76 | 1867 | g_free(namebuf); |
3384f95c | 1868 | |
1d36da76 | 1869 | namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname); |
daa23699 | 1870 | memory_region_init_alias(&sphb->mem32window, OBJECT(sphb), |
40c5dce9 | 1871 | namebuf, &sphb->memspace, |
8c9f64df | 1872 | SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); |
1d36da76 | 1873 | g_free(namebuf); |
8c9f64df | 1874 | memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, |
daa23699 DG |
1875 | &sphb->mem32window); |
1876 | ||
30b3bc5a | 1877 | if (sphb->mem64_win_size != 0) { |
96dbc9af GK |
1878 | namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname); |
1879 | memory_region_init_alias(&sphb->mem64window, OBJECT(sphb), | |
1880 | namebuf, &sphb->memspace, | |
1881 | sphb->mem64_win_pciaddr, sphb->mem64_win_size); | |
1882 | g_free(namebuf); | |
1883 | ||
30b3bc5a GK |
1884 | memory_region_add_subregion(get_system_memory(), |
1885 | sphb->mem64_win_addr, | |
1886 | &sphb->mem64window); | |
96dbc9af | 1887 | } |
3384f95c | 1888 | |
fabe9ee1 | 1889 | /* Initialize IO regions */ |
1d36da76 | 1890 | namebuf = g_strdup_printf("%s.io", sphb->dtbusname); |
40c5dce9 PB |
1891 | memory_region_init(&sphb->iospace, OBJECT(sphb), |
1892 | namebuf, SPAPR_PCI_IO_WIN_SIZE); | |
1d36da76 | 1893 | g_free(namebuf); |
3384f95c | 1894 | |
1d36da76 | 1895 | namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname); |
66aab867 | 1896 | memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, |
fabe9ee1 | 1897 | &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); |
1d36da76 | 1898 | g_free(namebuf); |
8c9f64df | 1899 | memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, |
a3cfa18e | 1900 | &sphb->iowindow); |
1b8601b0 | 1901 | |
4560116e | 1902 | bus = pci_register_root_bus(dev, NULL, |
e8ec4adf | 1903 | pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb, |
1115ff6d | 1904 | &sphb->memspace, &sphb->iospace, |
5cf0d326 | 1905 | PCI_DEVFN(0, 0), PCI_NUM_PINS, |
2f57db8a DG |
1906 | TYPE_PCI_BUS); |
1907 | ||
1908 | /* | |
1909 | * Despite resembling a vanilla PCI bus in most ways, the PAPR | |
1910 | * para-virtualized PCI bus *does* permit PCI-E extended config | |
1911 | * space access | |
1912 | */ | |
1913 | if (sphb->pcie_ecs) { | |
1914 | bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; | |
1915 | } | |
8c9f64df | 1916 | phb->bus = bus; |
94d1cc5f | 1917 | qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb), NULL); |
298a9710 | 1918 | |
cca7fad5 AK |
1919 | /* |
1920 | * Initialize PHB address space. | |
1921 | * By default there will be at least one subregion for default | |
1922 | * 32bit DMA window. | |
1923 | * Later the guest might want to create another DMA window | |
1924 | * which will become another memory subregion. | |
1925 | */ | |
1d36da76 | 1926 | namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname); |
cca7fad5 AK |
1927 | memory_region_init(&sphb->iommu_root, OBJECT(sphb), |
1928 | namebuf, UINT64_MAX); | |
1d36da76 | 1929 | g_free(namebuf); |
cca7fad5 AK |
1930 | address_space_init(&sphb->iommu_as, &sphb->iommu_root, |
1931 | sphb->dtbusname); | |
1932 | ||
8c46f7ec GK |
1933 | /* |
1934 | * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, | |
1935 | * we need to allocate some memory to catch those writes coming | |
1936 | * from msi_notify()/msix_notify(). | |
1937 | * As MSIMessage:addr is going to be the same and MSIMessage:data | |
1938 | * is going to be a VIRQ number, 4 bytes of the MSI MR will only | |
1939 | * be used. | |
1940 | * | |
1941 | * For KVM we want to ensure that this memory is a full page so that | |
1942 | * our memory slot is of page size granularity. | |
1943 | */ | |
8c46f7ec | 1944 | if (kvm_enabled()) { |
038adc2f | 1945 | msi_window_size = qemu_real_host_page_size; |
8c46f7ec | 1946 | } |
8c46f7ec | 1947 | |
dba95ebb | 1948 | memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr, |
8c46f7ec GK |
1949 | "msi", msi_window_size); |
1950 | memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, | |
1951 | &sphb->msiwindow); | |
1952 | ||
e00387d5 | 1953 | pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); |
edded454 | 1954 | |
5cc7a967 AK |
1955 | pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); |
1956 | ||
8c9f64df | 1957 | QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); |
298a9710 DG |
1958 | |
1959 | /* Initialize the LSI table */ | |
7fb0bd34 | 1960 | for (i = 0; i < PCI_NUM_PINS; i++) { |
82cffa2e | 1961 | uint32_t irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i; |
298a9710 | 1962 | |
2c88b098 | 1963 | if (smc->legacy_irq_allocation) { |
82cffa2e CLG |
1964 | irq = spapr_irq_findone(spapr, &local_err); |
1965 | if (local_err) { | |
4b576648 MA |
1966 | error_propagate_prepend(errp, local_err, |
1967 | "can't allocate LSIs: "); | |
ef28b98d GK |
1968 | /* |
1969 | * Older machines will never support PHB hotplug, ie, this is an | |
1970 | * init only path and QEMU will terminate. No need to rollback. | |
1971 | */ | |
82cffa2e CLG |
1972 | return; |
1973 | } | |
4fe75a8c CLG |
1974 | } |
1975 | ||
1976 | spapr_irq_claim(spapr, irq, true, &local_err); | |
a005b3ef | 1977 | if (local_err) { |
4b576648 | 1978 | error_propagate_prepend(errp, local_err, "can't allocate LSIs: "); |
ef28b98d | 1979 | goto unrealize; |
298a9710 DG |
1980 | } |
1981 | ||
8c9f64df | 1982 | sphb->lsi_table[i].irq = irq; |
298a9710 | 1983 | } |
da6ccee4 | 1984 | |
62083979 | 1985 | /* allocate connectors for child PCI devices */ |
14e71490 DG |
1986 | add_drcs(sphb, phb->bus, &local_err); |
1987 | if (local_err) { | |
1988 | error_propagate(errp, local_err); | |
1989 | goto unrealize; | |
62083979 MR |
1990 | } |
1991 | ||
ae4de14c AK |
1992 | /* DMA setup */ |
1993 | for (i = 0; i < windows_supported; ++i) { | |
1994 | tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]); | |
1995 | if (!tcet) { | |
1996 | error_setg(errp, "Creating window#%d failed for %s", | |
1997 | i, sphb->dtbusname); | |
ef28b98d | 1998 | goto unrealize; |
ae4de14c | 1999 | } |
5c3d70e9 GK |
2000 | memory_region_add_subregion(&sphb->iommu_root, 0, |
2001 | spapr_tce_get_iommu(tcet)); | |
da6ccee4 | 2002 | } |
cca7fad5 | 2003 | |
078eb6b0 GK |
2004 | sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, |
2005 | spapr_phb_destroy_msi); | |
ef28b98d GK |
2006 | return; |
2007 | ||
2008 | unrealize: | |
2009 | spapr_phb_unrealize(dev, NULL); | |
298a9710 DG |
2010 | } |
2011 | ||
e28c16f6 | 2012 | static int spapr_phb_children_reset(Object *child, void *opaque) |
eddeed26 | 2013 | { |
e28c16f6 AK |
2014 | DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); |
2015 | ||
2016 | if (dev) { | |
2017 | device_reset(dev); | |
2018 | } | |
eddeed26 | 2019 | |
e28c16f6 AK |
2020 | return 0; |
2021 | } | |
2022 | ||
ce2918cb | 2023 | void spapr_phb_dma_reset(SpaprPhbState *sphb) |
e28c16f6 | 2024 | { |
ae4de14c | 2025 | int i; |
ce2918cb | 2026 | SpaprTceTable *tcet; |
ae4de14c AK |
2027 | |
2028 | for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) { | |
2029 | tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); | |
acf1b6dd | 2030 | |
ae4de14c AK |
2031 | if (tcet && tcet->nb_table) { |
2032 | spapr_tce_table_disable(tcet); | |
2033 | } | |
acf1b6dd AK |
2034 | } |
2035 | ||
2036 | /* Register default 32bit DMA window */ | |
ae4de14c | 2037 | tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]); |
acf1b6dd AK |
2038 | spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, |
2039 | sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT); | |
b3162f22 AK |
2040 | } |
2041 | ||
2042 | static void spapr_phb_reset(DeviceState *qdev) | |
2043 | { | |
ce2918cb | 2044 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev); |
8ca63ba8 | 2045 | Error *err = NULL; |
b3162f22 AK |
2046 | |
2047 | spapr_phb_dma_reset(sphb); | |
ec132efa | 2048 | spapr_phb_nvgpu_free(sphb); |
8ca63ba8 MA |
2049 | spapr_phb_nvgpu_setup(sphb, &err); |
2050 | if (err) { | |
2051 | error_report_err(err); | |
ec132efa | 2052 | } |
acf1b6dd | 2053 | |
eddeed26 | 2054 | /* Reset the IOMMU state */ |
e28c16f6 | 2055 | object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); |
fbb4e983 DG |
2056 | |
2057 | if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) { | |
2058 | spapr_phb_vfio_reset(qdev); | |
2059 | } | |
ea52074d GK |
2060 | |
2061 | g_hash_table_remove_all(sphb->msi); | |
eddeed26 DG |
2062 | } |
2063 | ||
298a9710 | 2064 | static Property spapr_phb_properties[] = { |
ce2918cb DG |
2065 | DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1), |
2066 | DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size, | |
357d1e3b | 2067 | SPAPR_PCI_MEM32_WIN_SIZE), |
ce2918cb | 2068 | DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size, |
357d1e3b | 2069 | SPAPR_PCI_MEM64_WIN_SIZE), |
ce2918cb | 2070 | DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size, |
c7bcc85d | 2071 | SPAPR_PCI_IO_WIN_SIZE), |
ce2918cb | 2072 | DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled, |
7619c7b0 | 2073 | true), |
f93caaac | 2074 | /* Default DMA window is 0..1GB */ |
ce2918cb DG |
2075 | DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0), |
2076 | DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000), | |
2077 | DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr, | |
ae4de14c | 2078 | 0x800000000000000ULL), |
ce2918cb DG |
2079 | DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true), |
2080 | DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask, | |
d15d4ad6 DG |
2081 | (1ULL << 12) | (1ULL << 16) |
2082 | | (1ULL << 21) | (1ULL << 24)), | |
ce2918cb DG |
2083 | DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1), |
2084 | DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState, | |
5c4537bd | 2085 | pre_2_8_migration, false), |
ce2918cb | 2086 | DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState, |
82516263 | 2087 | pcie_ecs, true), |
ec132efa AK |
2088 | DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0), |
2089 | DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0), | |
298a9710 DG |
2090 | DEFINE_PROP_END_OF_LIST(), |
2091 | }; | |
2092 | ||
1112cf94 DG |
2093 | static const VMStateDescription vmstate_spapr_pci_lsi = { |
2094 | .name = "spapr_pci/lsi", | |
2095 | .version_id = 1, | |
2096 | .minimum_version_id = 1, | |
3aff6c2f | 2097 | .fields = (VMStateField[]) { |
572ebd08 | 2098 | VMSTATE_UINT32_EQUAL(irq, SpaprPciLsi, NULL), |
1112cf94 DG |
2099 | |
2100 | VMSTATE_END_OF_LIST() | |
2101 | }, | |
2102 | }; | |
2103 | ||
2104 | static const VMStateDescription vmstate_spapr_pci_msi = { | |
9a321e92 | 2105 | .name = "spapr_pci/msi", |
1112cf94 DG |
2106 | .version_id = 1, |
2107 | .minimum_version_id = 1, | |
9a321e92 | 2108 | .fields = (VMStateField []) { |
572ebd08 GK |
2109 | VMSTATE_UINT32(key, SpaprPciMsiMig), |
2110 | VMSTATE_UINT32(value.first_irq, SpaprPciMsiMig), | |
2111 | VMSTATE_UINT32(value.num, SpaprPciMsiMig), | |
1112cf94 DG |
2112 | VMSTATE_END_OF_LIST() |
2113 | }, | |
2114 | }; | |
2115 | ||
44b1ff31 | 2116 | static int spapr_pci_pre_save(void *opaque) |
9a321e92 | 2117 | { |
ce2918cb | 2118 | SpaprPhbState *sphb = opaque; |
708414f0 MA |
2119 | GHashTableIter iter; |
2120 | gpointer key, value; | |
2121 | int i; | |
9a321e92 | 2122 | |
5c4537bd DG |
2123 | if (sphb->pre_2_8_migration) { |
2124 | sphb->mig_liobn = sphb->dma_liobn[0]; | |
2125 | sphb->mig_mem_win_addr = sphb->mem_win_addr; | |
2126 | sphb->mig_mem_win_size = sphb->mem_win_size; | |
2127 | sphb->mig_io_win_addr = sphb->io_win_addr; | |
2128 | sphb->mig_io_win_size = sphb->io_win_size; | |
2129 | ||
2130 | if ((sphb->mem64_win_size != 0) | |
2131 | && (sphb->mem64_win_addr | |
2132 | == (sphb->mem_win_addr + sphb->mem_win_size))) { | |
2133 | sphb->mig_mem_win_size += sphb->mem64_win_size; | |
2134 | } | |
2135 | } | |
e806b4db LV |
2136 | |
2137 | g_free(sphb->msi_devs); | |
2138 | sphb->msi_devs = NULL; | |
2139 | sphb->msi_devs_num = g_hash_table_size(sphb->msi); | |
2140 | if (!sphb->msi_devs_num) { | |
44b1ff31 | 2141 | return 0; |
e806b4db | 2142 | } |
572ebd08 | 2143 | sphb->msi_devs = g_new(SpaprPciMsiMig, sphb->msi_devs_num); |
e806b4db LV |
2144 | |
2145 | g_hash_table_iter_init(&iter, sphb->msi); | |
2146 | for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { | |
2147 | sphb->msi_devs[i].key = *(uint32_t *) key; | |
572ebd08 | 2148 | sphb->msi_devs[i].value = *(SpaprPciMsi *) value; |
e806b4db | 2149 | } |
44b1ff31 DDAG |
2150 | |
2151 | return 0; | |
9a321e92 AK |
2152 | } |
2153 | ||
2154 | static int spapr_pci_post_load(void *opaque, int version_id) | |
2155 | { | |
ce2918cb | 2156 | SpaprPhbState *sphb = opaque; |
9a321e92 AK |
2157 | gpointer key, value; |
2158 | int i; | |
2159 | ||
2160 | for (i = 0; i < sphb->msi_devs_num; ++i) { | |
2161 | key = g_memdup(&sphb->msi_devs[i].key, | |
2162 | sizeof(sphb->msi_devs[i].key)); | |
2163 | value = g_memdup(&sphb->msi_devs[i].value, | |
2164 | sizeof(sphb->msi_devs[i].value)); | |
2165 | g_hash_table_insert(sphb->msi, key, value); | |
2166 | } | |
012aef07 MA |
2167 | g_free(sphb->msi_devs); |
2168 | sphb->msi_devs = NULL; | |
9a321e92 AK |
2169 | sphb->msi_devs_num = 0; |
2170 | ||
2171 | return 0; | |
2172 | } | |
2173 | ||
5c4537bd DG |
2174 | static bool pre_2_8_migration(void *opaque, int version_id) |
2175 | { | |
ce2918cb | 2176 | SpaprPhbState *sphb = opaque; |
5c4537bd DG |
2177 | |
2178 | return sphb->pre_2_8_migration; | |
2179 | } | |
2180 | ||
1112cf94 DG |
2181 | static const VMStateDescription vmstate_spapr_pci = { |
2182 | .name = "spapr_pci", | |
5a78b821 | 2183 | .version_id = 2, |
9a321e92 AK |
2184 | .minimum_version_id = 2, |
2185 | .pre_save = spapr_pci_pre_save, | |
2186 | .post_load = spapr_pci_post_load, | |
3aff6c2f | 2187 | .fields = (VMStateField[]) { |
ce2918cb DG |
2188 | VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL), |
2189 | VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration), | |
2190 | VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration), | |
2191 | VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration), | |
2192 | VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration), | |
2193 | VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration), | |
2194 | VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0, | |
572ebd08 | 2195 | vmstate_spapr_pci_lsi, SpaprPciLsi), |
ce2918cb DG |
2196 | VMSTATE_INT32(msi_devs_num, SpaprPhbState), |
2197 | VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0, | |
572ebd08 | 2198 | vmstate_spapr_pci_msi, SpaprPciMsiMig), |
1112cf94 DG |
2199 | VMSTATE_END_OF_LIST() |
2200 | }, | |
2201 | }; | |
2202 | ||
568f0690 DG |
2203 | static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, |
2204 | PCIBus *rootbus) | |
2205 | { | |
ce2918cb | 2206 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); |
568f0690 DG |
2207 | |
2208 | return sphb->dtbusname; | |
2209 | } | |
2210 | ||
298a9710 DG |
2211 | static void spapr_phb_class_init(ObjectClass *klass, void *data) |
2212 | { | |
568f0690 | 2213 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
298a9710 | 2214 | DeviceClass *dc = DEVICE_CLASS(klass); |
7454c7af | 2215 | HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); |
298a9710 | 2216 | |
568f0690 | 2217 | hc->root_bus_path = spapr_phb_root_bus_path; |
c6ba42f6 | 2218 | dc->realize = spapr_phb_realize; |
ef28b98d | 2219 | dc->unrealize = spapr_phb_unrealize; |
298a9710 | 2220 | dc->props = spapr_phb_properties; |
eddeed26 | 2221 | dc->reset = spapr_phb_reset; |
1112cf94 | 2222 | dc->vmsd = &vmstate_spapr_pci; |
e4f4fb1e EH |
2223 | /* Supported by TYPE_SPAPR_MACHINE */ |
2224 | dc->user_creatable = true; | |
09aa9a52 | 2225 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
3340e5c4 | 2226 | hp->plug = spapr_pci_plug; |
27c1da51 | 2227 | hp->unplug = spapr_pci_unplug; |
3340e5c4 | 2228 | hp->unplug_request = spapr_pci_unplug_request; |
298a9710 | 2229 | } |
3384f95c | 2230 | |
4240abff | 2231 | static const TypeInfo spapr_phb_info = { |
8c9f64df | 2232 | .name = TYPE_SPAPR_PCI_HOST_BRIDGE, |
8558d942 | 2233 | .parent = TYPE_PCI_HOST_BRIDGE, |
ce2918cb | 2234 | .instance_size = sizeof(SpaprPhbState), |
ef28b98d | 2235 | .instance_finalize = spapr_phb_finalizefn, |
298a9710 | 2236 | .class_init = spapr_phb_class_init, |
7454c7af MR |
2237 | .interfaces = (InterfaceInfo[]) { |
2238 | { TYPE_HOTPLUG_HANDLER }, | |
2239 | { } | |
2240 | } | |
298a9710 DG |
2241 | }; |
2242 | ||
1d2d9742 ND |
2243 | static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, |
2244 | void *opaque) | |
2245 | { | |
2246 | unsigned int *bus_no = opaque; | |
1d2d9742 ND |
2247 | PCIBus *sec_bus = NULL; |
2248 | ||
2249 | if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != | |
2250 | PCI_HEADER_TYPE_BRIDGE)) { | |
2251 | return; | |
2252 | } | |
2253 | ||
2254 | (*bus_no)++; | |
d8e81d6e | 2255 | pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1); |
1d2d9742 ND |
2256 | pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); |
2257 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); | |
2258 | ||
2259 | sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); | |
2260 | if (!sec_bus) { | |
2261 | return; | |
2262 | } | |
2263 | ||
1d2d9742 ND |
2264 | pci_for_each_device(sec_bus, pci_bus_num(sec_bus), |
2265 | spapr_phb_pci_enumerate_bridge, bus_no); | |
2266 | pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); | |
2267 | } | |
2268 | ||
ce2918cb | 2269 | static void spapr_phb_pci_enumerate(SpaprPhbState *phb) |
1d2d9742 ND |
2270 | { |
2271 | PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; | |
2272 | unsigned int bus_no = 0; | |
2273 | ||
2274 | pci_for_each_device(bus, pci_bus_num(bus), | |
2275 | spapr_phb_pci_enumerate_bridge, | |
2276 | &bus_no); | |
2277 | ||
2278 | } | |
2279 | ||
8cbe71ec DG |
2280 | int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb, |
2281 | uint32_t intc_phandle, void *fdt, int *node_offset) | |
3384f95c | 2282 | { |
62083979 | 2283 | int bus_off, i, j, ret; |
3384f95c DG |
2284 | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
2285 | struct { | |
2286 | uint32_t hi; | |
2287 | uint64_t child; | |
2288 | uint64_t parent; | |
2289 | uint64_t size; | |
c4889f54 | 2290 | } QEMU_PACKED ranges[] = { |
3384f95c DG |
2291 | { |
2292 | cpu_to_be32(b_ss(1)), cpu_to_be64(0), | |
2293 | cpu_to_be64(phb->io_win_addr), | |
2294 | cpu_to_be64(memory_region_size(&phb->iospace)), | |
2295 | }, | |
2296 | { | |
2297 | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), | |
2298 | cpu_to_be64(phb->mem_win_addr), | |
daa23699 | 2299 | cpu_to_be64(phb->mem_win_size), |
b194df47 AK |
2300 | }, |
2301 | { | |
daa23699 DG |
2302 | cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr), |
2303 | cpu_to_be64(phb->mem64_win_addr), | |
2304 | cpu_to_be64(phb->mem64_win_size), | |
3384f95c DG |
2305 | }, |
2306 | }; | |
daa23699 DG |
2307 | const unsigned sizeof_ranges = |
2308 | (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]); | |
3384f95c DG |
2309 | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; |
2310 | uint32_t interrupt_map_mask[] = { | |
7fb0bd34 DG |
2311 | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; |
2312 | uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; | |
ae4de14c AK |
2313 | uint32_t ddw_applicable[] = { |
2314 | cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW), | |
2315 | cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW), | |
2316 | cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW) | |
2317 | }; | |
2318 | uint32_t ddw_extensions[] = { | |
2319 | cpu_to_be32(1), | |
2320 | cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW) | |
2321 | }; | |
4814401f AK |
2322 | uint32_t associativity[] = {cpu_to_be32(0x4), |
2323 | cpu_to_be32(0x0), | |
2324 | cpu_to_be32(0x0), | |
2325 | cpu_to_be32(0x0), | |
2326 | cpu_to_be32(phb->numa_node)}; | |
ce2918cb | 2327 | SpaprTceTable *tcet; |
ce2918cb | 2328 | SpaprDrc *drc; |
8ca63ba8 | 2329 | Error *err = NULL; |
3384f95c DG |
2330 | |
2331 | /* Start populating the FDT */ | |
c413605b | 2332 | _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname)); |
0a0a66cd MR |
2333 | if (node_offset) { |
2334 | *node_offset = bus_off; | |
2335 | } | |
3384f95c | 2336 | |
3384f95c DG |
2337 | /* Write PHB properties */ |
2338 | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); | |
2339 | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); | |
3384f95c DG |
2340 | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); |
2341 | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); | |
2342 | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); | |
b194df47 | 2343 | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); |
3384f95c | 2344 | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); |
3f7565c9 | 2345 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
8cbe71ec DG |
2346 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", |
2347 | spapr_irq_nr_msis(spapr))); | |
3384f95c | 2348 | |
ae4de14c AK |
2349 | /* Dynamic DMA window */ |
2350 | if (phb->ddw_enabled) { | |
2351 | _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable, | |
2352 | sizeof(ddw_applicable))); | |
2353 | _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions", | |
2354 | &ddw_extensions, sizeof(ddw_extensions))); | |
2355 | } | |
2356 | ||
4814401f | 2357 | /* Advertise NUMA via ibm,associativity */ |
4bcfa56c | 2358 | if (phb->numa_node != -1) { |
4814401f AK |
2359 | _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity, |
2360 | sizeof(associativity))); | |
2361 | } | |
2362 | ||
4d8d5467 | 2363 | /* Build the interrupt-map, this must matches what is done |
e8ec4adf | 2364 | * in pci_swizzle_map_irq_fn |
4d8d5467 BH |
2365 | */ |
2366 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", | |
2367 | &interrupt_map_mask, sizeof(interrupt_map_mask))); | |
7fb0bd34 DG |
2368 | for (i = 0; i < PCI_SLOT_MAX; i++) { |
2369 | for (j = 0; j < PCI_NUM_PINS; j++) { | |
2370 | uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; | |
e8ec4adf | 2371 | int lsi_num = pci_swizzle(i, j); |
7fb0bd34 DG |
2372 | |
2373 | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); | |
2374 | irqmap[1] = 0; | |
2375 | irqmap[2] = 0; | |
2376 | irqmap[3] = cpu_to_be32(j+1); | |
5c7adcf4 GK |
2377 | irqmap[4] = cpu_to_be32(intc_phandle); |
2378 | spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true); | |
7fb0bd34 | 2379 | } |
3384f95c | 2380 | } |
3384f95c DG |
2381 | /* Write interrupt map */ |
2382 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, | |
7fb0bd34 | 2383 | sizeof(interrupt_map))); |
3384f95c | 2384 | |
ae4de14c | 2385 | tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]); |
da34fed7 TH |
2386 | if (!tcet) { |
2387 | return -1; | |
2388 | } | |
ccf9ff85 AK |
2389 | spapr_dma_dt(fdt, bus_off, "ibm,dma-window", |
2390 | tcet->liobn, tcet->bus_offset, | |
2391 | tcet->nb_table << tcet->page_shift); | |
edded454 | 2392 | |
f130928d MR |
2393 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index); |
2394 | if (drc) { | |
2395 | uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc)); | |
2396 | ||
2397 | _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index, | |
2398 | sizeof(drc_index))); | |
2399 | } | |
2400 | ||
1d2d9742 ND |
2401 | /* Walk the bridges and program the bus numbers*/ |
2402 | spapr_phb_pci_enumerate(phb); | |
2403 | _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); | |
2404 | ||
466e8831 DG |
2405 | /* Walk the bridge and subordinate buses */ |
2406 | ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off); | |
2407 | if (ret < 0) { | |
62083979 MR |
2408 | return ret; |
2409 | } | |
2410 | ||
8ca63ba8 MA |
2411 | spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &err); |
2412 | if (err) { | |
2413 | error_report_err(err); | |
ec132efa AK |
2414 | } |
2415 | spapr_phb_nvgpu_ram_populate_dt(phb, fdt); | |
2416 | ||
3384f95c DG |
2417 | return 0; |
2418 | } | |
298a9710 | 2419 | |
fa28f71b AK |
2420 | void spapr_pci_rtas_init(void) |
2421 | { | |
3a3b8502 AK |
2422 | spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", |
2423 | rtas_read_pci_config); | |
2424 | spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", | |
2425 | rtas_write_pci_config); | |
2426 | spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", | |
2427 | rtas_ibm_read_pci_config); | |
2428 | spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", | |
2429 | rtas_ibm_write_pci_config); | |
226419d6 | 2430 | if (msi_nonbroken) { |
3a3b8502 AK |
2431 | spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, |
2432 | "ibm,query-interrupt-source-number", | |
0ee2c058 | 2433 | rtas_ibm_query_interrupt_source_number); |
3a3b8502 AK |
2434 | spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", |
2435 | rtas_ibm_change_msi); | |
0ee2c058 | 2436 | } |
ee954280 GS |
2437 | |
2438 | spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, | |
2439 | "ibm,set-eeh-option", | |
2440 | rtas_ibm_set_eeh_option); | |
2441 | spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, | |
2442 | "ibm,get-config-addr-info2", | |
2443 | rtas_ibm_get_config_addr_info2); | |
2444 | spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, | |
2445 | "ibm,read-slot-reset-state2", | |
2446 | rtas_ibm_read_slot_reset_state2); | |
2447 | spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, | |
2448 | "ibm,set-slot-reset", | |
2449 | rtas_ibm_set_slot_reset); | |
2450 | spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, | |
2451 | "ibm,configure-pe", | |
2452 | rtas_ibm_configure_pe); | |
2453 | spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, | |
2454 | "ibm,slot-error-detail", | |
2455 | rtas_ibm_slot_error_detail); | |
fa28f71b AK |
2456 | } |
2457 | ||
8c9f64df | 2458 | static void spapr_pci_register_types(void) |
298a9710 DG |
2459 | { |
2460 | type_register_static(&spapr_phb_info); | |
2461 | } | |
8c9f64df AF |
2462 | |
2463 | type_init(spapr_pci_register_types) | |
eefaccc0 DG |
2464 | |
2465 | static int spapr_switch_one_vga(DeviceState *dev, void *opaque) | |
2466 | { | |
2467 | bool be = *(bool *)opaque; | |
2468 | ||
2469 | if (object_dynamic_cast(OBJECT(dev), "VGA") | |
2470 | || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { | |
2471 | object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", | |
2472 | &error_abort); | |
2473 | } | |
2474 | return 0; | |
2475 | } | |
2476 | ||
2477 | void spapr_pci_switch_vga(bool big_endian) | |
2478 | { | |
ce2918cb DG |
2479 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
2480 | SpaprPhbState *sphb; | |
eefaccc0 DG |
2481 | |
2482 | /* | |
2483 | * For backward compatibility with existing guests, we switch | |
2484 | * the endianness of the VGA controller when changing the guest | |
2485 | * interrupt mode | |
2486 | */ | |
2487 | QLIST_FOREACH(sphb, &spapr->phbs, list) { | |
2488 | BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; | |
2489 | qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, | |
2490 | &big_endian); | |
2491 | } | |
2492 | } |