[mirror_qemu.git] / hw / riscv / sifive_u.c

/*
 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
 *
 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
 * Copyright (c) 2017 SiFive, Inc.
 *
 * Provides a board compatible with the SiFive Freedom U SDK:
 *
 * 0) UART
 * 1) CLINT (Core Level Interruptor)
 * 2) PLIC (Platform Level Interrupt Controller)
 *
 * This board currently uses a hardcoded devicetree that indicates one hart.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/hw.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "exec/address-spaces.h"

#include <libfdt.h>

static const struct MemmapEntry {
    hwaddr base;
    hwaddr size;
} sifive_u_memmap[] = {
    [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
    [SIFIVE_U_MROM] =     {     0x1000,    0x11000 },
    [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
    [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
    [SIFIVE_U_UART0] =    { 0x10013000,     0x1000 },
    [SIFIVE_U_UART1] =    { 0x10023000,     0x1000 },
    [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
    [SIFIVE_U_GEM] =      { 0x100900FC,     0x2000 },
};

#define GEM_REVISION        0x10070109

static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
    uint64_t mem_size, const char *cmdline)
{
    void *fdt;
    int cpu;
    uint32_t *cells;
    char *nodename;
    char ethclk_names[] = "pclk\0hclk\0tx_clk";
    uint32_t plic_phandle, ethclk_phandle, phandle = 1;

    fdt = s->fdt = create_device_tree(&s->fdt_size);
    if (!fdt) {
        error_report("create_device_tree() failed");
        exit(1);
    }

    qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
    qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
    qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
    qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);

    qemu_fdt_add_subnode(fdt, "/soc");
    qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
    qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
    qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);

    nodename = g_strdup_printf("/memory@%lx",
        (long)memmap[SIFIVE_U_DRAM].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
        mem_size >> 32, mem_size);
    qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
    g_free(nodename);

    qemu_fdt_add_subnode(fdt, "/cpus");
    qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
        SIFIVE_CLINT_TIMEBASE_FREQ);
    qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
    qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);

    for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) {
        int cpu_phandle = phandle++;
        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]);
        qemu_fdt_add_subnode(fdt, nodename);
        qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
                              SIFIVE_U_CLOCK_FREQ);
        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
        qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
        qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
        qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
        qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
        qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
        qemu_fdt_add_subnode(fdt, intc);
        qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
        qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
        qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
        qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
        qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
        g_free(isa);
        g_free(intc);
        g_free(nodename);
    }

    cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4);
    for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
        nodename =
            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
        g_free(nodename);
    }
    nodename = g_strdup_printf("/soc/clint@%lx",
        (long)memmap[SIFIVE_U_CLINT].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[SIFIVE_U_CLINT].base,
        0x0, memmap[SIFIVE_U_CLINT].size);
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
        cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
    g_free(cells);
    g_free(nodename);

    plic_phandle = phandle++;
    cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4);
    for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
        nodename =
            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
        g_free(nodename);
    }
    nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
        (long)memmap[SIFIVE_U_PLIC].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
    qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
        cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[SIFIVE_U_PLIC].base,
        0x0, memmap[SIFIVE_U_PLIC].size);
    qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
    qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
    qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
    qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
    plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
    g_free(cells);
    g_free(nodename);

    ethclk_phandle = phandle++;
    nodename = g_strdup_printf("/soc/ethclk");
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
    qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
        SIFIVE_U_GEM_CLOCK_FREQ);
    qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);
    qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle);
    ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
    g_free(nodename);

    nodename = g_strdup_printf("/soc/ethernet@%lx",
        (long)memmap[SIFIVE_U_GEM].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[SIFIVE_U_GEM].base,
        0x0, memmap[SIFIVE_U_GEM].size);
    qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
    qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
    qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
    qemu_fdt_setprop_cells(fdt, nodename, "clocks",
        ethclk_phandle, ethclk_phandle, ethclk_phandle);
    qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
        sizeof(ethclk_names));
    qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
    qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
    g_free(nodename);

    nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
        (long)memmap[SIFIVE_U_GEM].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
    g_free(nodename);

    nodename = g_strdup_printf("/soc/uart@%lx",
        (long)memmap[SIFIVE_U_UART0].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[SIFIVE_U_UART0].base,
        0x0, memmap[SIFIVE_U_UART0].size);
    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
                          SIFIVE_U_CLOCK_FREQ / 2);
    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
    qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);

    qemu_fdt_add_subnode(fdt, "/chosen");
    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
    if (cmdline) {
        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
    }
    g_free(nodename);
}

static void riscv_sifive_u_init(MachineState *machine)
{
    const struct MemmapEntry *memmap = sifive_u_memmap;

    SiFiveUState *s = g_new0(SiFiveUState, 1);
    MemoryRegion *system_memory = get_system_memory();
    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
    int i;

    /* Initialize SoC */
    object_initialize_child(OBJECT(machine), "soc", &s->soc,
                            sizeof(s->soc), TYPE_RISCV_U_SOC,
                            &error_abort, NULL);
    object_property_set_bool(OBJECT(&s->soc), true, "realized",
                            &error_abort);

    /* register RAM */
    memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
                           machine->ram_size, &error_fatal);
    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
                                main_mem);

    /* create device tree */
    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);

    if (machine->firmware) {
        riscv_load_firmware(machine->firmware, memmap[SIFIVE_U_DRAM].base);
    }

    if (machine->kernel_filename) {
        riscv_load_kernel(machine->kernel_filename);
    }

    /* reset vector */
    uint32_t reset_vec[8] = {
        0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
        0x02028593,                    /*     addi   a1, t0, %pcrel_lo(1b) */
        0xf1402573,                    /*     csrr   a0, mhartid  */
#if defined(TARGET_RISCV32)
        0x0182a283,                    /*     lw     t0, 24(t0) */
#elif defined(TARGET_RISCV64)
        0x0182b283,                    /*     ld     t0, 24(t0) */
#endif
        0x00028067,                    /*     jr     t0 */
        0x00000000,
        memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
        0x00000000,
                                       /* dtb: */
    };

    /* copy in the reset vector in little_endian byte order */
    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
        reset_vec[i] = cpu_to_le32(reset_vec[i]);
    }
    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
                          memmap[SIFIVE_U_MROM].base, &address_space_memory);

    /* copy in the device tree */
    if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
            memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
        error_report("not enough space to store device-tree");
        exit(1);
    }
    qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
    rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
                          memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
                          &address_space_memory);
}

static void riscv_sifive_u_soc_init(Object *obj)
{
    SiFiveUSoCState *s = RISCV_U_SOC(obj);

    object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
                            TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
    object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
                            &error_abort);
    object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
                            &error_abort);

    sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
                          TYPE_CADENCE_GEM);
}

static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
{
    SiFiveUSoCState *s = RISCV_U_SOC(dev);
    const struct MemmapEntry *memmap = sifive_u_memmap;
    MemoryRegion *system_memory = get_system_memory();
    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
    qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
    char *plic_hart_config;
    size_t plic_hart_config_len;
    int i;
    Error *err = NULL;
    NICInfo *nd = &nd_table[0];

    object_property_set_bool(OBJECT(&s->cpus), true, "realized",
                             &error_abort);

    /* boot rom */
    memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
                           memmap[SIFIVE_U_MROM].size, &error_fatal);
    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
                                mask_rom);

    /* create PLIC hart topology configuration string */
    plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * smp_cpus;
    plic_hart_config = g_malloc0(plic_hart_config_len);
    for (i = 0; i < smp_cpus; i++) {
        if (i != 0) {
            strncat(plic_hart_config, ",", plic_hart_config_len);
        }
        strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG,
                plic_hart_config_len);
        plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
    }

    /* MMIO */
    s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
        plic_hart_config,
        SIFIVE_U_PLIC_NUM_SOURCES,
        SIFIVE_U_PLIC_NUM_PRIORITIES,
        SIFIVE_U_PLIC_PRIORITY_BASE,
        SIFIVE_U_PLIC_PENDING_BASE,
        SIFIVE_U_PLIC_ENABLE_BASE,
        SIFIVE_U_PLIC_ENABLE_STRIDE,
        SIFIVE_U_PLIC_CONTEXT_BASE,
        SIFIVE_U_PLIC_CONTEXT_STRIDE,
        memmap[SIFIVE_U_PLIC].size);
    sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
        serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
    sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
        serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
    sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
        memmap[SIFIVE_U_CLINT].size, smp_cpus,
        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);

    for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
        plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
    }

    if (nd->used) {
        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
        qdev_set_nic_properties(DEVICE(&s->gem), nd);
    }
    object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
                            &error_abort);
    object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
                       plic_gpios[SIFIVE_U_GEM_IRQ]);
}

static void riscv_sifive_u_machine_init(MachineClass *mc)
{
    mc->desc = "RISC-V Board compatible with SiFive U SDK";
    mc->init = riscv_sifive_u_init;
    /* The real hardware has 5 CPUs, but one of them is a small embedded power
     * management CPU.
     */
    mc->max_cpus = 4;
}

DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)

static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = riscv_sifive_u_soc_realize;
    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
    dc->user_creatable = false;
}

static const TypeInfo riscv_sifive_u_soc_type_info = {
    .name = TYPE_RISCV_U_SOC,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(SiFiveUSoCState),
    .instance_init = riscv_sifive_u_soc_init,
    .class_init = riscv_sifive_u_soc_class_init,
};

static void riscv_sifive_u_soc_register_types(void)
{
    type_register_static(&riscv_sifive_u_soc_type_info);
}

type_init(riscv_sifive_u_soc_register_types)
Commit	Line	Data
a7240d1e MC	1	/*
	2	* QEMU RISC-V Board Compatible with SiFive Freedom U SDK
	3	*
	4	* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
	5	* Copyright (c) 2017 SiFive, Inc.
	6	*
	7	* Provides a board compatible with the SiFive Freedom U SDK:
	8	*
	9	* 0) UART
	10	* 1) CLINT (Core Level Interruptor)
	11	* 2) PLIC (Platform Level Interrupt Controller)
	12	*
	13	* This board currently uses a hardcoded devicetree that indicates one hart.
	14	*
	15	* This program is free software; you can redistribute it and/or modify it
	16	* under the terms and conditions of the GNU General Public License,
	17	* version 2 or later, as published by the Free Software Foundation.
	18	*
	19	* This program is distributed in the hope it will be useful, but WITHOUT
	20	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	21	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	22	* more details.
	23	*
	24	* You should have received a copy of the GNU General Public License along with
	25	* this program. If not, see <http://www.gnu.org/licenses/>.
	26	*/
	27
	28	#include "qemu/osdep.h"
	29	#include "qemu/log.h"
	30	#include "qemu/error-report.h"
	31	#include "qapi/error.h"
	32	#include "hw/hw.h"
	33	#include "hw/boards.h"
	34	#include "hw/loader.h"
	35	#include "hw/sysbus.h"
	36	#include "hw/char/serial.h"
	37	#include "target/riscv/cpu.h"
	38	#include "hw/riscv/riscv_hart.h"
	39	#include "hw/riscv/sifive_plic.h"
	40	#include "hw/riscv/sifive_clint.h"
	41	#include "hw/riscv/sifive_uart.h"
	42	#include "hw/riscv/sifive_prci.h"
	43	#include "hw/riscv/sifive_u.h"
0ac24d56	44	#include "hw/riscv/boot.h"
a7240d1e MC	45	#include "chardev/char.h"
	46	#include "sysemu/arch_init.h"
	47	#include "sysemu/device_tree.h"
	48	#include "exec/address-spaces.h"
a7240d1e	49
5aec3247 MC	50	#include <libfdt.h>
5aec3247 MC	51
a7240d1e MC	52	static const struct MemmapEntry {
	53	hwaddr base;
	54	hwaddr size;
	55	} sifive_u_memmap[] = {
	56	[SIFIVE_U_DEBUG] = { 0x0, 0x100 },
5aec3247	57	[SIFIVE_U_MROM] = { 0x1000, 0x11000 },
a7240d1e MC	58	[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
	59	[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
	60	[SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
	61	[SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
	62	[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
5a7f76a3	63	[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
a7240d1e MC	64	};
a7240d1e MC	65
5a7f76a3 AF	66	#define GEM_REVISION 0x10070109
5a7f76a3 AF	67
a7240d1e MC	68	static void create_fdt(SiFiveUState s, const struct MemmapEntry memmap,
	69	uint64_t mem_size, const char *cmdline)
	70	{
	71	void *fdt;
	72	int cpu;
	73	uint32_t *cells;
	74	char *nodename;
fe93582c	75	char ethclk_names[] = "pclk\0hclk\0tx_clk";
382cb439	76	uint32_t plic_phandle, ethclk_phandle, phandle = 1;
a7240d1e MC	77
	78	fdt = s->fdt = create_device_tree(&s->fdt_size);
	79	if (!fdt) {
	80	error_report("create_device_tree() failed");
	81	exit(1);
	82	}
	83
	84	qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
	85	qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
	86	qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
	87	qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
	88
	89	qemu_fdt_add_subnode(fdt, "/soc");
	90	qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
2a1a6f6d	91	qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
a7240d1e MC	92	qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
	93	qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
	94
	95	nodename = g_strdup_printf("/memory@%lx",
	96	(long)memmap[SIFIVE_U_DRAM].base);
	97	qemu_fdt_add_subnode(fdt, nodename);
	98	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	99	memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
	100	mem_size >> 32, mem_size);
	101	qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
	102	g_free(nodename);
	103
	104	qemu_fdt_add_subnode(fdt, "/cpus");
2a8756ed MC	105	qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
2a8756ed MC	106	SIFIVE_CLINT_TIMEBASE_FREQ);
a7240d1e MC	107	qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
	108	qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
	109
2308092b	110	for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) {
382cb439	111	int cpu_phandle = phandle++;
a7240d1e MC	112	nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
a7240d1e MC	113	char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
2308092b	114	char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]);
a7240d1e	115	qemu_fdt_add_subnode(fdt, nodename);
2a8756ed MC	116	qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
2a8756ed MC	117	SIFIVE_U_CLOCK_FREQ);
a7240d1e MC	118	qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
	119	qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
	120	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
	121	qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
	122	qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
	123	qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
	124	qemu_fdt_add_subnode(fdt, intc);
382cb439 BM	125	qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
382cb439 BM	126	qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
a7240d1e MC	127	qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
	128	qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
	129	qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
	130	g_free(isa);
	131	g_free(intc);
	132	g_free(nodename);
	133	}
	134
2308092b AF	135	cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4);
2308092b AF	136	for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
a7240d1e MC	137	nodename =
	138	g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	139	uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
	140	cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
	141	cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
	142	cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
	143	cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
	144	g_free(nodename);
	145	}
	146	nodename = g_strdup_printf("/soc/clint@%lx",
	147	(long)memmap[SIFIVE_U_CLINT].base);
	148	qemu_fdt_add_subnode(fdt, nodename);
	149	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
	150	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	151	0x0, memmap[SIFIVE_U_CLINT].base,
	152	0x0, memmap[SIFIVE_U_CLINT].size);
	153	qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
2308092b	154	cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
a7240d1e MC	155	g_free(cells);
	156	g_free(nodename);
	157
382cb439	158	plic_phandle = phandle++;
2308092b AF	159	cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4);
2308092b AF	160	for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
a7240d1e MC	161	nodename =
	162	g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	163	uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
	164	cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
	165	cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
	166	cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
	167	cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
	168	g_free(nodename);
	169	}
	170	nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
	171	(long)memmap[SIFIVE_U_PLIC].base);
	172	qemu_fdt_add_subnode(fdt, nodename);
	173	qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
	174	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
	175	qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
	176	qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
2308092b	177	cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
a7240d1e MC	178	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	179	0x0, memmap[SIFIVE_U_PLIC].base,
	180	0x0, memmap[SIFIVE_U_PLIC].size);
	181	qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
	182	qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
98ceee7f	183	qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
382cb439 BM	184	qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
382cb439 BM	185	qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
a7240d1e MC	186	plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
	187	g_free(cells);
	188	g_free(nodename);
	189
382cb439	190	ethclk_phandle = phandle++;
fe93582c AP	191	nodename = g_strdup_printf("/soc/ethclk");
	192	qemu_fdt_add_subnode(fdt, nodename);
	193	qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
	194	qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
	195	qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
	196	SIFIVE_U_GEM_CLOCK_FREQ);
382cb439 BM	197	qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);
382cb439 BM	198	qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle);
fe93582c AP	199	ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
	200	g_free(nodename);
	201
5a7f76a3 AF	202	nodename = g_strdup_printf("/soc/ethernet@%lx",
	203	(long)memmap[SIFIVE_U_GEM].base);
	204	qemu_fdt_add_subnode(fdt, nodename);
	205	qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
	206	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	207	0x0, memmap[SIFIVE_U_GEM].base,
	208	0x0, memmap[SIFIVE_U_GEM].size);
	209	qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
	210	qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
	211	qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
	212	qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
fe93582c AP	213	qemu_fdt_setprop_cells(fdt, nodename, "clocks",
	214	ethclk_phandle, ethclk_phandle, ethclk_phandle);
	215	qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
	216	sizeof(ethclk_names));
5a7f76a3 AF	217	qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
	218	qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
	219	g_free(nodename);
	220
	221	nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
	222	(long)memmap[SIFIVE_U_GEM].base);
	223	qemu_fdt_add_subnode(fdt, nodename);
	224	qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
	225	g_free(nodename);
	226
bde3ab9a	227	nodename = g_strdup_printf("/soc/uart@%lx",
a7240d1e MC	228	(long)memmap[SIFIVE_U_UART0].base);
	229	qemu_fdt_add_subnode(fdt, nodename);
	230	qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
	231	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	232	0x0, memmap[SIFIVE_U_UART0].base,
	233	0x0, memmap[SIFIVE_U_UART0].size);
6c60757e AP	234	qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
6c60757e AP	235	SIFIVE_U_CLOCK_FREQ / 2);
a7240d1e	236	qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
a9ec1c76	237	qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
a7240d1e MC	238
	239	qemu_fdt_add_subnode(fdt, "/chosen");
	240	qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
7c28f4da MC	241	if (cmdline) {
	242	qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
	243	}
a7240d1e MC	244	g_free(nodename);
	245	}
	246
	247	static void riscv_sifive_u_init(MachineState *machine)
	248	{
	249	const struct MemmapEntry *memmap = sifive_u_memmap;
	250
	251	SiFiveUState *s = g_new0(SiFiveUState, 1);
5aec3247	252	MemoryRegion *system_memory = get_system_memory();
a7240d1e	253	MemoryRegion *main_mem = g_new(MemoryRegion, 1);
5aec3247	254	int i;
a7240d1e	255
2308092b	256	/* Initialize SoC */
4eea9d7d AF	257	object_initialize_child(OBJECT(machine), "soc", &s->soc,
	258	sizeof(s->soc), TYPE_RISCV_U_SOC,
	259	&error_abort, NULL);
a7240d1e MC	260	object_property_set_bool(OBJECT(&s->soc), true, "realized",
	261	&error_abort);
	262
	263	/* register RAM */
	264	memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
	265	machine->ram_size, &error_fatal);
5aec3247	266	memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
2308092b	267	main_mem);
a7240d1e MC	268
	269	/* create device tree */
	270	create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
	271
b3042223 AF	272	if (machine->firmware) {
	273	riscv_load_firmware(machine->firmware, memmap[SIFIVE_U_DRAM].base);
	274	}
	275
a7240d1e	276	if (machine->kernel_filename) {
0ac24d56	277	riscv_load_kernel(machine->kernel_filename);
a7240d1e MC	278	}
	279
	280	/* reset vector */
	281	uint32_t reset_vec[8] = {
	282	0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
	283	0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
	284	0xf1402573, /* csrr a0, mhartid */
	285	#if defined(TARGET_RISCV32)
	286	0x0182a283, /* lw t0, 24(t0) */
	287	#elif defined(TARGET_RISCV64)
	288	0x0182b283, /* ld t0, 24(t0) */
	289	#endif
	290	0x00028067, /* jr t0 */
	291	0x00000000,
	292	memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
	293	0x00000000,
	294	/* dtb: */
	295	};
	296
5aec3247 MC	297	/* copy in the reset vector in little_endian byte order */
	298	for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
	299	reset_vec[i] = cpu_to_le32(reset_vec[i]);
	300	}
	301	rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
	302	memmap[SIFIVE_U_MROM].base, &address_space_memory);
a7240d1e MC	303
a7240d1e MC	304	/* copy in the device tree */
5aec3247 MC	305	if (fdt_pack(s->fdt) \|\| fdt_totalsize(s->fdt) >
	306	memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
	307	error_report("not enough space to store device-tree");
	308	exit(1);
	309	}
	310	qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
	311	rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
	312	memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
	313	&address_space_memory);
2308092b AF	314	}
	315
	316	static void riscv_sifive_u_soc_init(Object *obj)
	317	{
	318	SiFiveUSoCState *s = RISCV_U_SOC(obj);
	319
4eea9d7d AF	320	object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
4eea9d7d AF	321	TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
2308092b AF	322	object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
	323	&error_abort);
	324	object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
	325	&error_abort);
5a7f76a3	326
4eea9d7d AF	327	sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
4eea9d7d AF	328	TYPE_CADENCE_GEM);
2308092b AF	329	}
	330
	331	static void riscv_sifive_u_soc_realize(DeviceState dev, Error *errp)
	332	{
	333	SiFiveUSoCState *s = RISCV_U_SOC(dev);
	334	const struct MemmapEntry *memmap = sifive_u_memmap;
	335	MemoryRegion *system_memory = get_system_memory();
	336	MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
5a7f76a3	337	qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
05446f41 BM	338	char *plic_hart_config;
05446f41 BM	339	size_t plic_hart_config_len;
5a7f76a3 AF	340	int i;
	341	Error *err = NULL;
	342	NICInfo *nd = &nd_table[0];
2308092b AF	343
	344	object_property_set_bool(OBJECT(&s->cpus), true, "realized",
	345	&error_abort);
	346
	347	/* boot rom */
	348	memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
	349	memmap[SIFIVE_U_MROM].size, &error_fatal);
	350	memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
	351	mask_rom);
a7240d1e	352
05446f41 BM	353	/* create PLIC hart topology configuration string */
	354	plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * smp_cpus;
	355	plic_hart_config = g_malloc0(plic_hart_config_len);
	356	for (i = 0; i < smp_cpus; i++) {
	357	if (i != 0) {
	358	strncat(plic_hart_config, ",", plic_hart_config_len);
	359	}
	360	strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG,
	361	plic_hart_config_len);
	362	plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
	363	}
	364
a7240d1e MC	365	/* MMIO */
a7240d1e MC	366	s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
05446f41	367	plic_hart_config,
a7240d1e MC	368	SIFIVE_U_PLIC_NUM_SOURCES,
	369	SIFIVE_U_PLIC_NUM_PRIORITIES,
	370	SIFIVE_U_PLIC_PRIORITY_BASE,
	371	SIFIVE_U_PLIC_PENDING_BASE,
	372	SIFIVE_U_PLIC_ENABLE_BASE,
	373	SIFIVE_U_PLIC_ENABLE_STRIDE,
	374	SIFIVE_U_PLIC_CONTEXT_BASE,
	375	SIFIVE_U_PLIC_CONTEXT_STRIDE,
	376	memmap[SIFIVE_U_PLIC].size);
5aec3247	377	sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
647a70a1	378	serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
194eef09 MC	379	sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
194eef09 MC	380	serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
a7240d1e MC	381	sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
	382	memmap[SIFIVE_U_CLINT].size, smp_cpus,
	383	SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
5a7f76a3 AF	384
	385	for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
	386	plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
	387	}
	388
	389	if (nd->used) {
	390	qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
	391	qdev_set_nic_properties(DEVICE(&s->gem), nd);
	392	}
	393	object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
	394	&error_abort);
	395	object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
	396	if (err) {
	397	error_propagate(errp, err);
	398	return;
	399	}
	400	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
	401	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
	402	plic_gpios[SIFIVE_U_GEM_IRQ]);
a7240d1e MC	403	}
a7240d1e MC	404
a7240d1e MC	405	static void riscv_sifive_u_machine_init(MachineClass *mc)
	406	{
	407	mc->desc = "RISC-V Board compatible with SiFive U SDK";
	408	mc->init = riscv_sifive_u_init;
8b1d0714 AF	409	/* The real hardware has 5 CPUs, but one of them is a small embedded power
	410	* management CPU.
	411	*/
	412	mc->max_cpus = 4;
a7240d1e MC	413	}
	414
	415	DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
2308092b AF	416
	417	static void riscv_sifive_u_soc_class_init(ObjectClass oc, void data)
	418	{
	419	DeviceClass *dc = DEVICE_CLASS(oc);
	420
	421	dc->realize = riscv_sifive_u_soc_realize;
	422	/* Reason: Uses serial_hds in realize function, thus can't be used twice */
	423	dc->user_creatable = false;
	424	}
	425
	426	static const TypeInfo riscv_sifive_u_soc_type_info = {
	427	.name = TYPE_RISCV_U_SOC,
	428	.parent = TYPE_DEVICE,
	429	.instance_size = sizeof(SiFiveUSoCState),
	430	.instance_init = riscv_sifive_u_soc_init,
	431	.class_init = riscv_sifive_u_soc_class_init,
	432	};
	433
	434	static void riscv_sifive_u_soc_register_types(void)
	435	{
	436	type_register_static(&riscv_sifive_u_soc_type_info);
	437	}
	438
	439	type_init(riscv_sifive_u_soc_register_types)