[mirror_qemu.git] / hw / riscv / virt.c

/*
 * QEMU RISC-V VirtIO Board
 *
 * Copyright (c) 2017 SiFive, Inc.
 *
 * RISC-V machine with 16550a UART and VirtIO MMIO
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/hw.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_test.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "exec/address-spaces.h"
#include "hw/pci/pci.h"
#include "hw/pci-host/gpex.h"

#include <libfdt.h>

static const struct MemmapEntry {
    hwaddr base;
    hwaddr size;
} virt_memmap[] = {
    [VIRT_DEBUG] =       {        0x0,         0x100 },
    [VIRT_MROM] =        {     0x1000,       0x11000 },
    [VIRT_TEST] =        {   0x100000,        0x1000 },
    [VIRT_CLINT] =       {  0x2000000,       0x10000 },
    [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
    [VIRT_UART0] =       { 0x10000000,         0x100 },
    [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
    [VIRT_DRAM] =        { 0x80000000,           0x0 },
    [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
    [VIRT_PCIE_PIO] =    { 0x03000000,    0x00010000 },
    [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
};

static void create_pcie_irq_map(void *fdt, char *nodename,
                                uint32_t plic_phandle)
{
    int pin, dev;
    uint32_t
        full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
    uint32_t *irq_map = full_irq_map;

    /* This code creates a standard swizzle of interrupts such that
     * each device's first interrupt is based on it's PCI_SLOT number.
     * (See pci_swizzle_map_irq_fn())
     *
     * We only need one entry per interrupt in the table (not one per
     * possible slot) seeing the interrupt-map-mask will allow the table
     * to wrap to any number of devices.
     */
    for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
        int devfn = dev * 0x8;

        for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
            int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
            int i = 0;

            irq_map[i] = cpu_to_be32(devfn << 8);

            i += FDT_PCI_ADDR_CELLS;
            irq_map[i] = cpu_to_be32(pin + 1);

            i += FDT_PCI_INT_CELLS;
            irq_map[i++] = cpu_to_be32(plic_phandle);

            i += FDT_PLIC_ADDR_CELLS;
            irq_map[i] = cpu_to_be32(irq_nr);

            irq_map += FDT_INT_MAP_WIDTH;
        }
    }

    qemu_fdt_setprop(fdt, nodename, "interrupt-map",
                     full_irq_map, sizeof(full_irq_map));

    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
                           0x1800, 0, 0, 0x7);
}

static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
    uint64_t mem_size, const char *cmdline)
{
    void *fdt;
    int cpu;
    uint32_t *cells;
    char *nodename;
    uint32_t plic_phandle, phandle = 1;
    int i;

    fdt = s->fdt = create_device_tree(&s->fdt_size);
    if (!fdt) {
        error_report("create_device_tree() failed");
        exit(1);
    }

    qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
    qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
    qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
    qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);

    qemu_fdt_add_subnode(fdt, "/soc");
    qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
    qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
    qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);

    nodename = g_strdup_printf("/memory@%lx",
        (long)memmap[VIRT_DRAM].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
        mem_size >> 32, mem_size);
    qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
    g_free(nodename);

    qemu_fdt_add_subnode(fdt, "/cpus");
    qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
                          SIFIVE_CLINT_TIMEBASE_FREQ);
    qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
    qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);

    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
        int cpu_phandle = phandle++;
        int intc_phandle;
        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        char *isa = riscv_isa_string(&s->soc.harts[cpu]);
        qemu_fdt_add_subnode(fdt, nodename);
        qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
                              VIRT_CLOCK_FREQ);
        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
        qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
        qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
        qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
        qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
        qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
        qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
        qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle);
        intc_phandle = phandle++;
        qemu_fdt_add_subnode(fdt, intc);
        qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
        qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle);
        qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
        qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
        qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
        g_free(isa);
        g_free(intc);
        g_free(nodename);
    }

    /* Add cpu-topology node */
    qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
    qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
        char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
                                              cpu);
        char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
        qemu_fdt_add_subnode(fdt, core_nodename);
        qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
        g_free(core_nodename);
        g_free(cpu_nodename);
    }

    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
        nodename =
            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
        g_free(nodename);
    }
    nodename = g_strdup_printf("/soc/clint@%lx",
        (long)memmap[VIRT_CLINT].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[VIRT_CLINT].base,
        0x0, memmap[VIRT_CLINT].size);
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
    g_free(cells);
    g_free(nodename);

    plic_phandle = phandle++;
    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
        nodename =
            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
        g_free(nodename);
    }
    nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
        (long)memmap[VIRT_PLIC].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
                           FDT_PLIC_ADDR_CELLS);
    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
                          FDT_PLIC_INT_CELLS);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
    qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[VIRT_PLIC].base,
        0x0, memmap[VIRT_PLIC].size);
    qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
    qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
    qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
    qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
    plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
    g_free(cells);
    g_free(nodename);

    for (i = 0; i < VIRTIO_COUNT; i++) {
        nodename = g_strdup_printf("/virtio_mmio@%lx",
            (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
        qemu_fdt_add_subnode(fdt, nodename);
        qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
        qemu_fdt_setprop_cells(fdt, nodename, "reg",
            0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
            0x0, memmap[VIRT_VIRTIO].size);
        qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
        qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
        g_free(nodename);
    }

    nodename = g_strdup_printf("/soc/pci@%lx",
        (long) memmap[VIRT_PCIE_ECAM].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
                           FDT_PCI_ADDR_CELLS);
    qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells",
                           FDT_PCI_INT_CELLS);
    qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2);
    qemu_fdt_setprop_string(fdt, nodename, "compatible",
                            "pci-host-ecam-generic");
    qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
    qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
    qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
                           memmap[VIRT_PCIE_ECAM].size /
                               PCIE_MMCFG_SIZE_MIN - 1);
    qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
    qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
                           0, memmap[VIRT_PCIE_ECAM].size);
    qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
        1, FDT_PCI_RANGE_IOPORT, 2, 0,
        2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
        1, FDT_PCI_RANGE_MMIO,
        2, memmap[VIRT_PCIE_MMIO].base,
        2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
    create_pcie_irq_map(fdt, nodename, plic_phandle);
    g_free(nodename);

    nodename = g_strdup_printf("/test@%lx",
        (long)memmap[VIRT_TEST].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[VIRT_TEST].base,
        0x0, memmap[VIRT_TEST].size);
    g_free(nodename);

    nodename = g_strdup_printf("/uart@%lx",
        (long)memmap[VIRT_UART0].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[VIRT_UART0].base,
        0x0, memmap[VIRT_UART0].size);
    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
        qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
        qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ);

    qemu_fdt_add_subnode(fdt, "/chosen");
    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
    if (cmdline) {
        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
    }
    g_free(nodename);

    return fdt;
}


static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
                                          hwaddr ecam_base, hwaddr ecam_size,
                                          hwaddr mmio_base, hwaddr mmio_size,
                                          hwaddr pio_base,
                                          DeviceState *plic, bool link_up)
{
    DeviceState *dev;
    MemoryRegion *ecam_alias, *ecam_reg;
    MemoryRegion *mmio_alias, *mmio_reg;
    qemu_irq irq;
    int i;

    dev = qdev_create(NULL, TYPE_GPEX_HOST);

    qdev_init_nofail(dev);

    ecam_alias = g_new0(MemoryRegion, 1);
    ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
    memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
                             ecam_reg, 0, ecam_size);
    memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);

    mmio_alias = g_new0(MemoryRegion, 1);
    mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
    memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
                             mmio_reg, mmio_base, mmio_size);
    memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);

    for (i = 0; i < GPEX_NUM_IRQS; i++) {
        irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);

        sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
        gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
    }

    return dev;
}

static void riscv_virt_board_init(MachineState *machine)
{
    const struct MemmapEntry *memmap = virt_memmap;

    RISCVVirtState *s = g_new0(RISCVVirtState, 1);
    MemoryRegion *system_memory = get_system_memory();
    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
    char *plic_hart_config;
    size_t plic_hart_config_len;
    int i;
    void *fdt;

    /* Initialize SOC */
    object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
                            TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
                            &error_abort);
    object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
                            &error_abort);
    object_property_set_bool(OBJECT(&s->soc), true, "realized",
                            &error_abort);

    /* register system main memory (actual RAM) */
    memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
                           machine->ram_size, &error_fatal);
    memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
        main_mem);

    /* create device tree */
    fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);

    /* boot rom */
    memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
                           memmap[VIRT_MROM].size, &error_fatal);
    memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
                                mask_rom);

    if (machine->firmware) {
        riscv_load_firmware(machine->firmware, memmap[VIRT_DRAM].base);
    }

    if (machine->kernel_filename) {
        uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);

        if (machine->initrd_filename) {
            hwaddr start;
            hwaddr end = riscv_load_initrd(machine->initrd_filename,
                                           machine->ram_size, kernel_entry,
                                           &start);
            qemu_fdt_setprop_cell(fdt, "/chosen",
                                  "linux,initrd-start", start);
            qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
                                  end);
        }
    }

    /* reset vector */
    uint32_t reset_vec[8] = {
        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
        0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
        0xf1402573,                  /*     csrr   a0, mhartid  */
#if defined(TARGET_RISCV32)
        0x0182a283,                  /*     lw     t0, 24(t0) */
#elif defined(TARGET_RISCV64)
        0x0182b283,                  /*     ld     t0, 24(t0) */
#endif
        0x00028067,                  /*     jr     t0 */
        0x00000000,
        memmap[VIRT_DRAM].base,      /* start: .dword memmap[VIRT_DRAM].base */
        0x00000000,
                                     /* dtb: */
    };

    /* copy in the reset vector in little_endian byte order */
    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
        reset_vec[i] = cpu_to_le32(reset_vec[i]);
    }
    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
                          memmap[VIRT_MROM].base, &address_space_memory);

    /* copy in the device tree */
    if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
            memmap[VIRT_MROM].size - sizeof(reset_vec)) {
        error_report("not enough space to store device-tree");
        exit(1);
    }
    qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
    rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
                          memmap[VIRT_MROM].base + sizeof(reset_vec),
                          &address_space_memory);

    /* create PLIC hart topology configuration string */
    plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
    plic_hart_config = g_malloc0(plic_hart_config_len);
    for (i = 0; i < smp_cpus; i++) {
        if (i != 0) {
            strncat(plic_hart_config, ",", plic_hart_config_len);
        }
        strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
        plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
    }

    /* MMIO */
    s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
        plic_hart_config,
        VIRT_PLIC_NUM_SOURCES,
        VIRT_PLIC_NUM_PRIORITIES,
        VIRT_PLIC_PRIORITY_BASE,
        VIRT_PLIC_PENDING_BASE,
        VIRT_PLIC_ENABLE_BASE,
        VIRT_PLIC_ENABLE_STRIDE,
        VIRT_PLIC_CONTEXT_BASE,
        VIRT_PLIC_CONTEXT_STRIDE,
        memmap[VIRT_PLIC].size);
    sifive_clint_create(memmap[VIRT_CLINT].base,
        memmap[VIRT_CLINT].size, smp_cpus,
        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
    sifive_test_create(memmap[VIRT_TEST].base);

    for (i = 0; i < VIRTIO_COUNT; i++) {
        sysbus_create_simple("virtio-mmio",
            memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
            qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
    }

    gpex_pcie_init(system_memory,
                         memmap[VIRT_PCIE_ECAM].base,
                         memmap[VIRT_PCIE_ECAM].size,
                         memmap[VIRT_PCIE_MMIO].base,
                         memmap[VIRT_PCIE_MMIO].size,
                         memmap[VIRT_PCIE_PIO].base,
                         DEVICE(s->plic), true);

    serial_mm_init(system_memory, memmap[VIRT_UART0].base,
        0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
        serial_hd(0), DEVICE_LITTLE_ENDIAN);

    g_free(plic_hart_config);
}

static void riscv_virt_board_machine_init(MachineClass *mc)
{
    mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
    mc->init = riscv_virt_board_init;
    mc->max_cpus = 8; /* hardcoded limit in BBL */
    mc->default_cpu_type = VIRT_CPU;
}

DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
Commit	Line	Data
04331d0b MC	1	/*
	2	* QEMU RISC-V VirtIO Board
	3	*
	4	* Copyright (c) 2017 SiFive, Inc.
	5	*
	6	* RISC-V machine with 16550a UART and VirtIO MMIO
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2 or later, as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include "qemu/osdep.h"
4bf46af7	22	#include "qemu/units.h"
04331d0b MC	23	#include "qemu/log.h"
	24	#include "qemu/error-report.h"
	25	#include "qapi/error.h"
	26	#include "hw/hw.h"
	27	#include "hw/boards.h"
	28	#include "hw/loader.h"
	29	#include "hw/sysbus.h"
	30	#include "hw/char/serial.h"
	31	#include "target/riscv/cpu.h"
04331d0b MC	32	#include "hw/riscv/riscv_hart.h"
	33	#include "hw/riscv/sifive_plic.h"
	34	#include "hw/riscv/sifive_clint.h"
	35	#include "hw/riscv/sifive_test.h"
	36	#include "hw/riscv/virt.h"
0ac24d56	37	#include "hw/riscv/boot.h"
04331d0b MC	38	#include "chardev/char.h"
	39	#include "sysemu/arch_init.h"
	40	#include "sysemu/device_tree.h"
	41	#include "exec/address-spaces.h"
6d56e396 AF	42	#include "hw/pci/pci.h"
6d56e396 AF	43	#include "hw/pci-host/gpex.h"
04331d0b	44
5aec3247 MC	45	#include <libfdt.h>
5aec3247 MC	46
04331d0b MC	47	static const struct MemmapEntry {
	48	hwaddr base;
	49	hwaddr size;
	50	} virt_memmap[] = {
bb1973aa AF	51	[VIRT_DEBUG] = { 0x0, 0x100 },
	52	[VIRT_MROM] = { 0x1000, 0x11000 },
	53	[VIRT_TEST] = { 0x100000, 0x1000 },
	54	[VIRT_CLINT] = { 0x2000000, 0x10000 },
	55	[VIRT_PLIC] = { 0xc000000, 0x4000000 },
	56	[VIRT_UART0] = { 0x10000000, 0x100 },
	57	[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
	58	[VIRT_DRAM] = { 0x80000000, 0x0 },
6d56e396 AF	59	[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
	60	[VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 },
	61	[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
04331d0b MC	62	};
04331d0b MC	63
6d56e396 AF	64	static void create_pcie_irq_map(void fdt, char nodename,
	65	uint32_t plic_phandle)
	66	{
	67	int pin, dev;
	68	uint32_t
	69	full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
	70	uint32_t *irq_map = full_irq_map;
	71
	72	/* This code creates a standard swizzle of interrupts such that
	73	* each device's first interrupt is based on it's PCI_SLOT number.
	74	* (See pci_swizzle_map_irq_fn())
	75	*
	76	* We only need one entry per interrupt in the table (not one per
	77	* possible slot) seeing the interrupt-map-mask will allow the table
	78	* to wrap to any number of devices.
	79	*/
	80	for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
	81	int devfn = dev * 0x8;
	82
	83	for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
	84	int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
	85	int i = 0;
	86
	87	irq_map[i] = cpu_to_be32(devfn << 8);
	88
	89	i += FDT_PCI_ADDR_CELLS;
	90	irq_map[i] = cpu_to_be32(pin + 1);
	91
	92	i += FDT_PCI_INT_CELLS;
	93	irq_map[i++] = cpu_to_be32(plic_phandle);
	94
	95	i += FDT_PLIC_ADDR_CELLS;
	96	irq_map[i] = cpu_to_be32(irq_nr);
	97
	98	irq_map += FDT_INT_MAP_WIDTH;
	99	}
	100	}
	101
	102	qemu_fdt_setprop(fdt, nodename, "interrupt-map",
	103	full_irq_map, sizeof(full_irq_map));
	104
	105	qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
	106	0x1800, 0, 0, 0x7);
	107	}
	108
04331d0b MC	109	static void create_fdt(RISCVVirtState s, const struct MemmapEntry *memmap,
	110	uint64_t mem_size, const char *cmdline)
	111	{
	112	void *fdt;
	113	int cpu;
	114	uint32_t *cells;
	115	char *nodename;
	116	uint32_t plic_phandle, phandle = 1;
	117	int i;
	118
	119	fdt = s->fdt = create_device_tree(&s->fdt_size);
	120	if (!fdt) {
	121	error_report("create_device_tree() failed");
	122	exit(1);
	123	}
	124
	125	qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
	126	qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
	127	qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
	128	qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
	129
	130	qemu_fdt_add_subnode(fdt, "/soc");
	131	qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
53f54508	132	qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
04331d0b MC	133	qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
	134	qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
	135
	136	nodename = g_strdup_printf("/memory@%lx",
	137	(long)memmap[VIRT_DRAM].base);
	138	qemu_fdt_add_subnode(fdt, nodename);
	139	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	140	memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
	141	mem_size >> 32, mem_size);
	142	qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
	143	g_free(nodename);
	144
	145	qemu_fdt_add_subnode(fdt, "/cpus");
2a8756ed MC	146	qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
2a8756ed MC	147	SIFIVE_CLINT_TIMEBASE_FREQ);
04331d0b MC	148	qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
	149	qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
	150
	151	for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
	152	int cpu_phandle = phandle++;
28a4df97	153	int intc_phandle;
04331d0b MC	154	nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
	155	char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	156	char *isa = riscv_isa_string(&s->soc.harts[cpu]);
	157	qemu_fdt_add_subnode(fdt, nodename);
2a8756ed MC	158	qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
2a8756ed MC	159	VIRT_CLOCK_FREQ);
04331d0b MC	160	qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
	161	qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
	162	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
	163	qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
	164	qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
	165	qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
28a4df97 AP	166	qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
	167	qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle);
	168	intc_phandle = phandle++;
04331d0b	169	qemu_fdt_add_subnode(fdt, intc);
28a4df97 AP	170	qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
28a4df97 AP	171	qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle);
04331d0b MC	172	qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
	173	qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
	174	qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
	175	g_free(isa);
	176	g_free(intc);
	177	g_free(nodename);
	178	}
	179
28a4df97 AP	180	/* Add cpu-topology node */
	181	qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
	182	qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
	183	for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
	184	char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
	185	cpu);
	186	char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
	187	uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
	188	qemu_fdt_add_subnode(fdt, core_nodename);
	189	qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
	190	g_free(core_nodename);
	191	g_free(cpu_nodename);
	192	}
	193
04331d0b MC	194	cells = g_new0(uint32_t, s->soc.num_harts * 4);
	195	for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
	196	nodename =
	197	g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	198	uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
	199	cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
	200	cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
	201	cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
	202	cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
	203	g_free(nodename);
	204	}
	205	nodename = g_strdup_printf("/soc/clint@%lx",
	206	(long)memmap[VIRT_CLINT].base);
	207	qemu_fdt_add_subnode(fdt, nodename);
	208	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
	209	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	210	0x0, memmap[VIRT_CLINT].base,
	211	0x0, memmap[VIRT_CLINT].size);
	212	qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
	213	cells, s->soc.num_harts * sizeof(uint32_t) * 4);
	214	g_free(cells);
	215	g_free(nodename);
	216
	217	plic_phandle = phandle++;
	218	cells = g_new0(uint32_t, s->soc.num_harts * 4);
	219	for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
	220	nodename =
	221	g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	222	uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
	223	cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
	224	cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
	225	cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
	226	cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
	227	g_free(nodename);
	228	}
	229	nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
	230	(long)memmap[VIRT_PLIC].base);
	231	qemu_fdt_add_subnode(fdt, nodename);
6d56e396 AF	232	qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
	233	FDT_PLIC_ADDR_CELLS);
	234	qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
	235	FDT_PLIC_INT_CELLS);
04331d0b MC	236	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
	237	qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
	238	qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
	239	cells, s->soc.num_harts * sizeof(uint32_t) * 4);
	240	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	241	0x0, memmap[VIRT_PLIC].base,
	242	0x0, memmap[VIRT_PLIC].size);
	243	qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
	244	qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
	245	qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
	246	qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
	247	qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
	248	plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
	249	g_free(cells);
	250	g_free(nodename);
	251
	252	for (i = 0; i < VIRTIO_COUNT; i++) {
	253	nodename = g_strdup_printf("/virtio_mmio@%lx",
	254	(long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
	255	qemu_fdt_add_subnode(fdt, nodename);
	256	qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
	257	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	258	0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
	259	0x0, memmap[VIRT_VIRTIO].size);
	260	qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
	261	qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
	262	g_free(nodename);
	263	}
	264
6d56e396 AF	265	nodename = g_strdup_printf("/soc/pci@%lx",
	266	(long) memmap[VIRT_PCIE_ECAM].base);
	267	qemu_fdt_add_subnode(fdt, nodename);
	268	qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
	269	FDT_PCI_ADDR_CELLS);
	270	qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells",
	271	FDT_PCI_INT_CELLS);
	272	qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2);
	273	qemu_fdt_setprop_string(fdt, nodename, "compatible",
	274	"pci-host-ecam-generic");
	275	qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
	276	qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
	277	qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
5b7ae1ce	278	memmap[VIRT_PCIE_ECAM].size /
6d56e396 AF	279	PCIE_MMCFG_SIZE_MIN - 1);
	280	qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
	281	qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
	282	0, memmap[VIRT_PCIE_ECAM].size);
	283	qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
	284	1, FDT_PCI_RANGE_IOPORT, 2, 0,
	285	2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
	286	1, FDT_PCI_RANGE_MMIO,
	287	2, memmap[VIRT_PCIE_MMIO].base,
	288	2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
	289	create_pcie_irq_map(fdt, nodename, plic_phandle);
	290	g_free(nodename);
	291
04331d0b MC	292	nodename = g_strdup_printf("/test@%lx",
	293	(long)memmap[VIRT_TEST].base);
	294	qemu_fdt_add_subnode(fdt, nodename);
	295	qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0");
	296	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	297	0x0, memmap[VIRT_TEST].base,
	298	0x0, memmap[VIRT_TEST].size);
632fb279	299	g_free(nodename);
04331d0b MC	300
	301	nodename = g_strdup_printf("/uart@%lx",
	302	(long)memmap[VIRT_UART0].base);
	303	qemu_fdt_add_subnode(fdt, nodename);
	304	qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
	305	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	306	0x0, memmap[VIRT_UART0].base,
	307	0x0, memmap[VIRT_UART0].size);
	308	qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
	309	qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
	310	qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ);
	311
	312	qemu_fdt_add_subnode(fdt, "/chosen");
	313	qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
7c28f4da MC	314	if (cmdline) {
	315	qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
	316	}
04331d0b MC	317	g_free(nodename);
	318
	319	return fdt;
	320	}
	321
6d56e396 AF	322
	323	static inline DeviceState gpex_pcie_init(MemoryRegion sys_mem,
	324	hwaddr ecam_base, hwaddr ecam_size,
	325	hwaddr mmio_base, hwaddr mmio_size,
	326	hwaddr pio_base,
	327	DeviceState *plic, bool link_up)
	328	{
	329	DeviceState *dev;
	330	MemoryRegion ecam_alias, ecam_reg;
	331	MemoryRegion mmio_alias, mmio_reg;
	332	qemu_irq irq;
	333	int i;
	334
	335	dev = qdev_create(NULL, TYPE_GPEX_HOST);
	336
	337	qdev_init_nofail(dev);
	338
	339	ecam_alias = g_new0(MemoryRegion, 1);
	340	ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
	341	memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
	342	ecam_reg, 0, ecam_size);
	343	memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
	344
	345	mmio_alias = g_new0(MemoryRegion, 1);
	346	mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
	347	memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
	348	mmio_reg, mmio_base, mmio_size);
	349	memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
	350
	351	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
	352
	353	for (i = 0; i < GPEX_NUM_IRQS; i++) {
	354	irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
	355
	356	sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
	357	gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
	358	}
	359
	360	return dev;
	361	}
	362
04331d0b MC	363	static void riscv_virt_board_init(MachineState *machine)
	364	{
	365	const struct MemmapEntry *memmap = virt_memmap;
	366
	367	RISCVVirtState *s = g_new0(RISCVVirtState, 1);
	368	MemoryRegion *system_memory = get_system_memory();
	369	MemoryRegion *main_mem = g_new(MemoryRegion, 1);
5aec3247	370	MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
04331d0b MC	371	char *plic_hart_config;
	372	size_t plic_hart_config_len;
	373	int i;
	374	void *fdt;
	375
	376	/* Initialize SOC */
a993cb15 AF	377	object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
a993cb15 AF	378	TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
ceb2ffd5	379	object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
04331d0b MC	380	&error_abort);
	381	object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
	382	&error_abort);
	383	object_property_set_bool(OBJECT(&s->soc), true, "realized",
	384	&error_abort);
	385
	386	/* register system main memory (actual RAM) */
	387	memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
	388	machine->ram_size, &error_fatal);
	389	memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
	390	main_mem);
	391
	392	/* create device tree */
	393	fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
	394
	395	/* boot rom */
5aec3247 MC	396	memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
	397	memmap[VIRT_MROM].size, &error_fatal);
	398	memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
	399	mask_rom);
04331d0b	400
b3042223 AF	401	if (machine->firmware) {
	402	riscv_load_firmware(machine->firmware, memmap[VIRT_DRAM].base);
	403	}
	404
04331d0b	405	if (machine->kernel_filename) {
0ac24d56	406	uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
04331d0b MC	407
	408	if (machine->initrd_filename) {
	409	hwaddr start;
0ac24d56 AF	410	hwaddr end = riscv_load_initrd(machine->initrd_filename,
	411	machine->ram_size, kernel_entry,
	412	&start);
04331d0b MC	413	qemu_fdt_setprop_cell(fdt, "/chosen",
	414	"linux,initrd-start", start);
	415	qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
	416	end);
	417	}
	418	}
	419
	420	/* reset vector */
	421	uint32_t reset_vec[8] = {
	422	0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
	423	0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
	424	0xf1402573, /* csrr a0, mhartid */
	425	#if defined(TARGET_RISCV32)
	426	0x0182a283, /* lw t0, 24(t0) */
	427	#elif defined(TARGET_RISCV64)
	428	0x0182b283, /* ld t0, 24(t0) */
	429	#endif
	430	0x00028067, /* jr t0 */
	431	0x00000000,
	432	memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].base */
	433	0x00000000,
	434	/* dtb: */
	435	};
	436
5aec3247 MC	437	/* copy in the reset vector in little_endian byte order */
	438	for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
	439	reset_vec[i] = cpu_to_le32(reset_vec[i]);
	440	}
	441	rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
	442	memmap[VIRT_MROM].base, &address_space_memory);
04331d0b MC	443
04331d0b MC	444	/* copy in the device tree */
5aec3247 MC	445	if (fdt_pack(s->fdt) \|\| fdt_totalsize(s->fdt) >
	446	memmap[VIRT_MROM].size - sizeof(reset_vec)) {
	447	error_report("not enough space to store device-tree");
	448	exit(1);
	449	}
	450	qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
	451	rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
	452	memmap[VIRT_MROM].base + sizeof(reset_vec),
	453	&address_space_memory);
04331d0b MC	454
	455	/* create PLIC hart topology configuration string */
	456	plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
	457	plic_hart_config = g_malloc0(plic_hart_config_len);
	458	for (i = 0; i < smp_cpus; i++) {
	459	if (i != 0) {
	460	strncat(plic_hart_config, ",", plic_hart_config_len);
	461	}
	462	strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
	463	plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
	464	}
	465
	466	/* MMIO */
	467	s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
	468	plic_hart_config,
	469	VIRT_PLIC_NUM_SOURCES,
	470	VIRT_PLIC_NUM_PRIORITIES,
	471	VIRT_PLIC_PRIORITY_BASE,
	472	VIRT_PLIC_PENDING_BASE,
	473	VIRT_PLIC_ENABLE_BASE,
	474	VIRT_PLIC_ENABLE_STRIDE,
	475	VIRT_PLIC_CONTEXT_BASE,
	476	VIRT_PLIC_CONTEXT_STRIDE,
	477	memmap[VIRT_PLIC].size);
	478	sifive_clint_create(memmap[VIRT_CLINT].base,
	479	memmap[VIRT_CLINT].size, smp_cpus,
	480	SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
	481	sifive_test_create(memmap[VIRT_TEST].base);
	482
	483	for (i = 0; i < VIRTIO_COUNT; i++) {
	484	sysbus_create_simple("virtio-mmio",
	485	memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
647a70a1	486	qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
04331d0b MC	487	}
04331d0b MC	488
6d56e396 AF	489	gpex_pcie_init(system_memory,
	490	memmap[VIRT_PCIE_ECAM].base,
	491	memmap[VIRT_PCIE_ECAM].size,
	492	memmap[VIRT_PCIE_MMIO].base,
	493	memmap[VIRT_PCIE_MMIO].size,
	494	memmap[VIRT_PCIE_PIO].base,
	495	DEVICE(s->plic), true);
	496
04331d0b	497	serial_mm_init(system_memory, memmap[VIRT_UART0].base,
647a70a1	498	0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
9bca0edb	499	serial_hd(0), DEVICE_LITTLE_ENDIAN);
b6aa6ced MC	500
b6aa6ced MC	501	g_free(plic_hart_config);
04331d0b MC	502	}
04331d0b MC	503
04331d0b MC	504	static void riscv_virt_board_machine_init(MachineClass *mc)
04331d0b MC	505	{
77ff5bba	506	mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
04331d0b MC	507	mc->init = riscv_virt_board_init;
04331d0b MC	508	mc->max_cpus = 8; /* hardcoded limit in BBL */
ceb2ffd5	509	mc->default_cpu_type = VIRT_CPU;
04331d0b MC	510	}
	511
	512	DEFINE_MACHINE("virt", riscv_virt_board_machine_init)