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error: Eliminate error_propagate() with Coccinelle, part 1
[mirror_qemu.git] / hw / s390x / css.c
CommitLineData
df1fe5bb
CH		 1/*
2 * Channel subsystem base support.
3 *
4 * Copyright 2012 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
9 * directory.
10 */
11
9615495a 12#include "qemu/osdep.h"
c1755b14 13#include "qapi/error.h"
06e686ea 14#include "qapi/visitor.h"
df1fe5bb 15#include "qemu/bitops.h"
8ed179c9 16#include "qemu/error-report.h"
fdfba1a2 17#include "exec/address-spaces.h"
df1fe5bb 18#include "cpu.h"
bd3f16ac 19#include "hw/s390x/ioinst.h"
a27bd6c7 20#include "hw/qdev-properties.h"
bd3f16ac 21#include "hw/s390x/css.h"
df1fe5bb 22#include "trace.h"
03cf077a 23#include "hw/s390x/s390_flic.h"
517ff12c 24#include "hw/s390x/s390-virtio-ccw.h"
8fadea24 25#include "hw/s390x/s390-ccw.h"
df1fe5bb
CH		 26
27typedef struct CrwContainer {
28 CRW crw;
29 QTAILQ_ENTRY(CrwContainer) sibling;
30} CrwContainer;
31
457af626
HP		 32static const VMStateDescription vmstate_crw = {
33 .name = "s390_crw",
34 .version_id = 1,
35 .minimum_version_id = 1,
36 .fields = (VMStateField[]) {
37 VMSTATE_UINT16(flags, CRW),
38 VMSTATE_UINT16(rsid, CRW),
39 VMSTATE_END_OF_LIST()
40 },
41};
42
43static const VMStateDescription vmstate_crw_container = {
44 .name = "s390_crw_container",
45 .version_id = 1,
46 .minimum_version_id = 1,
47 .fields = (VMStateField[]) {
48 VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW),
49 VMSTATE_END_OF_LIST()
50 },
51};
52
df1fe5bb
CH		 53typedef struct ChpInfo {
54 uint8_t in_use;
55 uint8_t type;
56 uint8_t is_virtual;
57} ChpInfo;
58
457af626
HP		 59static const VMStateDescription vmstate_chp_info = {
60 .name = "s390_chp_info",
61 .version_id = 1,
62 .minimum_version_id = 1,
63 .fields = (VMStateField[]) {
64 VMSTATE_UINT8(in_use, ChpInfo),
65 VMSTATE_UINT8(type, ChpInfo),
66 VMSTATE_UINT8(is_virtual, ChpInfo),
67 VMSTATE_END_OF_LIST()
68 }
69};
70
df1fe5bb
CH		 71typedef struct SubchSet {
72 SubchDev *sch[MAX_SCHID + 1];
73 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)];
74 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)];
75} SubchSet;
76
517ff12c
HP		 77static const VMStateDescription vmstate_scsw = {
78 .name = "s390_scsw",
79 .version_id = 1,
80 .minimum_version_id = 1,
81 .fields = (VMStateField[]) {
82 VMSTATE_UINT16(flags, SCSW),
83 VMSTATE_UINT16(ctrl, SCSW),
84 VMSTATE_UINT32(cpa, SCSW),
85 VMSTATE_UINT8(dstat, SCSW),
86 VMSTATE_UINT8(cstat, SCSW),
87 VMSTATE_UINT16(count, SCSW),
88 VMSTATE_END_OF_LIST()
89 }
90};
91
92static const VMStateDescription vmstate_pmcw = {
93 .name = "s390_pmcw",
94 .version_id = 1,
95 .minimum_version_id = 1,
96 .fields = (VMStateField[]) {
97 VMSTATE_UINT32(intparm, PMCW),
98 VMSTATE_UINT16(flags, PMCW),
99 VMSTATE_UINT16(devno, PMCW),
100 VMSTATE_UINT8(lpm, PMCW),
101 VMSTATE_UINT8(pnom, PMCW),
102 VMSTATE_UINT8(lpum, PMCW),
103 VMSTATE_UINT8(pim, PMCW),
104 VMSTATE_UINT16(mbi, PMCW),
105 VMSTATE_UINT8(pom, PMCW),
106 VMSTATE_UINT8(pam, PMCW),
107 VMSTATE_UINT8_ARRAY(chpid, PMCW, 8),
108 VMSTATE_UINT32(chars, PMCW),
109 VMSTATE_END_OF_LIST()
110 }
111};
112
113static const VMStateDescription vmstate_schib = {
114 .name = "s390_schib",
115 .version_id = 1,
116 .minimum_version_id = 1,
117 .fields = (VMStateField[]) {
118 VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW),
119 VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW),
120 VMSTATE_UINT64(mba, SCHIB),
121 VMSTATE_UINT8_ARRAY(mda, SCHIB, 4),
122 VMSTATE_END_OF_LIST()
123 }
124};
125
126
127static const VMStateDescription vmstate_ccw1 = {
128 .name = "s390_ccw1",
129 .version_id = 1,
130 .minimum_version_id = 1,
131 .fields = (VMStateField[]) {
132 VMSTATE_UINT8(cmd_code, CCW1),
133 VMSTATE_UINT8(flags, CCW1),
134 VMSTATE_UINT16(count, CCW1),
135 VMSTATE_UINT32(cda, CCW1),
136 VMSTATE_END_OF_LIST()
137 }
138};
139
140static const VMStateDescription vmstate_ciw = {
141 .name = "s390_ciw",
142 .version_id = 1,
143 .minimum_version_id = 1,
144 .fields = (VMStateField[]) {
145 VMSTATE_UINT8(type, CIW),
146 VMSTATE_UINT8(command, CIW),
147 VMSTATE_UINT16(count, CIW),
148 VMSTATE_END_OF_LIST()
149 }
150};
151
152static const VMStateDescription vmstate_sense_id = {
153 .name = "s390_sense_id",
154 .version_id = 1,
155 .minimum_version_id = 1,
156 .fields = (VMStateField[]) {
157 VMSTATE_UINT8(reserved, SenseId),
158 VMSTATE_UINT16(cu_type, SenseId),
159 VMSTATE_UINT8(cu_model, SenseId),
160 VMSTATE_UINT16(dev_type, SenseId),
161 VMSTATE_UINT8(dev_model, SenseId),
162 VMSTATE_UINT8(unused, SenseId),
163 VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW),
164 VMSTATE_END_OF_LIST()
165 }
166};
167
ff443fe6
HP		 168static const VMStateDescription vmstate_orb = {
169 .name = "s390_orb",
170 .version_id = 1,
171 .minimum_version_id = 1,
172 .fields = (VMStateField[]) {
173 VMSTATE_UINT32(intparm, ORB),
174 VMSTATE_UINT16(ctrl0, ORB),
175 VMSTATE_UINT8(lpm, ORB),
176 VMSTATE_UINT8(ctrl1, ORB),
177 VMSTATE_UINT32(cpa, ORB),
178 VMSTATE_END_OF_LIST()
179 }
180};
181
182static bool vmstate_schdev_orb_needed(void *opaque)
183{
184 return css_migration_enabled();
185}
186
187static const VMStateDescription vmstate_schdev_orb = {
188 .name = "s390_subch_dev/orb",
189 .version_id = 1,
190 .minimum_version_id = 1,
191 .needed = vmstate_schdev_orb_needed,
192 .fields = (VMStateField[]) {
193 VMSTATE_STRUCT(orb, SubchDev, 1, vmstate_orb, ORB),
194 VMSTATE_END_OF_LIST()
195 }
196};
197
517ff12c 198static int subch_dev_post_load(void *opaque, int version_id);
44b1ff31 199static int subch_dev_pre_save(void *opaque);
517ff12c
HP		 200
201const char err_hint_devno[] = "Devno mismatch, tried to load wrong section!"
202 " Likely reason: some sequences of plug and unplug can break"
203 " migration for machine versions prior to 2.7 (known design flaw).";
204
205const VMStateDescription vmstate_subch_dev = {
206 .name = "s390_subch_dev",
207 .version_id = 1,
208 .minimum_version_id = 1,
209 .post_load = subch_dev_post_load,
210 .pre_save = subch_dev_pre_save,
211 .fields = (VMStateField[]) {
212 VMSTATE_UINT8_EQUAL(cssid, SubchDev, "Bug!"),
213 VMSTATE_UINT8_EQUAL(ssid, SubchDev, "Bug!"),
214 VMSTATE_UINT16(migrated_schid, SubchDev),
215 VMSTATE_UINT16_EQUAL(devno, SubchDev, err_hint_devno),
216 VMSTATE_BOOL(thinint_active, SubchDev),
217 VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB),
218 VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32),
219 VMSTATE_UINT64(channel_prog, SubchDev),
220 VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1),
221 VMSTATE_BOOL(last_cmd_valid, SubchDev),
222 VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId),
223 VMSTATE_BOOL(ccw_fmt_1, SubchDev),
224 VMSTATE_UINT8(ccw_no_data_cnt, SubchDev),
225 VMSTATE_END_OF_LIST()
ff443fe6
HP		 226 },
227 .subsections = (const VMStateDescription * []) {
228 &vmstate_schdev_orb,
229 NULL
517ff12c
HP		 230 }
231};
232
233typedef struct IndAddrPtrTmp {
234 IndAddr **parent;
235 uint64_t addr;
236 int32_t len;
237} IndAddrPtrTmp;
238
239static int post_load_ind_addr(void *opaque, int version_id)
240{
241 IndAddrPtrTmp *ptmp = opaque;
242 IndAddr **ind_addr = ptmp->parent;
243
244 if (ptmp->len != 0) {
245 *ind_addr = get_indicator(ptmp->addr, ptmp->len);
246 } else {
247 *ind_addr = NULL;
248 }
249 return 0;
250}
251
44b1ff31 252static int pre_save_ind_addr(void *opaque)
517ff12c
HP		 253{
254 IndAddrPtrTmp *ptmp = opaque;
255 IndAddr *ind_addr = *(ptmp->parent);
256
257 if (ind_addr != NULL) {
258 ptmp->len = ind_addr->len;
259 ptmp->addr = ind_addr->addr;
260 } else {
261 ptmp->len = 0;
262 ptmp->addr = 0L;
263 }
44b1ff31
DDAG		 264
265 return 0;
517ff12c
HP		 266}
267
268const VMStateDescription vmstate_ind_addr_tmp = {
269 .name = "s390_ind_addr_tmp",
270 .pre_save = pre_save_ind_addr,
271 .post_load = post_load_ind_addr,
272
273 .fields = (VMStateField[]) {
274 VMSTATE_INT32(len, IndAddrPtrTmp),
275 VMSTATE_UINT64(addr, IndAddrPtrTmp),
276 VMSTATE_END_OF_LIST()
277 }
278};
279
280const VMStateDescription vmstate_ind_addr = {
281 .name = "s390_ind_addr_tmp",
282 .fields = (VMStateField[]) {
283 VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp),
284 VMSTATE_END_OF_LIST()
285 }
286};
287
df1fe5bb
CH		 288typedef struct CssImage {
289 SubchSet *sch_set[MAX_SSID + 1];
290 ChpInfo chpids[MAX_CHPID + 1];
291} CssImage;
292
457af626
HP		 293static const VMStateDescription vmstate_css_img = {
294 .name = "s390_css_img",
295 .version_id = 1,
296 .minimum_version_id = 1,
297 .fields = (VMStateField[]) {
298 /* Subchannel sets have no relevant state. */
299 VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0,
300 vmstate_chp_info, ChpInfo),
301 VMSTATE_END_OF_LIST()
302 }
303
304};
305
03cf077a
CH		 306typedef struct IoAdapter {
307 uint32_t id;
308 uint8_t type;
309 uint8_t isc;
1497c160 310 uint8_t flags;
03cf077a
CH		 311} IoAdapter;
312
df1fe5bb
CH		 313typedef struct ChannelSubSys {
314 QTAILQ_HEAD(, CrwContainer) pending_crws;
c81b4f89 315 bool sei_pending;
df1fe5bb
CH		 316 bool do_crw_mchk;
317 bool crws_lost;
318 uint8_t max_cssid;
319 uint8_t max_ssid;
320 bool chnmon_active;
321 uint64_t chnmon_area;
322 CssImage *css[MAX_CSSID + 1];
323 uint8_t default_cssid;
457af626 324 /* don't migrate, see css_register_io_adapters */
dde522bb 325 IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1];
457af626 326 /* don't migrate, see get_indicator and IndAddrPtrTmp */
a28d8391 327 QTAILQ_HEAD(, IndAddr) indicator_addresses;
df1fe5bb
CH		 328} ChannelSubSys;
329
457af626
HP		 330static const VMStateDescription vmstate_css = {
331 .name = "s390_css",
332 .version_id = 1,
333 .minimum_version_id = 1,
334 .fields = (VMStateField[]) {
335 VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container,
336 CrwContainer, sibling),
337 VMSTATE_BOOL(sei_pending, ChannelSubSys),
338 VMSTATE_BOOL(do_crw_mchk, ChannelSubSys),
339 VMSTATE_BOOL(crws_lost, ChannelSubSys),
340 /* These were kind of migrated by virtio */
341 VMSTATE_UINT8(max_cssid, ChannelSubSys),
342 VMSTATE_UINT8(max_ssid, ChannelSubSys),
343 VMSTATE_BOOL(chnmon_active, ChannelSubSys),
344 VMSTATE_UINT64(chnmon_area, ChannelSubSys),
345 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1,
346 0, vmstate_css_img, CssImage),
347 VMSTATE_UINT8(default_cssid, ChannelSubSys),
348 VMSTATE_END_OF_LIST()
349 }
350};
351
bc994b74
EH		 352static ChannelSubSys channel_subsys = {
353 .pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws),
354 .do_crw_mchk = true,
355 .sei_pending = false,
356 .do_crw_mchk = true,
357 .crws_lost = false,
358 .chnmon_active = false,
bc994b74
EH		 359 .indicator_addresses =
360 QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses),
361};
df1fe5bb 362
44b1ff31 363static int subch_dev_pre_save(void *opaque)
517ff12c
HP		 364{
365 SubchDev *s = opaque;
366
367 /* Prepare remote_schid for save */
368 s->migrated_schid = s->schid;
44b1ff31
DDAG		 369
370 return 0;
517ff12c
HP		 371}
372
373static int subch_dev_post_load(void *opaque, int version_id)
374{
375
376 SubchDev *s = opaque;
377
378 /* Re-assign the subchannel to remote_schid if necessary */
379 if (s->migrated_schid != s->schid) {
380 if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) {
381 /*
382 * Cleanup the slot before moving to s->migrated_schid provided
383 * it still belongs to us, i.e. it was not changed by previous
384 * invocation of this function.
385 */
386 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL);
387 }
388 /* It's OK to re-assign without a prior de-assign. */
389 s->schid = s->migrated_schid;
390 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s);
391 }
392
457af626
HP		 393 if (css_migration_enabled()) {
394 /* No compat voodoo to do ;) */
395 return 0;
396 }
517ff12c
HP		 397 /*
398 * Hack alert. If we don't migrate the channel subsystem status
399 * we still need to find out if the guest enabled mss/mcss-e.
400 * If the subchannel is enabled, it certainly was able to access it,
401 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid
402 * values. This is not watertight, but better than nothing.
403 */
404 if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) {
405 if (s->ssid) {
406 channel_subsys.max_ssid = MAX_SSID;
407 }
408 if (s->cssid != channel_subsys.default_cssid) {
409 channel_subsys.max_cssid = MAX_CSSID;
410 }
411 }
412 return 0;
413}
414
e996583e
HP		 415void css_register_vmstate(void)
416{
417 vmstate_register(NULL, 0, &vmstate_css, &channel_subsys);
418}
419
a28d8391
YMZ		 420IndAddr *get_indicator(hwaddr ind_addr, int len)
421{
422 IndAddr *indicator;
423
562f5e0b 424 QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) {
a28d8391
YMZ		 425 if (indicator->addr == ind_addr) {
426 indicator->refcnt++;
427 return indicator;
428 }
429 }
430 indicator = g_new0(IndAddr, 1);
431 indicator->addr = ind_addr;
432 indicator->len = len;
433 indicator->refcnt = 1;
562f5e0b 434 QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses,
a28d8391
YMZ		 435 indicator, sibling);
436 return indicator;
437}
438
439static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr,
440 bool do_map)
441{
442 S390FLICState *fs = s390_get_flic();
6762808f 443 S390FLICStateClass *fsc = s390_get_flic_class(fs);
a28d8391
YMZ		 444
445 return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map);
446}
447
448void release_indicator(AdapterInfo *adapter, IndAddr *indicator)
449{
450 assert(indicator->refcnt > 0);
451 indicator->refcnt--;
452 if (indicator->refcnt > 0) {
453 return;
454 }
562f5e0b 455 QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling);
a28d8391
YMZ		 456 if (indicator->map) {
457 s390_io_adapter_map(adapter, indicator->map, false);
458 }
459 g_free(indicator);
460}
461
462int map_indicator(AdapterInfo *adapter, IndAddr *indicator)
463{
464 int ret;
465
466 if (indicator->map) {
467 return 0; /* already mapped is not an error */
468 }
469 indicator->map = indicator->addr;
470 ret = s390_io_adapter_map(adapter, indicator->map, true);
471 if ((ret != 0) && (ret != -ENOSYS)) {
472 goto out_err;
473 }
474 return 0;
475
476out_err:
477 indicator->map = 0;
478 return ret;
479}
480
df1fe5bb
CH		 481int css_create_css_image(uint8_t cssid, bool default_image)
482{
483 trace_css_new_image(cssid, default_image ? "(default)" : "");
882b3b97
CH		 484 /* 255 is reserved */
485 if (cssid == 255) {
df1fe5bb
CH		 486 return -EINVAL;
487 }
562f5e0b 488 if (channel_subsys.css[cssid]) {
df1fe5bb
CH		 489 return -EBUSY;
490 }
96f64aa8 491 channel_subsys.css[cssid] = g_new0(CssImage, 1);
df1fe5bb 492 if (default_image) {
562f5e0b 493 channel_subsys.default_cssid = cssid;
df1fe5bb
CH		 494 }
495 return 0;
496}
497
dde522bb 498uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc)
03cf077a 499{
dde522bb
FL		 500 if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC ||
501 !channel_subsys.io_adapters[type][isc]) {
502 return -1;
503 }
504
505 return channel_subsys.io_adapters[type][isc]->id;
506}
507
508/**
509 * css_register_io_adapters: Register I/O adapters per ISC during init
510 *
511 * @swap: an indication if byte swap is needed.
512 * @maskable: an indication if the adapter is subject to the mask operation.
1497c160
FL		 513 * @flags: further characteristics of the adapter.
514 * e.g. suppressible, an indication if the adapter is subject to AIS.
dde522bb
FL		 515 * @errp: location to store error information.
516 */
517void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
1497c160 518 uint8_t flags, Error **errp)
dde522bb
FL		 519{
520 uint32_t id;
521 int ret, isc;
03cf077a 522 IoAdapter *adapter;
03cf077a 523 S390FLICState *fs = s390_get_flic();
6762808f 524 S390FLICStateClass *fsc = s390_get_flic_class(fs);
03cf077a 525
dde522bb
FL		 526 /*
527 * Disallow multiple registrations for the same device type.
528 * Report an error if registering for an already registered type.
529 */
530 if (channel_subsys.io_adapters[type][0]) {
531 error_setg(errp, "Adapters for type %d already registered", type);
532 }
533
534 for (isc = 0; isc <= MAX_ISC; isc++) {
535 id = (type << 3) | isc;
1497c160 536 ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags);
dde522bb
FL		 537 if (ret == 0) {
538 adapter = g_new0(IoAdapter, 1);
539 adapter->id = id;
540 adapter->isc = isc;
541 adapter->type = type;
1497c160 542 adapter->flags = flags;
dde522bb
FL		 543 channel_subsys.io_adapters[type][isc] = adapter;
544 } else {
545 error_setg_errno(errp, -ret, "Unexpected error %d when "
546 "registering adapter %d", ret, id);
03cf077a
CH		 547 break;
548 }
03cf077a 549 }
dde522bb
FL		 550
551 /*
552 * No need to free registered adapters in kvm: kvm will clean up
553 * when the machine goes away.
554 */
555 if (ret) {
556 for (isc--; isc >= 0; isc--) {
557 g_free(channel_subsys.io_adapters[type][isc]);
558 channel_subsys.io_adapters[type][isc] = NULL;
559 }
03cf077a 560 }
dde522bb 561
03cf077a
CH		 562}
563
c1755b14
HP		 564static void css_clear_io_interrupt(uint16_t subchannel_id,
565 uint16_t subchannel_nr)
566{
567 Error *err = NULL;
568 static bool no_clear_irq;
569 S390FLICState *fs = s390_get_flic();
6762808f 570 S390FLICStateClass *fsc = s390_get_flic_class(fs);
c1755b14
HP		 571 int r;
572
573 if (unlikely(no_clear_irq)) {
574 return;
575 }
576 r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr);
577 switch (r) {
578 case 0:
579 break;
580 case -ENOSYS:
581 no_clear_irq = true;
582 /*
583 * Ignore unavailability, as the user can't do anything
584 * about it anyway.
585 */
586 break;
587 default:
588 error_setg_errno(&err, -r, "unexpected error condition");
589 error_propagate(&error_abort, err);
590 }
591}
592
593static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid)
df1fe5bb 594{
562f5e0b 595 if (channel_subsys.max_cssid > 0) {
c1755b14 596 return (cssid << 8) | (1 << 3) | (ssid << 1) | 1;
df1fe5bb 597 }
c1755b14
HP		 598 return (ssid << 1) | 1;
599}
600
601uint16_t css_build_subchannel_id(SubchDev *sch)
602{
603 return css_do_build_subchannel_id(sch->cssid, sch->ssid);
df1fe5bb
CH		 604}
605
8ca2b376 606void css_inject_io_interrupt(SubchDev *sch)
df1fe5bb 607{
df1fe5bb
CH		 608 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
609
610 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
611 sch->curr_status.pmcw.intparm, isc, "");
de13d216 612 s390_io_interrupt(css_build_subchannel_id(sch),
df1fe5bb
CH		 613 sch->schid,
614 sch->curr_status.pmcw.intparm,
91b0a8f3 615 isc << 27);
df1fe5bb
CH		 616}
617
618void css_conditional_io_interrupt(SubchDev *sch)
619{
6e9c893e
CH		 620 /*
621 * If the subchannel is not enabled, it is not made status pending
622 * (see PoP p. 16-17, "Status Control").
623 */
624 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA)) {
625 return;
626 }
627
df1fe5bb
CH		 628 /*
629 * If the subchannel is not currently status pending, make it pending
630 * with alert status.
631 */
632 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) {
df1fe5bb
CH		 633 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
634
635 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
636 sch->curr_status.pmcw.intparm, isc,
637 "(unsolicited)");
638 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
639 sch->curr_status.scsw.ctrl |=
640 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
641 /* Inject an I/O interrupt. */
de13d216 642 s390_io_interrupt(css_build_subchannel_id(sch),
df1fe5bb
CH		 643 sch->schid,
644 sch->curr_status.pmcw.intparm,
91b0a8f3 645 isc << 27);
df1fe5bb
CH		 646 }
647}
648
2283f4d6
FL		 649int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode)
650{
651 S390FLICState *fs = s390_get_flic();
6762808f 652 S390FLICStateClass *fsc = s390_get_flic_class(fs);
2283f4d6
FL		 653 int r;
654
655 if (env->psw.mask & PSW_MASK_PSTATE) {
656 r = -PGM_PRIVILEGED;
657 goto out;
658 }
659
660 trace_css_do_sic(mode, isc);
661 switch (mode) {
662 case SIC_IRQ_MODE_ALL:
663 case SIC_IRQ_MODE_SINGLE:
664 break;
665 default:
666 r = -PGM_OPERAND;
667 goto out;
668 }
669
670 r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0;
671out:
672 return r;
673}
674
25a08b8d 675void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc)
7e749462 676{
25a08b8d 677 S390FLICState *fs = s390_get_flic();
6762808f 678 S390FLICStateClass *fsc = s390_get_flic_class(fs);
7e749462 679 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI;
25a08b8d
YMZ		 680 IoAdapter *adapter = channel_subsys.io_adapters[type][isc];
681
682 if (!adapter) {
683 return;
684 }
7e749462
CH		 685
686 trace_css_adapter_interrupt(isc);
25a08b8d
YMZ		 687 if (fs->ais_supported) {
688 if (fsc->inject_airq(fs, type, isc, adapter->flags)) {
689 error_report("Failed to inject airq with AIS supported");
690 exit(1);
691 }
692 } else {
693 s390_io_interrupt(0, 0, 0, io_int_word);
694 }
7e749462
CH		 695}
696
df1fe5bb
CH		 697static void sch_handle_clear_func(SubchDev *sch)
698{
bea0279b 699 SCHIB *schib = &sch->curr_status;
df1fe5bb
CH		 700 int path;
701
702 /* Path management: In our simple css, we always choose the only path. */
703 path = 0x80;
704
4c293dc6 705 /* Reset values prior to 'issuing the clear signal'. */
bea0279b
DB		 706 schib->pmcw.lpum = 0;
707 schib->pmcw.pom = 0xff;
708 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO;
df1fe5bb
CH		 709
710 /* We always 'attempt to issue the clear signal', and we always succeed. */
df1fe5bb
CH		 711 sch->channel_prog = 0x0;
712 sch->last_cmd_valid = false;
bea0279b
DB		 713 schib->scsw.ctrl &= ~SCSW_ACTL_CLEAR_PEND;
714 schib->scsw.ctrl |= SCSW_STCTL_STATUS_PEND;
df1fe5bb 715
bea0279b
DB		 716 schib->scsw.dstat = 0;
717 schib->scsw.cstat = 0;
718 schib->pmcw.lpum = path;
df1fe5bb
CH		 719
720}
721
722static void sch_handle_halt_func(SubchDev *sch)
723{
bea0279b 724 SCHIB *schib = &sch->curr_status;
2ed982b6 725 hwaddr curr_ccw = sch->channel_prog;
df1fe5bb
CH		 726 int path;
727
728 /* Path management: In our simple css, we always choose the only path. */
729 path = 0x80;
730
731 /* We always 'attempt to issue the halt signal', and we always succeed. */
df1fe5bb
CH		 732 sch->channel_prog = 0x0;
733 sch->last_cmd_valid = false;
bea0279b
DB		 734 schib->scsw.ctrl &= ~SCSW_ACTL_HALT_PEND;
735 schib->scsw.ctrl |= SCSW_STCTL_STATUS_PEND;
df1fe5bb 736
bea0279b
DB		 737 if ((schib->scsw.ctrl & (SCSW_ACTL_SUBCH_ACTIVE |
738 SCSW_ACTL_DEVICE_ACTIVE)) ||
739 !((schib->scsw.ctrl & SCSW_ACTL_START_PEND) ||
740 (schib->scsw.ctrl & SCSW_ACTL_SUSP))) {
741 schib->scsw.dstat = SCSW_DSTAT_DEVICE_END;
df1fe5bb 742 }
bea0279b
DB		 743 if ((schib->scsw.ctrl & (SCSW_ACTL_SUBCH_ACTIVE |
744 SCSW_ACTL_DEVICE_ACTIVE)) ||
745 (schib->scsw.ctrl & SCSW_ACTL_SUSP)) {
746 schib->scsw.cpa = curr_ccw + 8;
2ed982b6 747 }
bea0279b
DB		 748 schib->scsw.cstat = 0;
749 schib->pmcw.lpum = path;
df1fe5bb
CH		 750
751}
752
729315eb
TH		 753/*
754 * As the SenseId struct cannot be packed (would cause unaligned accesses), we
755 * have to copy the individual fields to an unstructured area using the correct
756 * layout (see SA22-7204-01 "Common I/O-Device Commands").
757 */
758static void copy_sense_id_to_guest(uint8_t *dest, SenseId *src)
df1fe5bb
CH		 759{
760 int i;
761
729315eb
TH		 762 dest[0] = src->reserved;
763 stw_be_p(dest + 1, src->cu_type);
764 dest[3] = src->cu_model;
765 stw_be_p(dest + 4, src->dev_type);
766 dest[6] = src->dev_model;
767 dest[7] = src->unused;
768 for (i = 0; i < ARRAY_SIZE(src->ciw); i++) {
769 dest[8 + i * 4] = src->ciw[i].type;
770 dest[9 + i * 4] = src->ciw[i].command;
771 stw_be_p(dest + 10 + i * 4, src->ciw[i].count);
df1fe5bb
CH		 772 }
773}
774
a327c921 775static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1)
df1fe5bb 776{
a327c921
CH		 777 CCW0 tmp0;
778 CCW1 tmp1;
df1fe5bb
CH		 779 CCW1 ret;
780
a327c921
CH		 781 if (fmt1) {
782 cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1));
783 ret.cmd_code = tmp1.cmd_code;
784 ret.flags = tmp1.flags;
785 ret.count = be16_to_cpu(tmp1.count);
786 ret.cda = be32_to_cpu(tmp1.cda);
787 } else {
788 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0));
9f94f84c
DJS		 789 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) {
790 ret.cmd_code = CCW_CMD_TIC;
791 ret.flags = 0;
792 ret.count = 0;
793 } else {
794 ret.cmd_code = tmp0.cmd_code;
795 ret.flags = tmp0.flags;
796 ret.count = be16_to_cpu(tmp0.count);
fde8206b 797 }
9f94f84c 798 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16);
a327c921 799 }
df1fe5bb
CH		 800 return ret;
801}
57065a70
HP		 802/**
803 * If out of bounds marks the stream broken. If broken returns -EINVAL,
804 * otherwise the requested length (may be zero)
805 */
806static inline int cds_check_len(CcwDataStream *cds, int len)
807{
808 if (cds->at_byte + len > cds->count) {
809 cds->flags |= CDS_F_STREAM_BROKEN;
810 }
811 return cds->flags & CDS_F_STREAM_BROKEN ? -EINVAL : len;
812}
813
62a2554e
HP		 814static inline bool cds_ccw_addrs_ok(hwaddr addr, int len, bool ccw_fmt1)
815{
816 return (addr + len) < (ccw_fmt1 ? (1UL << 31) : (1UL << 24));
817}
818
57065a70
HP		 819static int ccw_dstream_rw_noflags(CcwDataStream *cds, void *buff, int len,
820 CcwDataStreamOp op)
821{
822 int ret;
823
824 ret = cds_check_len(cds, len);
825 if (ret <= 0) {
826 return ret;
827 }
62a2554e
HP		 828 if (!cds_ccw_addrs_ok(cds->cda, len, cds->flags & CDS_F_FMT)) {
829 return -EINVAL; /* channel program check */
830 }
57065a70
HP		 831 if (op == CDS_OP_A) {
832 goto incr;
833 }
85fa94e1
CH		 834 if (!cds->do_skip) {
835 ret = address_space_rw(&address_space_memory, cds->cda,
836 MEMTXATTRS_UNSPECIFIED, buff, len, op);
837 } else {
838 ret = MEMTX_OK;
839 }
57065a70
HP		 840 if (ret != MEMTX_OK) {
841 cds->flags |= CDS_F_STREAM_BROKEN;
842 return -EINVAL;
843 }
844incr:
845 cds->at_byte += len;
846 cds->cda += len;
847 return 0;
848}
849
93973f8f
HP		 850/* returns values between 1 and bsz, where bsz is a power of 2 */
851static inline uint16_t ida_continuous_left(hwaddr cda, uint64_t bsz)
852{
853 return bsz - (cda & (bsz - 1));
854}
855
856static inline uint64_t ccw_ida_block_size(uint8_t flags)
857{
858 if ((flags & CDS_F_C64) && !(flags & CDS_F_I2K)) {
859 return 1ULL << 12;
860 }
861 return 1ULL << 11;
862}
863
864static inline int ida_read_next_idaw(CcwDataStream *cds)
865{
866 union {uint64_t fmt2; uint32_t fmt1; } idaw;
867 int ret;
868 hwaddr idaw_addr;
869 bool idaw_fmt2 = cds->flags & CDS_F_C64;
870 bool ccw_fmt1 = cds->flags & CDS_F_FMT;
871
872 if (idaw_fmt2) {
873 idaw_addr = cds->cda_orig + sizeof(idaw.fmt2) * cds->at_idaw;
874 if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
875 return -EINVAL; /* channel program check */
876 }
19f70347
PM		 877 ret = address_space_read(&address_space_memory, idaw_addr,
878 MEMTXATTRS_UNSPECIFIED, &idaw.fmt2,
879 sizeof(idaw.fmt2));
93973f8f
HP		 880 cds->cda = be64_to_cpu(idaw.fmt2);
881 } else {
882 idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw;
883 if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
884 return -EINVAL; /* channel program check */
885 }
19f70347
PM		 886 ret = address_space_read(&address_space_memory, idaw_addr,
887 MEMTXATTRS_UNSPECIFIED, &idaw.fmt1,
888 sizeof(idaw.fmt1));
93973f8f
HP		 889 cds->cda = be64_to_cpu(idaw.fmt1);
890 if (cds->cda & 0x80000000) {
891 return -EINVAL; /* channel program check */
892 }
893 }
894 ++(cds->at_idaw);
895 if (ret != MEMTX_OK) {
896 /* assume inaccessible address */
897 return -EINVAL; /* channel program check */
898 }
899 return 0;
900}
901
902static int ccw_dstream_rw_ida(CcwDataStream *cds, void *buff, int len,
903 CcwDataStreamOp op)
904{
905 uint64_t bsz = ccw_ida_block_size(cds->flags);
906 int ret = 0;
907 uint16_t cont_left, iter_len;
908
909 ret = cds_check_len(cds, len);
910 if (ret <= 0) {
911 return ret;
912 }
913 if (!cds->at_idaw) {
914 /* read first idaw */
915 ret = ida_read_next_idaw(cds);
916 if (ret) {
917 goto err;
918 }
919 cont_left = ida_continuous_left(cds->cda, bsz);
920 } else {
921 cont_left = ida_continuous_left(cds->cda, bsz);
922 if (cont_left == bsz) {
923 ret = ida_read_next_idaw(cds);
924 if (ret) {
925 goto err;
926 }
927 if (cds->cda & (bsz - 1)) {
928 ret = -EINVAL; /* channel program check */
929 goto err;
930 }
931 }
932 }
933 do {
934 iter_len = MIN(len, cont_left);
935 if (op != CDS_OP_A) {
85fa94e1
CH		 936 if (!cds->do_skip) {
937 ret = address_space_rw(&address_space_memory, cds->cda,
938 MEMTXATTRS_UNSPECIFIED, buff, iter_len,
939 op);
940 } else {
941 ret = MEMTX_OK;
942 }
93973f8f
HP		 943 if (ret != MEMTX_OK) {
944 /* assume inaccessible address */
945 ret = -EINVAL; /* channel program check */
946 goto err;
947 }
948 }
949 cds->at_byte += iter_len;
950 cds->cda += iter_len;
951 len -= iter_len;
952 if (!len) {
953 break;
954 }
955 ret = ida_read_next_idaw(cds);
956 if (ret) {
957 goto err;
958 }
959 cont_left = bsz;
960 } while (true);
961 return ret;
962err:
963 cds->flags |= CDS_F_STREAM_BROKEN;
964 return ret;
965}
966
57065a70
HP		 967void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb)
968{
969 /*
970 * We don't support MIDA (an optional facility) yet and we
971 * catch this earlier. Just for expressing the precondition.
972 */
973 g_assert(!(orb->ctrl1 & ORB_CTRL1_MASK_MIDAW));
974 cds->flags = (orb->ctrl0 & ORB_CTRL0_MASK_I2K ? CDS_F_I2K : 0) |
975 (orb->ctrl0 & ORB_CTRL0_MASK_C64 ? CDS_F_C64 : 0) |
62a2554e 976 (orb->ctrl0 & ORB_CTRL0_MASK_FMT ? CDS_F_FMT : 0) |
57065a70 977 (ccw->flags & CCW_FLAG_IDA ? CDS_F_IDA : 0);
62a2554e 978
57065a70
HP		 979 cds->count = ccw->count;
980 cds->cda_orig = ccw->cda;
85fa94e1
CH		 981 /* skip is only effective for read, read backwards, or sense commands */
982 cds->do_skip = (ccw->flags & CCW_FLAG_SKIP) &&
983 ((ccw->cmd_code & 0x0f) == CCW_CMD_BASIC_SENSE ||
984 (ccw->cmd_code & 0x03) == 0x02 /* read */ ||
985 (ccw->cmd_code & 0x0f) == 0x0c /* read backwards */);
57065a70
HP		 986 ccw_dstream_rewind(cds);
987 if (!(cds->flags & CDS_F_IDA)) {
988 cds->op_handler = ccw_dstream_rw_noflags;
989 } else {
93973f8f 990 cds->op_handler = ccw_dstream_rw_ida;
57065a70
HP		 991 }
992}
df1fe5bb 993
ce350f32
CH		 994static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr,
995 bool suspend_allowed)
df1fe5bb
CH		 996{
997 int ret;
998 bool check_len;
999 int len;
1000 CCW1 ccw;
1001
1002 if (!ccw_addr) {
cc6a9f8d 1003 return -EINVAL; /* channel-program check */
df1fe5bb 1004 }
198c0d1f
HP		 1005 /* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */
1006 if (ccw_addr & (sch->ccw_fmt_1 ? 0x80000007 : 0xff000007)) {
1007 return -EINVAL;
1008 }
df1fe5bb 1009
a327c921
CH		 1010 /* Translate everything to format-1 ccws - the information is the same. */
1011 ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1);
df1fe5bb
CH		 1012
1013 /* Check for invalid command codes. */
1014 if ((ccw.cmd_code & 0x0f) == 0) {
1015 return -EINVAL;
1016 }
1017 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) &&
1018 ((ccw.cmd_code & 0xf0) != 0)) {
1019 return -EINVAL;
1020 }
fa4463e0
CH		 1021 if (!sch->ccw_fmt_1 && (ccw.count == 0) &&
1022 (ccw.cmd_code != CCW_CMD_TIC)) {
1023 return -EINVAL;
1024 }
df1fe5bb 1025
4e19b57b
CH		 1026 /* We don't support MIDA. */
1027 if (ccw.flags & CCW_FLAG_MIDA) {
1028 return -EINVAL;
1029 }
1030
df1fe5bb 1031 if (ccw.flags & CCW_FLAG_SUSPEND) {
ce350f32 1032 return suspend_allowed ? -EINPROGRESS : -EINVAL;
df1fe5bb
CH		 1033 }
1034
1035 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC));
1036
e8601dd5
CH		 1037 if (!ccw.cda) {
1038 if (sch->ccw_no_data_cnt == 255) {
1039 return -EINVAL;
1040 }
1041 sch->ccw_no_data_cnt++;
1042 }
1043
df1fe5bb 1044 /* Look at the command. */
0a22eac5 1045 ccw_dstream_init(&sch->cds, &ccw, &(sch->orb));
df1fe5bb
CH		 1046 switch (ccw.cmd_code) {
1047 case CCW_CMD_NOOP:
1048 /* Nothing to do. */
1049 ret = 0;
1050 break;
1051 case CCW_CMD_BASIC_SENSE:
1052 if (check_len) {
1053 if (ccw.count != sizeof(sch->sense_data)) {
1054 ret = -EINVAL;
1055 break;
1056 }
1057 }
1058 len = MIN(ccw.count, sizeof(sch->sense_data));
0a22eac5
HP		 1059 ccw_dstream_write_buf(&sch->cds, sch->sense_data, len);
1060 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds);
df1fe5bb
CH		 1061 memset(sch->sense_data, 0, sizeof(sch->sense_data));
1062 ret = 0;
1063 break;
1064 case CCW_CMD_SENSE_ID:
1065 {
729315eb
TH		 1066 /* According to SA22-7204-01, Sense-ID can store up to 256 bytes */
1067 uint8_t sense_id[256];
df1fe5bb 1068
729315eb 1069 copy_sense_id_to_guest(sense_id, &sch->id);
df1fe5bb
CH		 1070 /* Sense ID information is device specific. */
1071 if (check_len) {
1072 if (ccw.count != sizeof(sense_id)) {
1073 ret = -EINVAL;
1074 break;
1075 }
1076 }
1077 len = MIN(ccw.count, sizeof(sense_id));
1078 /*
1079 * Only indicate 0xff in the first sense byte if we actually
1080 * have enough place to store at least bytes 0-3.
1081 */
1082 if (len >= 4) {
729315eb 1083 sense_id[0] = 0xff;
df1fe5bb 1084 } else {
729315eb 1085 sense_id[0] = 0;
df1fe5bb 1086 }
729315eb 1087 ccw_dstream_write_buf(&sch->cds, sense_id, len);
0a22eac5 1088 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds);
df1fe5bb
CH		 1089 ret = 0;
1090 break;
1091 }
1092 case CCW_CMD_TIC:
1093 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) {
1094 ret = -EINVAL;
1095 break;
1096 }
4add0da6
HP		 1097 if (ccw.flags || ccw.count) {
1098 /* We have already sanitized these if converted from fmt 0. */
df1fe5bb
CH		 1099 ret = -EINVAL;
1100 break;
1101 }
1102 sch->channel_prog = ccw.cda;
1103 ret = -EAGAIN;
1104 break;
1105 default:
1106 if (sch->ccw_cb) {
1107 /* Handle device specific commands. */
1108 ret = sch->ccw_cb(sch, ccw);
1109 } else {
8d034a6f 1110 ret = -ENOSYS;
df1fe5bb
CH		 1111 }
1112 break;
1113 }
1114 sch->last_cmd = ccw;
1115 sch->last_cmd_valid = true;
1116 if (ret == 0) {
1117 if (ccw.flags & CCW_FLAG_CC) {
1118 sch->channel_prog += 8;
1119 ret = -EAGAIN;
1120 }
1121 }
1122
1123 return ret;
1124}
1125
b5f5a3af 1126static void sch_handle_start_func_virtual(SubchDev *sch)
df1fe5bb 1127{
bea0279b 1128 SCHIB *schib = &sch->curr_status;
df1fe5bb
CH		 1129 int path;
1130 int ret;
ce350f32 1131 bool suspend_allowed;
df1fe5bb
CH		 1132
1133 /* Path management: In our simple css, we always choose the only path. */
1134 path = 0x80;
1135
bea0279b 1136 if (!(schib->scsw.ctrl & SCSW_ACTL_SUSP)) {
727a0424 1137 /* Start Function triggered via ssch, i.e. we have an ORB */
b5f5a3af 1138 ORB *orb = &sch->orb;
bea0279b
DB		 1139 schib->scsw.cstat = 0;
1140 schib->scsw.dstat = 0;
df1fe5bb 1141 /* Look at the orb and try to execute the channel program. */
bea0279b 1142 schib->pmcw.intparm = orb->intparm;
df1fe5bb
CH		 1143 if (!(orb->lpm & path)) {
1144 /* Generate a deferred cc 3 condition. */
bea0279b
DB		 1145 schib->scsw.flags |= SCSW_FLAGS_MASK_CC;
1146 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
1147 schib->scsw.ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND);
df1fe5bb
CH		 1148 return;
1149 }
a327c921 1150 sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT);
bea0279b 1151 schib->scsw.flags |= (sch->ccw_fmt_1) ? SCSW_FLAGS_MASK_FMT : 0;
e8601dd5 1152 sch->ccw_no_data_cnt = 0;
ce350f32 1153 suspend_allowed = !!(orb->ctrl0 & ORB_CTRL0_MASK_SPND);
df1fe5bb 1154 } else {
b5f5a3af 1155 /* Start Function resumed via rsch */
bea0279b 1156 schib->scsw.ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND);
ce350f32
CH		 1157 /* The channel program had been suspended before. */
1158 suspend_allowed = true;
df1fe5bb
CH		 1159 }
1160 sch->last_cmd_valid = false;
1161 do {
ce350f32 1162 ret = css_interpret_ccw(sch, sch->channel_prog, suspend_allowed);
df1fe5bb
CH		 1163 switch (ret) {
1164 case -EAGAIN:
1165 /* ccw chain, continue processing */
1166 break;
1167 case 0:
1168 /* success */
bea0279b
DB		 1169 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND;
1170 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
1171 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
df1fe5bb 1172 SCSW_STCTL_STATUS_PEND;
bea0279b
DB		 1173 schib->scsw.dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END;
1174 schib->scsw.cpa = sch->channel_prog + 8;
df1fe5bb 1175 break;
2dc95b4c
JL		 1176 case -EIO:
1177 /* I/O errors, status depends on specific devices */
1178 break;
8d034a6f 1179 case -ENOSYS:
df1fe5bb 1180 /* unsupported command, generate unit check (command reject) */
bea0279b
DB		 1181 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND;
1182 schib->scsw.dstat = SCSW_DSTAT_UNIT_CHECK;
df1fe5bb
CH		 1183 /* Set sense bit 0 in ecw0. */
1184 sch->sense_data[0] = 0x80;
bea0279b
DB		 1185 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
1186 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
df1fe5bb 1187 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
bea0279b 1188 schib->scsw.cpa = sch->channel_prog + 8;
df1fe5bb 1189 break;
8d034a6f 1190 case -EINPROGRESS:
df1fe5bb 1191 /* channel program has been suspended */
bea0279b
DB		 1192 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND;
1193 schib->scsw.ctrl |= SCSW_ACTL_SUSP;
df1fe5bb
CH		 1194 break;
1195 default:
1196 /* error, generate channel program check */
bea0279b
DB		 1197 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND;
1198 schib->scsw.cstat = SCSW_CSTAT_PROG_CHECK;
1199 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
1200 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
df1fe5bb 1201 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
bea0279b 1202 schib->scsw.cpa = sch->channel_prog + 8;
df1fe5bb
CH		 1203 break;
1204 }
1205 } while (ret == -EAGAIN);
1206
1207}
1208
8fadea24
CH		 1209static void sch_handle_halt_func_passthrough(SubchDev *sch)
1210{
1211 int ret;
1212
1213 ret = s390_ccw_halt(sch);
1214 if (ret == -ENOSYS) {
1215 sch_handle_halt_func(sch);
1216 }
1217}
1218
1219static void sch_handle_clear_func_passthrough(SubchDev *sch)
1220{
1221 int ret;
1222
1223 ret = s390_ccw_clear(sch);
1224 if (ret == -ENOSYS) {
1225 sch_handle_clear_func(sch);
1226 }
1227}
1228
66dc50f7 1229static IOInstEnding sch_handle_start_func_passthrough(SubchDev *sch)
bab482d7 1230{
bea0279b 1231 SCHIB *schib = &sch->curr_status;
b5f5a3af 1232 ORB *orb = &sch->orb;
bea0279b 1233 if (!(schib->scsw.ctrl & SCSW_ACTL_SUSP)) {
bab482d7 1234 assert(orb != NULL);
bea0279b 1235 schib->pmcw.intparm = orb->intparm;
bab482d7 1236 }
66dc50f7 1237 return s390_ccw_cmd_request(sch);
bab482d7
XFR		 1238}
1239
df1fe5bb
CH		 1240/*
1241 * On real machines, this would run asynchronously to the main vcpus.
1242 * We might want to make some parts of the ssch handling (interpreting
1243 * read/writes) asynchronous later on if we start supporting more than
1244 * our current very simple devices.
1245 */
66dc50f7 1246IOInstEnding do_subchannel_work_virtual(SubchDev *sch)
df1fe5bb 1247{
bea0279b 1248 SCHIB *schib = &sch->curr_status;
df1fe5bb 1249
bea0279b 1250 if (schib->scsw.ctrl & SCSW_FCTL_CLEAR_FUNC) {
df1fe5bb 1251 sch_handle_clear_func(sch);
bea0279b 1252 } else if (schib->scsw.ctrl & SCSW_FCTL_HALT_FUNC) {
df1fe5bb 1253 sch_handle_halt_func(sch);
bea0279b 1254 } else if (schib->scsw.ctrl & SCSW_FCTL_START_FUNC) {
727a0424 1255 /* Triggered by both ssch and rsch. */
b5f5a3af 1256 sch_handle_start_func_virtual(sch);
df1fe5bb
CH		 1257 }
1258 css_inject_io_interrupt(sch);
66dc50f7
HP		 1259 /* inst must succeed if this func is called */
1260 return IOINST_CC_EXPECTED;
bab482d7
XFR		 1261}
1262
66dc50f7 1263IOInstEnding do_subchannel_work_passthrough(SubchDev *sch)
bab482d7 1264{
bea0279b 1265 SCHIB *schib = &sch->curr_status;
bab482d7 1266
bea0279b 1267 if (schib->scsw.ctrl & SCSW_FCTL_CLEAR_FUNC) {
8fadea24 1268 sch_handle_clear_func_passthrough(sch);
bea0279b 1269 } else if (schib->scsw.ctrl & SCSW_FCTL_HALT_FUNC) {
8fadea24 1270 sch_handle_halt_func_passthrough(sch);
bea0279b 1271 } else if (schib->scsw.ctrl & SCSW_FCTL_START_FUNC) {
66dc50f7 1272 return sch_handle_start_func_passthrough(sch);
bab482d7 1273 }
66dc50f7 1274 return IOINST_CC_EXPECTED;
bab482d7
XFR		 1275}
1276
66dc50f7 1277static IOInstEnding do_subchannel_work(SubchDev *sch)
bab482d7 1278{
9ea63c05 1279 if (!sch->do_subchannel_work) {
66dc50f7 1280 return IOINST_CC_STATUS_PRESENT;
bab482d7 1281 }
9ea63c05
HP		 1282 g_assert(sch->curr_status.scsw.ctrl & SCSW_CTRL_MASK_FCTL);
1283 return sch->do_subchannel_work(sch);
df1fe5bb
CH		 1284}
1285
1286static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src)
1287{
1288 int i;
1289
1290 dest->intparm = cpu_to_be32(src->intparm);
1291 dest->flags = cpu_to_be16(src->flags);
1292 dest->devno = cpu_to_be16(src->devno);
1293 dest->lpm = src->lpm;
1294 dest->pnom = src->pnom;
1295 dest->lpum = src->lpum;
1296 dest->pim = src->pim;
1297 dest->mbi = cpu_to_be16(src->mbi);
1298 dest->pom = src->pom;
1299 dest->pam = src->pam;
1300 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) {
1301 dest->chpid[i] = src->chpid[i];
1302 }
1303 dest->chars = cpu_to_be32(src->chars);
1304}
1305
8ca2b376 1306void copy_scsw_to_guest(SCSW *dest, const SCSW *src)
df1fe5bb
CH		 1307{
1308 dest->flags = cpu_to_be16(src->flags);
1309 dest->ctrl = cpu_to_be16(src->ctrl);
1310 dest->cpa = cpu_to_be32(src->cpa);
1311 dest->dstat = src->dstat;
1312 dest->cstat = src->cstat;
1313 dest->count = cpu_to_be16(src->count);
1314}
1315
1316static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src)
1317{
1318 int i;
55281a2c
PM		 1319 /*
1320 * We copy the PMCW and SCSW in and out of local variables to
1321 * avoid taking the address of members of a packed struct.
1322 */
1323 PMCW src_pmcw, dest_pmcw;
1324 SCSW src_scsw, dest_scsw;
1325
1326 src_pmcw = src->pmcw;
1327 copy_pmcw_to_guest(&dest_pmcw, &src_pmcw);
1328 dest->pmcw = dest_pmcw;
1329 src_scsw = src->scsw;
1330 copy_scsw_to_guest(&dest_scsw, &src_scsw);
1331 dest->scsw = dest_scsw;
df1fe5bb
CH		 1332 dest->mba = cpu_to_be64(src->mba);
1333 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) {
1334 dest->mda[i] = src->mda[i];
1335 }
1336}
1337
46ea3841 1338IOInstEnding css_do_stsch(SubchDev *sch, SCHIB *schib)
df1fe5bb 1339{
46ea3841
FA		 1340 int ret;
1341
1342 /*
1343 * For some subchannels, we may want to update parts of
1344 * the schib (e.g., update path masks from the host device
1345 * for passthrough subchannels).
1346 */
1347 ret = s390_ccw_store(sch);
1348
df1fe5bb
CH		 1349 /* Use current status. */
1350 copy_schib_to_guest(schib, &sch->curr_status);
46ea3841 1351 return ret;
df1fe5bb
CH		 1352}
1353
1354static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src)
1355{
1356 int i;
1357
1358 dest->intparm = be32_to_cpu(src->intparm);
1359 dest->flags = be16_to_cpu(src->flags);
1360 dest->devno = be16_to_cpu(src->devno);
1361 dest->lpm = src->lpm;
1362 dest->pnom = src->pnom;
1363 dest->lpum = src->lpum;
1364 dest->pim = src->pim;
1365 dest->mbi = be16_to_cpu(src->mbi);
1366 dest->pom = src->pom;
1367 dest->pam = src->pam;
1368 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) {
1369 dest->chpid[i] = src->chpid[i];
1370 }
1371 dest->chars = be32_to_cpu(src->chars);
1372}
1373
1374static void copy_scsw_from_guest(SCSW *dest, const SCSW *src)
1375{
1376 dest->flags = be16_to_cpu(src->flags);
1377 dest->ctrl = be16_to_cpu(src->ctrl);
1378 dest->cpa = be32_to_cpu(src->cpa);
1379 dest->dstat = src->dstat;
1380 dest->cstat = src->cstat;
1381 dest->count = be16_to_cpu(src->count);
1382}
1383
1384static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src)
1385{
1386 int i;
55281a2c
PM		 1387 /*
1388 * We copy the PMCW and SCSW in and out of local variables to
1389 * avoid taking the address of members of a packed struct.
1390 */
1391 PMCW src_pmcw, dest_pmcw;
1392 SCSW src_scsw, dest_scsw;
1393
1394 src_pmcw = src->pmcw;
1395 copy_pmcw_from_guest(&dest_pmcw, &src_pmcw);
1396 dest->pmcw = dest_pmcw;
1397 src_scsw = src->scsw;
1398 copy_scsw_from_guest(&dest_scsw, &src_scsw);
1399 dest->scsw = dest_scsw;
df1fe5bb
CH		 1400 dest->mba = be64_to_cpu(src->mba);
1401 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) {
1402 dest->mda[i] = src->mda[i];
1403 }
1404}
1405
6bb6f194 1406IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *orig_schib)
df1fe5bb 1407{
bea0279b 1408 SCHIB *schib = &sch->curr_status;
62ac4a52 1409 uint16_t oldflags;
bea0279b 1410 SCHIB schib_copy;
df1fe5bb 1411
bea0279b 1412 if (!(schib->pmcw.flags & PMCW_FLAGS_MASK_DNV)) {
6bb6f194 1413 return IOINST_CC_EXPECTED;
df1fe5bb
CH		 1414 }
1415
bea0279b 1416 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) {
6bb6f194 1417 return IOINST_CC_STATUS_PRESENT;
df1fe5bb
CH		 1418 }
1419
bea0279b 1420 if (schib->scsw.ctrl &
df1fe5bb 1421 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) {
6bb6f194 1422 return IOINST_CC_BUSY;
df1fe5bb
CH		 1423 }
1424
bea0279b 1425 copy_schib_from_guest(&schib_copy, orig_schib);
df1fe5bb 1426 /* Only update the program-modifiable fields. */
bea0279b
DB		 1427 schib->pmcw.intparm = schib_copy.pmcw.intparm;
1428 oldflags = schib->pmcw.flags;
1429 schib->pmcw.flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
df1fe5bb
CH		 1430 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
1431 PMCW_FLAGS_MASK_MP);
bea0279b 1432 schib->pmcw.flags |= schib_copy.pmcw.flags &
df1fe5bb
CH		 1433 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
1434 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
1435 PMCW_FLAGS_MASK_MP);
bea0279b
DB		 1436 schib->pmcw.lpm = schib_copy.pmcw.lpm;
1437 schib->pmcw.mbi = schib_copy.pmcw.mbi;
1438 schib->pmcw.pom = schib_copy.pmcw.pom;
1439 schib->pmcw.chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
1440 schib->pmcw.chars |= schib_copy.pmcw.chars &
df1fe5bb 1441 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
bea0279b 1442 schib->mba = schib_copy.mba;
df1fe5bb 1443
62ac4a52
TH		 1444 /* Has the channel been disabled? */
1445 if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0
bea0279b 1446 && (schib->pmcw.flags & PMCW_FLAGS_MASK_ENA) == 0) {
62ac4a52
TH		 1447 sch->disable_cb(sch);
1448 }
6bb6f194 1449 return IOINST_CC_EXPECTED;
df1fe5bb
CH		 1450}
1451
96376408 1452IOInstEnding css_do_xsch(SubchDev *sch)
df1fe5bb 1453{
bea0279b 1454 SCHIB *schib = &sch->curr_status;
df1fe5bb 1455
bea0279b 1456 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
96376408 1457 return IOINST_CC_NOT_OPERATIONAL;
df1fe5bb
CH		 1458 }
1459
bea0279b 1460 if (schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) {
96376408 1461 return IOINST_CC_STATUS_PRESENT;
6c864622
HP		 1462 }
1463
bea0279b
DB		 1464 if (!(schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) ||
1465 ((schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) ||
1466 (!(schib->scsw.ctrl &
df1fe5bb 1467 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) ||
bea0279b 1468 (schib->scsw.ctrl & SCSW_ACTL_SUBCH_ACTIVE)) {
96376408 1469 return IOINST_CC_BUSY;
df1fe5bb
CH		 1470 }
1471
1472 /* Cancel the current operation. */
bea0279b 1473 schib->scsw.ctrl &= ~(SCSW_FCTL_START_FUNC |
df1fe5bb
CH		 1474 SCSW_ACTL_RESUME_PEND |
1475 SCSW_ACTL_START_PEND |
1476 SCSW_ACTL_SUSP);
1477 sch->channel_prog = 0x0;
1478 sch->last_cmd_valid = false;
bea0279b
DB		 1479 schib->scsw.dstat = 0;
1480 schib->scsw.cstat = 0;
96376408 1481 return IOINST_CC_EXPECTED;
df1fe5bb
CH		 1482}
1483
77331442 1484IOInstEnding css_do_csch(SubchDev *sch)
df1fe5bb 1485{
bea0279b 1486 SCHIB *schib = &sch->curr_status;
df1fe5bb 1487
bea0279b 1488 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
77331442 1489 return IOINST_CC_NOT_OPERATIONAL;
df1fe5bb
CH		 1490 }
1491
1492 /* Trigger the clear function. */
bea0279b
DB		 1493 schib->scsw.ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL);
1494 schib->scsw.ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND;
df1fe5bb 1495
77331442 1496 return do_subchannel_work(sch);
df1fe5bb
CH		 1497}
1498
ae9f1be3 1499IOInstEnding css_do_hsch(SubchDev *sch)
df1fe5bb 1500{
bea0279b 1501 SCHIB *schib = &sch->curr_status;
df1fe5bb 1502
bea0279b 1503 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
ae9f1be3 1504 return IOINST_CC_NOT_OPERATIONAL;
df1fe5bb
CH		 1505 }
1506
bea0279b
DB		 1507 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) ||
1508 (schib->scsw.ctrl & (SCSW_STCTL_PRIMARY |
df1fe5bb
CH		 1509 SCSW_STCTL_SECONDARY |
1510 SCSW_STCTL_ALERT))) {
ae9f1be3 1511 return IOINST_CC_STATUS_PRESENT;
df1fe5bb
CH		 1512 }
1513
bea0279b 1514 if (schib->scsw.ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) {
ae9f1be3 1515 return IOINST_CC_BUSY;
df1fe5bb
CH		 1516 }
1517
1518 /* Trigger the halt function. */
bea0279b
DB		 1519 schib->scsw.ctrl |= SCSW_FCTL_HALT_FUNC;
1520 schib->scsw.ctrl &= ~SCSW_FCTL_START_FUNC;
1521 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_ACTL) ==
df1fe5bb 1522 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) &&
bea0279b
DB		 1523 ((schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) ==
1524 SCSW_STCTL_INTERMEDIATE)) {
1525 schib->scsw.ctrl &= ~SCSW_STCTL_STATUS_PEND;
df1fe5bb 1526 }
bea0279b 1527 schib->scsw.ctrl |= SCSW_ACTL_HALT_PEND;
df1fe5bb 1528
ae9f1be3 1529 return do_subchannel_work(sch);
df1fe5bb
CH		 1530}
1531
1532static void css_update_chnmon(SubchDev *sch)
1533{
1534 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) {
1535 /* Not active. */
1536 return;
1537 }
1538 /* The counter is conveniently located at the beginning of the struct. */
1539 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) {
1540 /* Format 1, per-subchannel area. */
1541 uint32_t count;
1542
42874d3a
PM		 1543 count = address_space_ldl(&address_space_memory,
1544 sch->curr_status.mba,
1545 MEMTXATTRS_UNSPECIFIED,
1546 NULL);
df1fe5bb 1547 count++;
42874d3a
PM		 1548 address_space_stl(&address_space_memory, sch->curr_status.mba, count,
1549 MEMTXATTRS_UNSPECIFIED, NULL);
df1fe5bb
CH		 1550 } else {
1551 /* Format 0, global area. */
1552 uint32_t offset;
1553 uint16_t count;
1554
1555 offset = sch->curr_status.pmcw.mbi << 5;
42874d3a 1556 count = address_space_lduw(&address_space_memory,
562f5e0b 1557 channel_subsys.chnmon_area + offset,
42874d3a
PM		 1558 MEMTXATTRS_UNSPECIFIED,
1559 NULL);
df1fe5bb 1560 count++;
42874d3a 1561 address_space_stw(&address_space_memory,
562f5e0b 1562 channel_subsys.chnmon_area + offset, count,
42874d3a 1563 MEMTXATTRS_UNSPECIFIED, NULL);
df1fe5bb
CH		 1564 }
1565}
1566
66dc50f7 1567IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb)
df1fe5bb 1568{
bea0279b 1569 SCHIB *schib = &sch->curr_status;
df1fe5bb 1570
bea0279b 1571 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
66dc50f7 1572 return IOINST_CC_NOT_OPERATIONAL;
df1fe5bb
CH		 1573 }
1574
bea0279b 1575 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) {
66dc50f7 1576 return IOINST_CC_STATUS_PRESENT;
df1fe5bb
CH		 1577 }
1578
bea0279b 1579 if (schib->scsw.ctrl & (SCSW_FCTL_START_FUNC |
df1fe5bb
CH		 1580 SCSW_FCTL_HALT_FUNC |
1581 SCSW_FCTL_CLEAR_FUNC)) {
66dc50f7 1582 return IOINST_CC_BUSY;
df1fe5bb
CH		 1583 }
1584
1585 /* If monitoring is active, update counter. */
562f5e0b 1586 if (channel_subsys.chnmon_active) {
df1fe5bb
CH		 1587 css_update_chnmon(sch);
1588 }
ff443fe6 1589 sch->orb = *orb;
df1fe5bb
CH		 1590 sch->channel_prog = orb->cpa;
1591 /* Trigger the start function. */
bea0279b
DB		 1592 schib->scsw.ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND);
1593 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO;
df1fe5bb 1594
66dc50f7 1595 return do_subchannel_work(sch);
df1fe5bb
CH		 1596}
1597
bea0279b 1598static void copy_irb_to_guest(IRB *dest, const IRB *src, const PMCW *pmcw,
b7b6348a 1599 int *irb_len)
df1fe5bb
CH		 1600{
1601 int i;
f068d320
CH		 1602 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
1603 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL;
df1fe5bb
CH		 1604
1605 copy_scsw_to_guest(&dest->scsw, &src->scsw);
1606
1607 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) {
1608 dest->esw[i] = cpu_to_be32(src->esw[i]);
1609 }
1610 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) {
1611 dest->ecw[i] = cpu_to_be32(src->ecw[i]);
1612 }
b7b6348a
TH		 1613 *irb_len = sizeof(*dest) - sizeof(dest->emw);
1614
f068d320
CH		 1615 /* extended measurements enabled? */
1616 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) ||
1617 !(pmcw->flags & PMCW_FLAGS_MASK_TF) ||
1618 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) {
1619 return;
1620 }
1621 /* extended measurements pending? */
1622 if (!(stctl & SCSW_STCTL_STATUS_PEND)) {
1623 return;
1624 }
1625 if ((stctl & SCSW_STCTL_PRIMARY) ||
1626 (stctl == SCSW_STCTL_SECONDARY) ||
1627 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) {
1628 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) {
1629 dest->emw[i] = cpu_to_be32(src->emw[i]);
1630 }
df1fe5bb 1631 }
b7b6348a 1632 *irb_len = sizeof(*dest);
df1fe5bb
CH		 1633}
1634
b7b6348a 1635int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len)
df1fe5bb 1636{
bea0279b
DB		 1637 SCHIB *schib = &sch->curr_status;
1638 PMCW p;
df1fe5bb 1639 uint16_t stctl;
df1fe5bb 1640 IRB irb;
df1fe5bb 1641
bea0279b 1642 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
b7b6348a 1643 return 3;
df1fe5bb
CH		 1644 }
1645
bea0279b 1646 stctl = schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
df1fe5bb
CH		 1647
1648 /* Prepare the irb for the guest. */
1649 memset(&irb, 0, sizeof(IRB));
1650
1651 /* Copy scsw from current status. */
bea0279b 1652 irb.scsw = schib->scsw;
df1fe5bb 1653 if (stctl & SCSW_STCTL_STATUS_PEND) {
bea0279b 1654 if (schib->scsw.cstat & (SCSW_CSTAT_DATA_CHECK |
df1fe5bb
CH		 1655 SCSW_CSTAT_CHN_CTRL_CHK |
1656 SCSW_CSTAT_INTF_CTRL_CHK)) {
1657 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF;
1658 irb.esw[0] = 0x04804000;
1659 } else {
1660 irb.esw[0] = 0x00800000;
1661 }
1662 /* If a unit check is pending, copy sense data. */
bea0279b
DB		 1663 if ((schib->scsw.dstat & SCSW_DSTAT_UNIT_CHECK) &&
1664 (schib->pmcw.chars & PMCW_CHARS_MASK_CSENSE)) {
b498484e
CH		 1665 int i;
1666
df1fe5bb 1667 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL;
b498484e 1668 /* Attention: sense_data is already BE! */
df1fe5bb 1669 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data));
b498484e
CH		 1670 for (i = 0; i < ARRAY_SIZE(irb.ecw); i++) {
1671 irb.ecw[i] = be32_to_cpu(irb.ecw[i]);
1672 }
8312976e 1673 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8);
df1fe5bb
CH		 1674 }
1675 }
1676 /* Store the irb to the guest. */
bea0279b
DB		 1677 p = schib->pmcw;
1678 copy_irb_to_guest(target_irb, &irb, &p, irb_len);
b7b6348a
TH		 1679
1680 return ((stctl & SCSW_STCTL_STATUS_PEND) == 0);
1681}
1682
1683void css_do_tsch_update_subch(SubchDev *sch)
1684{
bea0279b 1685 SCHIB *schib = &sch->curr_status;
b7b6348a
TH		 1686 uint16_t stctl;
1687 uint16_t fctl;
1688 uint16_t actl;
1689
bea0279b
DB		 1690 stctl = schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
1691 fctl = schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL;
1692 actl = schib->scsw.ctrl & SCSW_CTRL_MASK_ACTL;
df1fe5bb
CH		 1693
1694 /* Clear conditions on subchannel, if applicable. */
1695 if (stctl & SCSW_STCTL_STATUS_PEND) {
bea0279b 1696 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
df1fe5bb
CH		 1697 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) ||
1698 ((fctl & SCSW_FCTL_HALT_FUNC) &&
1699 (actl & SCSW_ACTL_SUSP))) {
bea0279b 1700 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_FCTL;
df1fe5bb
CH		 1701 }
1702 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) {
bea0279b
DB		 1703 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO;
1704 schib->scsw.ctrl &= ~(SCSW_ACTL_RESUME_PEND |
df1fe5bb
CH		 1705 SCSW_ACTL_START_PEND |
1706 SCSW_ACTL_HALT_PEND |
1707 SCSW_ACTL_CLEAR_PEND |
1708 SCSW_ACTL_SUSP);
1709 } else {
1710 if ((actl & SCSW_ACTL_SUSP) &&
1711 (fctl & SCSW_FCTL_START_FUNC)) {
bea0279b 1712 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO;
df1fe5bb 1713 if (fctl & SCSW_FCTL_HALT_FUNC) {
bea0279b 1714 schib->scsw.ctrl &= ~(SCSW_ACTL_RESUME_PEND |
df1fe5bb
CH		 1715 SCSW_ACTL_START_PEND |
1716 SCSW_ACTL_HALT_PEND |
1717 SCSW_ACTL_CLEAR_PEND |
1718 SCSW_ACTL_SUSP);
1719 } else {
bea0279b 1720 schib->scsw.ctrl &= ~SCSW_ACTL_RESUME_PEND;
df1fe5bb
CH		 1721 }
1722 }
1723 }
1724 /* Clear pending sense data. */
bea0279b 1725 if (schib->pmcw.chars & PMCW_CHARS_MASK_CSENSE) {
df1fe5bb
CH		 1726 memset(sch->sense_data, 0 , sizeof(sch->sense_data));
1727 }
1728 }
df1fe5bb
CH		 1729}
1730
1731static void copy_crw_to_guest(CRW *dest, const CRW *src)
1732{
1733 dest->flags = cpu_to_be16(src->flags);
1734 dest->rsid = cpu_to_be16(src->rsid);
1735}
1736
1737int css_do_stcrw(CRW *crw)
1738{
1739 CrwContainer *crw_cont;
1740 int ret;
1741
562f5e0b 1742 crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws);
df1fe5bb 1743 if (crw_cont) {
562f5e0b 1744 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb
CH		 1745 copy_crw_to_guest(crw, &crw_cont->crw);
1746 g_free(crw_cont);
1747 ret = 0;
1748 } else {
1749 /* List was empty, turn crw machine checks on again. */
1750 memset(crw, 0, sizeof(*crw));
562f5e0b 1751 channel_subsys.do_crw_mchk = true;
df1fe5bb
CH		 1752 ret = 1;
1753 }
1754
1755 return ret;
1756}
1757
7f74f0aa
TH		 1758static void copy_crw_from_guest(CRW *dest, const CRW *src)
1759{
1760 dest->flags = be16_to_cpu(src->flags);
1761 dest->rsid = be16_to_cpu(src->rsid);
1762}
1763
1764void css_undo_stcrw(CRW *crw)
1765{
1766 CrwContainer *crw_cont;
1767
96f64aa8 1768 crw_cont = g_try_new0(CrwContainer, 1);
7f74f0aa 1769 if (!crw_cont) {
562f5e0b 1770 channel_subsys.crws_lost = true;
7f74f0aa
TH		 1771 return;
1772 }
1773 copy_crw_from_guest(&crw_cont->crw, crw);
1774
562f5e0b 1775 QTAILQ_INSERT_HEAD(&channel_subsys.pending_crws, crw_cont, sibling);
7f74f0aa
TH		 1776}
1777
df1fe5bb
CH		 1778int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
1779 int rfmt, void *buf)
1780{
1781 int i, desc_size;
1782 uint32_t words[8];
1783 uint32_t chpid_type_word;
1784 CssImage *css;
1785
1786 if (!m && !cssid) {
562f5e0b 1787 css = channel_subsys.css[channel_subsys.default_cssid];
df1fe5bb 1788 } else {
562f5e0b 1789 css = channel_subsys.css[cssid];
df1fe5bb
CH		 1790 }
1791 if (!css) {
1792 return 0;
1793 }
1794 desc_size = 0;
1795 for (i = f_chpid; i <= l_chpid; i++) {
1796 if (css->chpids[i].in_use) {
1797 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i;
1798 if (rfmt == 0) {
1799 words[0] = cpu_to_be32(chpid_type_word);
1800 words[1] = 0;
1801 memcpy(buf + desc_size, words, 8);
1802 desc_size += 8;
1803 } else if (rfmt == 1) {
1804 words[0] = cpu_to_be32(chpid_type_word);
1805 words[1] = 0;
1806 words[2] = 0;
1807 words[3] = 0;
1808 words[4] = 0;
1809 words[5] = 0;
1810 words[6] = 0;
1811 words[7] = 0;
1812 memcpy(buf + desc_size, words, 32);
1813 desc_size += 32;
1814 }
1815 }
1816 }
1817 return desc_size;
1818}
1819
1820void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
1821{
1822 /* dct is currently ignored (not really meaningful for our devices) */
1823 /* TODO: Don't ignore mbk. */
562f5e0b 1824 if (update && !channel_subsys.chnmon_active) {
df1fe5bb 1825 /* Enable measuring. */
562f5e0b
EH		 1826 channel_subsys.chnmon_area = mbo;
1827 channel_subsys.chnmon_active = true;
df1fe5bb 1828 }
562f5e0b 1829 if (!update && channel_subsys.chnmon_active) {
df1fe5bb 1830 /* Disable measuring. */
562f5e0b
EH		 1831 channel_subsys.chnmon_area = 0;
1832 channel_subsys.chnmon_active = false;
df1fe5bb
CH		 1833 }
1834}
1835
66dc50f7 1836IOInstEnding css_do_rsch(SubchDev *sch)
df1fe5bb 1837{
bea0279b 1838 SCHIB *schib = &sch->curr_status;
df1fe5bb 1839
bea0279b 1840 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
66dc50f7 1841 return IOINST_CC_NOT_OPERATIONAL;
df1fe5bb
CH		 1842 }
1843
bea0279b 1844 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) {
66dc50f7 1845 return IOINST_CC_STATUS_PRESENT;
df1fe5bb
CH		 1846 }
1847
bea0279b
DB		 1848 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) ||
1849 (schib->scsw.ctrl & SCSW_ACTL_RESUME_PEND) ||
1850 (!(schib->scsw.ctrl & SCSW_ACTL_SUSP))) {
66dc50f7 1851 return IOINST_CC_BUSY;
df1fe5bb
CH		 1852 }
1853
1854 /* If monitoring is active, update counter. */
562f5e0b 1855 if (channel_subsys.chnmon_active) {
df1fe5bb
CH		 1856 css_update_chnmon(sch);
1857 }
1858
bea0279b 1859 schib->scsw.ctrl |= SCSW_ACTL_RESUME_PEND;
66dc50f7 1860 return do_subchannel_work(sch);
df1fe5bb
CH		 1861}
1862
1863int css_do_rchp(uint8_t cssid, uint8_t chpid)
1864{
1865 uint8_t real_cssid;
1866
562f5e0b 1867 if (cssid > channel_subsys.max_cssid) {
df1fe5bb
CH		 1868 return -EINVAL;
1869 }
562f5e0b
EH		 1870 if (channel_subsys.max_cssid == 0) {
1871 real_cssid = channel_subsys.default_cssid;
df1fe5bb
CH		 1872 } else {
1873 real_cssid = cssid;
1874 }
562f5e0b 1875 if (!channel_subsys.css[real_cssid]) {
df1fe5bb
CH		 1876 return -EINVAL;
1877 }
1878
562f5e0b 1879 if (!channel_subsys.css[real_cssid]->chpids[chpid].in_use) {
df1fe5bb
CH		 1880 return -ENODEV;
1881 }
1882
562f5e0b 1883 if (!channel_subsys.css[real_cssid]->chpids[chpid].is_virtual) {
df1fe5bb
CH		 1884 fprintf(stderr,
1885 "rchp unsupported for non-virtual chpid %x.%02x!\n",
1886 real_cssid, chpid);
1887 return -ENODEV;
1888 }
1889
1890 /* We don't really use a channel path, so we're done here. */
5c8d6f00 1891 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1,
562f5e0b
EH		 1892 channel_subsys.max_cssid > 0 ? 1 : 0, chpid);
1893 if (channel_subsys.max_cssid > 0) {
5c8d6f00 1894 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 0, real_cssid << 8);
df1fe5bb
CH		 1895 }
1896 return 0;
1897}
1898
38dd7cc7 1899bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid)
df1fe5bb
CH		 1900{
1901 SubchSet *set;
38dd7cc7 1902 uint8_t real_cssid;
df1fe5bb 1903
562f5e0b 1904 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid;
882b3b97 1905 if (ssid > MAX_SSID ||
562f5e0b
EH		 1906 !channel_subsys.css[real_cssid] ||
1907 !channel_subsys.css[real_cssid]->sch_set[ssid]) {
df1fe5bb
CH		 1908 return true;
1909 }
562f5e0b 1910 set = channel_subsys.css[real_cssid]->sch_set[ssid];
df1fe5bb
CH		 1911 return schid > find_last_bit(set->schids_used,
1912 (MAX_SCHID + 1) / sizeof(unsigned long));
1913}
1914
6c15e9bf
JL		 1915unsigned int css_find_free_chpid(uint8_t cssid)
1916{
1917 CssImage *css = channel_subsys.css[cssid];
1918 unsigned int chpid;
1919
1920 if (!css) {
1921 return MAX_CHPID + 1;
1922 }
1923
1924 for (chpid = 0; chpid <= MAX_CHPID; chpid++) {
1925 /* skip reserved chpid */
1926 if (chpid == VIRTIO_CCW_CHPID) {
1927 continue;
1928 }
1929 if (!css->chpids[chpid].in_use) {
1930 return chpid;
1931 }
1932 }
1933 return MAX_CHPID + 1;
1934}
1935
8f3cf012
XFR		 1936static int css_add_chpid(uint8_t cssid, uint8_t chpid, uint8_t type,
1937 bool is_virt)
df1fe5bb
CH		 1938{
1939 CssImage *css;
1940
1941 trace_css_chpid_add(cssid, chpid, type);
562f5e0b 1942 css = channel_subsys.css[cssid];
df1fe5bb
CH		 1943 if (!css) {
1944 return -EINVAL;
1945 }
1946 if (css->chpids[chpid].in_use) {
1947 return -EEXIST;
1948 }
1949 css->chpids[chpid].in_use = 1;
1950 css->chpids[chpid].type = type;
8f3cf012 1951 css->chpids[chpid].is_virtual = is_virt;
df1fe5bb
CH		 1952
1953 css_generate_chp_crws(cssid, chpid);
1954
1955 return 0;
1956}
1957
1958void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type)
1959{
bea0279b 1960 SCHIB *schib = &sch->curr_status;
df1fe5bb 1961 int i;
562f5e0b 1962 CssImage *css = channel_subsys.css[sch->cssid];
df1fe5bb
CH		 1963
1964 assert(css != NULL);
bea0279b
DB		 1965 memset(&schib->pmcw, 0, sizeof(PMCW));
1966 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV;
1967 schib->pmcw.devno = sch->devno;
df1fe5bb 1968 /* single path */
bea0279b
DB		 1969 schib->pmcw.pim = 0x80;
1970 schib->pmcw.pom = 0xff;
1971 schib->pmcw.pam = 0x80;
1972 schib->pmcw.chpid[0] = chpid;
df1fe5bb 1973 if (!css->chpids[chpid].in_use) {
8f3cf012 1974 css_add_chpid(sch->cssid, chpid, type, true);
df1fe5bb
CH		 1975 }
1976
bea0279b
DB		 1977 memset(&schib->scsw, 0, sizeof(SCSW));
1978 schib->mba = 0;
1979 for (i = 0; i < ARRAY_SIZE(schib->mda); i++) {
1980 schib->mda[i] = 0;
df1fe5bb
CH		 1981 }
1982}
1983
1984SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid)
1985{
1986 uint8_t real_cssid;
1987
562f5e0b 1988 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid;
df1fe5bb 1989
562f5e0b 1990 if (!channel_subsys.css[real_cssid]) {
df1fe5bb
CH		 1991 return NULL;
1992 }
1993
562f5e0b 1994 if (!channel_subsys.css[real_cssid]->sch_set[ssid]) {
df1fe5bb
CH		 1995 return NULL;
1996 }
1997
562f5e0b 1998 return channel_subsys.css[real_cssid]->sch_set[ssid]->sch[schid];
df1fe5bb
CH		 1999}
2000
cf249935
SS		 2001/**
2002 * Return free device number in subchannel set.
2003 *
2004 * Return index of the first free device number in the subchannel set
2005 * identified by @p cssid and @p ssid, beginning the search at @p
2006 * start and wrapping around at MAX_DEVNO. Return a value exceeding
2007 * MAX_SCHID if there are no free device numbers in the subchannel
2008 * set.
2009 */
2010static uint32_t css_find_free_devno(uint8_t cssid, uint8_t ssid,
2011 uint16_t start)
2012{
2013 uint32_t round;
2014
2015 for (round = 0; round <= MAX_DEVNO; round++) {
2016 uint16_t devno = (start + round) % MAX_DEVNO;
2017
2018 if (!css_devno_used(cssid, ssid, devno)) {
2019 return devno;
2020 }
2021 }
2022 return MAX_DEVNO + 1;
2023}
2024
2025/**
2026 * Return first free subchannel (id) in subchannel set.
2027 *
2028 * Return index of the first free subchannel in the subchannel set
2029 * identified by @p cssid and @p ssid, if there is any. Return a value
2030 * exceeding MAX_SCHID if there are no free subchannels in the
2031 * subchannel set.
2032 */
2033static uint32_t css_find_free_subch(uint8_t cssid, uint8_t ssid)
2034{
2035 uint32_t schid;
2036
2037 for (schid = 0; schid <= MAX_SCHID; schid++) {
2038 if (!css_find_subch(1, cssid, ssid, schid)) {
2039 return schid;
2040 }
2041 }
2042 return MAX_SCHID + 1;
2043}
2044
2045/**
2046 * Return first free subchannel (id) in subchannel set for a device number
2047 *
2048 * Verify the device number @p devno is not used yet in the subchannel
2049 * set identified by @p cssid and @p ssid. Set @p schid to the index
2050 * of the first free subchannel in the subchannel set, if there is
2051 * any. Return true if everything succeeded and false otherwise.
2052 */
2053static bool css_find_free_subch_for_devno(uint8_t cssid, uint8_t ssid,
2054 uint16_t devno, uint16_t *schid,
2055 Error **errp)
2056{
2057 uint32_t free_schid;
2058
2059 assert(schid);
2060 if (css_devno_used(cssid, ssid, devno)) {
2061 error_setg(errp, "Device %x.%x.%04x already exists",
2062 cssid, ssid, devno);
2063 return false;
2064 }
2065 free_schid = css_find_free_subch(cssid, ssid);
2066 if (free_schid > MAX_SCHID) {
2067 error_setg(errp, "No free subchannel found for %x.%x.%04x",
2068 cssid, ssid, devno);
2069 return false;
2070 }
2071 *schid = free_schid;
2072 return true;
2073}
2074
2075/**
2076 * Return first free subchannel (id) and device number
2077 *
2078 * Locate the first free subchannel and first free device number in
2079 * any of the subchannel sets of the channel subsystem identified by
2080 * @p cssid. Return false if no free subchannel / device number could
2081 * be found. Otherwise set @p ssid, @p devno and @p schid to identify
2082 * the available subchannel and device number and return true.
2083 *
2084 * May modify @p ssid, @p devno and / or @p schid even if no free
2085 * subchannel / device number could be found.
2086 */
2087static bool css_find_free_subch_and_devno(uint8_t cssid, uint8_t *ssid,
2088 uint16_t *devno, uint16_t *schid,
2089 Error **errp)
2090{
2091 uint32_t free_schid, free_devno;
2092
2093 assert(ssid && devno && schid);
2094 for (*ssid = 0; *ssid <= MAX_SSID; (*ssid)++) {
2095 free_schid = css_find_free_subch(cssid, *ssid);
2096 if (free_schid > MAX_SCHID) {
2097 continue;
2098 }
2099 free_devno = css_find_free_devno(cssid, *ssid, free_schid);
2100 if (free_devno > MAX_DEVNO) {
2101 continue;
2102 }
2103 *schid = free_schid;
2104 *devno = free_devno;
2105 return true;
2106 }
2107 error_setg(errp, "Virtual channel subsystem is full!");
2108 return false;
2109}
2110
df1fe5bb
CH		 2111bool css_subch_visible(SubchDev *sch)
2112{
562f5e0b 2113 if (sch->ssid > channel_subsys.max_ssid) {
df1fe5bb
CH		 2114 return false;
2115 }
2116
562f5e0b
EH		 2117 if (sch->cssid != channel_subsys.default_cssid) {
2118 return (channel_subsys.max_cssid > 0);
df1fe5bb
CH		 2119 }
2120
2121 return true;
2122}
2123
2124bool css_present(uint8_t cssid)
2125{
562f5e0b 2126 return (channel_subsys.css[cssid] != NULL);
df1fe5bb
CH		 2127}
2128
2129bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno)
2130{
562f5e0b 2131 if (!channel_subsys.css[cssid]) {
df1fe5bb
CH		 2132 return false;
2133 }
562f5e0b 2134 if (!channel_subsys.css[cssid]->sch_set[ssid]) {
df1fe5bb
CH		 2135 return false;
2136 }
2137
2138 return !!test_bit(devno,
562f5e0b 2139 channel_subsys.css[cssid]->sch_set[ssid]->devnos_used);
df1fe5bb
CH		 2140}
2141
2142void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
2143 uint16_t devno, SubchDev *sch)
2144{
2145 CssImage *css;
2146 SubchSet *s_set;
2147
2148 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid,
2149 devno);
562f5e0b 2150 if (!channel_subsys.css[cssid]) {
df1fe5bb
CH		 2151 fprintf(stderr,
2152 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n",
2153 __func__, cssid, ssid, schid);
2154 return;
2155 }
562f5e0b 2156 css = channel_subsys.css[cssid];
df1fe5bb
CH		 2157
2158 if (!css->sch_set[ssid]) {
96f64aa8 2159 css->sch_set[ssid] = g_new0(SubchSet, 1);
df1fe5bb
CH		 2160 }
2161 s_set = css->sch_set[ssid];
2162
2163 s_set->sch[schid] = sch;
2164 if (sch) {
2165 set_bit(schid, s_set->schids_used);
2166 set_bit(devno, s_set->devnos_used);
2167 } else {
2168 clear_bit(schid, s_set->schids_used);
2169 clear_bit(devno, s_set->devnos_used);
2170 }
2171}
2172
f6dde1b0 2173void css_crw_add_to_queue(CRW crw)
df1fe5bb
CH		 2174{
2175 CrwContainer *crw_cont;
2176
f6dde1b0
EF		 2177 trace_css_crw((crw.flags & CRW_FLAGS_MASK_RSC) >> 8,
2178 crw.flags & CRW_FLAGS_MASK_ERC,
2179 crw.rsid,
2180 (crw.flags & CRW_FLAGS_MASK_C) ? "(chained)" : "");
2181
df1fe5bb 2182 /* TODO: Maybe use a static crw pool? */
96f64aa8 2183 crw_cont = g_try_new0(CrwContainer, 1);
df1fe5bb 2184 if (!crw_cont) {
562f5e0b 2185 channel_subsys.crws_lost = true;
df1fe5bb
CH		 2186 return;
2187 }
f6dde1b0
EF		 2188
2189 crw_cont->crw = crw;
df1fe5bb 2190
562f5e0b 2191 QTAILQ_INSERT_TAIL(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb 2192
562f5e0b
EH		 2193 if (channel_subsys.do_crw_mchk) {
2194 channel_subsys.do_crw_mchk = false;
df1fe5bb 2195 /* Inject crw pending machine check. */
de13d216 2196 s390_crw_mchk();
df1fe5bb
CH		 2197 }
2198}
2199
f6dde1b0
EF		 2200void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited,
2201 int chain, uint16_t rsid)
2202{
2203 CRW crw;
2204
2205 crw.flags = (rsc << 8) | erc;
2206 if (solicited) {
2207 crw.flags |= CRW_FLAGS_MASK_S;
2208 }
2209 if (chain) {
2210 crw.flags |= CRW_FLAGS_MASK_C;
2211 }
2212 crw.rsid = rsid;
2213 if (channel_subsys.crws_lost) {
2214 crw.flags |= CRW_FLAGS_MASK_R;
2215 channel_subsys.crws_lost = false;
2216 }
2217
2218 css_crw_add_to_queue(crw);
2219}
2220
df1fe5bb
CH		 2221void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
2222 int hotplugged, int add)
2223{
2224 uint8_t guest_cssid;
2225 bool chain_crw;
2226
2227 if (add && !hotplugged) {
2228 return;
2229 }
562f5e0b 2230 if (channel_subsys.max_cssid == 0) {
df1fe5bb 2231 /* Default cssid shows up as 0. */
562f5e0b 2232 guest_cssid = (cssid == channel_subsys.default_cssid) ? 0 : cssid;
df1fe5bb
CH		 2233 } else {
2234 /* Show real cssid to the guest. */
2235 guest_cssid = cssid;
2236 }
2237 /*
2238 * Only notify for higher subchannel sets/channel subsystems if the
2239 * guest has enabled it.
2240 */
562f5e0b
EH		 2241 if ((ssid > channel_subsys.max_ssid) ||
2242 (guest_cssid > channel_subsys.max_cssid) ||
2243 ((channel_subsys.max_cssid == 0) &&
2244 (cssid != channel_subsys.default_cssid))) {
df1fe5bb
CH		 2245 return;
2246 }
562f5e0b
EH		 2247 chain_crw = (channel_subsys.max_ssid > 0) ||
2248 (channel_subsys.max_cssid > 0);
5c8d6f00 2249 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, chain_crw ? 1 : 0, schid);
df1fe5bb 2250 if (chain_crw) {
5c8d6f00 2251 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 0,
df1fe5bb
CH		 2252 (guest_cssid << 8) | (ssid << 4));
2253 }
c1755b14
HP		 2254 /* RW_ERC_IPI --> clear pending interrupts */
2255 css_clear_io_interrupt(css_do_build_subchannel_id(cssid, ssid), schid);
df1fe5bb
CH		 2256}
2257
2258void css_generate_chp_crws(uint8_t cssid, uint8_t chpid)
2259{
2260 /* TODO */
2261}
2262
8cba80c3
FB		 2263void css_generate_css_crws(uint8_t cssid)
2264{
562f5e0b 2265 if (!channel_subsys.sei_pending) {
5c8d6f00 2266 css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, 0, cssid);
c81b4f89 2267 }
562f5e0b 2268 channel_subsys.sei_pending = true;
c81b4f89
SSG		 2269}
2270
2271void css_clear_sei_pending(void)
2272{
562f5e0b 2273 channel_subsys.sei_pending = false;
8cba80c3
FB		 2274}
2275
df1fe5bb
CH		 2276int css_enable_mcsse(void)
2277{
2278 trace_css_enable_facility("mcsse");
562f5e0b 2279 channel_subsys.max_cssid = MAX_CSSID;
df1fe5bb
CH		 2280 return 0;
2281}
2282
2283int css_enable_mss(void)
2284{
2285 trace_css_enable_facility("mss");
562f5e0b 2286 channel_subsys.max_ssid = MAX_SSID;
df1fe5bb
CH		 2287 return 0;
2288}
2289
df1fe5bb
CH		 2290void css_reset_sch(SubchDev *sch)
2291{
bea0279b 2292 SCHIB *schib = &sch->curr_status;
df1fe5bb 2293
bea0279b 2294 if ((schib->pmcw.flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) {
62ac4a52
TH		 2295 sch->disable_cb(sch);
2296 }
2297
bea0279b
DB		 2298 schib->pmcw.intparm = 0;
2299 schib->pmcw.flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
df1fe5bb
CH		 2300 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
2301 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF);
bea0279b
DB		 2302 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV;
2303 schib->pmcw.devno = sch->devno;
2304 schib->pmcw.pim = 0x80;
2305 schib->pmcw.lpm = schib->pmcw.pim;
2306 schib->pmcw.pnom = 0;
2307 schib->pmcw.lpum = 0;
2308 schib->pmcw.mbi = 0;
2309 schib->pmcw.pom = 0xff;
2310 schib->pmcw.pam = 0x80;
2311 schib->pmcw.chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME |
df1fe5bb
CH		 2312 PMCW_CHARS_MASK_CSENSE);
2313
bea0279b
DB		 2314 memset(&schib->scsw, 0, sizeof(schib->scsw));
2315 schib->mba = 0;
df1fe5bb
CH		 2316
2317 sch->channel_prog = 0x0;
2318 sch->last_cmd_valid = false;
7e749462 2319 sch->thinint_active = false;
df1fe5bb
CH		 2320}
2321
2322void css_reset(void)
2323{
2324 CrwContainer *crw_cont;
2325
2326 /* Clean up monitoring. */
562f5e0b
EH		 2327 channel_subsys.chnmon_active = false;
2328 channel_subsys.chnmon_area = 0;
df1fe5bb
CH		 2329
2330 /* Clear pending CRWs. */
562f5e0b
EH		 2331 while ((crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws))) {
2332 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb
CH		 2333 g_free(crw_cont);
2334 }
562f5e0b
EH		 2335 channel_subsys.sei_pending = false;
2336 channel_subsys.do_crw_mchk = true;
2337 channel_subsys.crws_lost = false;
df1fe5bb
CH		 2338
2339 /* Reset maximum ids. */
562f5e0b
EH		 2340 channel_subsys.max_cssid = 0;
2341 channel_subsys.max_ssid = 0;
df1fe5bb 2342}
06e686ea
CH		 2343
2344static void get_css_devid(Object *obj, Visitor *v, const char *name,
2345 void *opaque, Error **errp)
2346{
2347 DeviceState *dev = DEVICE(obj);
2348 Property *prop = opaque;
2349 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop);
2350 char buffer[] = "xx.x.xxxx";
2351 char *p = buffer;
2352 int r;
2353
2354 if (dev_id->valid) {
2355
2356 r = snprintf(buffer, sizeof(buffer), "%02x.%1x.%04x", dev_id->cssid,
2357 dev_id->ssid, dev_id->devid);
2358 assert(r == sizeof(buffer) - 1);
2359
2360 /* drop leading zero */
2361 if (dev_id->cssid <= 0xf) {
2362 p++;
2363 }
2364 } else {
2365 snprintf(buffer, sizeof(buffer), "<unset>");
2366 }
2367
2368 visit_type_str(v, name, &p, errp);
2369}
2370
2371/*
2372 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid
2373 */
2374static void set_css_devid(Object *obj, Visitor *v, const char *name,
2375 void *opaque, Error **errp)
2376{
2377 DeviceState *dev = DEVICE(obj);
2378 Property *prop = opaque;
2379 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop);
06e686ea
CH		 2380 char *str;
2381 int num, n1, n2;
2382 unsigned int cssid, ssid, devid;
2383
2384 if (dev->realized) {
2385 qdev_prop_set_after_realize(dev, name, errp);
2386 return;
2387 }
2388
668f62ec 2389 if (!visit_type_str(v, name, &str, errp)) {
06e686ea
CH		 2390 return;
2391 }
2392
2393 num = sscanf(str, "%2x.%1x%n.%4x%n", &cssid, &ssid, &n1, &devid, &n2);
2394 if (num != 3 || (n2 - n1) != 5 || strlen(str) != n2) {
2395 error_set_from_qdev_prop_error(errp, EINVAL, dev, prop, str);
2396 goto out;
2397 }
2398 if ((cssid > MAX_CSSID) || (ssid > MAX_SSID)) {
2399 error_setg(errp, "Invalid cssid or ssid: cssid %x, ssid %x",
2400 cssid, ssid);
2401 goto out;
2402 }
2403
2404 dev_id->cssid = cssid;
2405 dev_id->ssid = ssid;
2406 dev_id->devid = devid;
2407 dev_id->valid = true;
2408
2409out:
2410 g_free(str);
2411}
2412
1b6b7d10 2413const PropertyInfo css_devid_propinfo = {
06e686ea
CH		 2414 .name = "str",
2415 .description = "Identifier of an I/O device in the channel "
2416 "subsystem, example: fe.1.23ab",
2417 .get = get_css_devid,
2418 .set = set_css_devid,
2419};
cf249935 2420
1b6b7d10 2421const PropertyInfo css_devid_ro_propinfo = {
c35fc6aa
DJS		 2422 .name = "str",
2423 .description = "Read-only identifier of an I/O device in the channel "
2424 "subsystem, example: fe.1.23ab",
2425 .get = get_css_devid,
2426};
2427
36699ab4 2428SubchDev *css_create_sch(CssDevId bus_id, Error **errp)
cf249935
SS		 2429{
2430 uint16_t schid = 0;
2431 SubchDev *sch;
2432
817d4a6b 2433 if (bus_id.valid) {
36699ab4 2434 if (!channel_subsys.css[bus_id.cssid]) {
817d4a6b
DJS		 2435 css_create_css_image(bus_id.cssid, false);
2436 }
2437
cf249935
SS		 2438 if (!css_find_free_subch_for_devno(bus_id.cssid, bus_id.ssid,
2439 bus_id.devid, &schid, errp)) {
2440 return NULL;
2441 }
817d4a6b 2442 } else {
99577c49 2443 for (bus_id.cssid = channel_subsys.default_cssid;;) {
817d4a6b
DJS		 2444 if (!channel_subsys.css[bus_id.cssid]) {
2445 css_create_css_image(bus_id.cssid, false);
2446 }
2447
2448 if (css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid,
2449 &bus_id.devid, &schid,
2450 NULL)) {
2451 break;
2452 }
99577c49
HP		 2453 bus_id.cssid = (bus_id.cssid + 1) % MAX_CSSID;
2454 if (bus_id.cssid == channel_subsys.default_cssid) {
817d4a6b
DJS		 2455 error_setg(errp, "Virtual channel subsystem is full!");
2456 return NULL;
2457 }
2458 }
cf249935
SS		 2459 }
2460
96f64aa8 2461 sch = g_new0(SubchDev, 1);
cf249935
SS		 2462 sch->cssid = bus_id.cssid;
2463 sch->ssid = bus_id.ssid;
2464 sch->devno = bus_id.devid;
2465 sch->schid = schid;
2466 css_subch_assign(sch->cssid, sch->ssid, schid, sch->devno, sch);
2467 return sch;
2468}
8f3cf012
XFR		 2469
2470static int css_sch_get_chpids(SubchDev *sch, CssDevId *dev_id)
2471{
2472 char *fid_path;
2473 FILE *fd;
2474 uint32_t chpid[8];
2475 int i;
bea0279b 2476 SCHIB *schib = &sch->curr_status;
8f3cf012
XFR		 2477
2478 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids",
2479 dev_id->cssid, dev_id->ssid, dev_id->devid);
2480 fd = fopen(fid_path, "r");
2481 if (fd == NULL) {
2482 error_report("%s: open %s failed", __func__, fid_path);
2483 g_free(fid_path);
2484 return -EINVAL;
2485 }
2486
2487 if (fscanf(fd, "%x %x %x %x %x %x %x %x",
2488 &chpid[0], &chpid[1], &chpid[2], &chpid[3],
2489 &chpid[4], &chpid[5], &chpid[6], &chpid[7]) != 8) {
2490 fclose(fd);
2491 g_free(fid_path);
2492 return -EINVAL;
2493 }
2494
bea0279b
DB		 2495 for (i = 0; i < ARRAY_SIZE(schib->pmcw.chpid); i++) {
2496 schib->pmcw.chpid[i] = chpid[i];
8f3cf012
XFR		 2497 }
2498
2499 fclose(fd);
2500 g_free(fid_path);
2501
2502 return 0;
2503}
2504
2505static int css_sch_get_path_masks(SubchDev *sch, CssDevId *dev_id)
2506{
2507 char *fid_path;
2508 FILE *fd;
2509 uint32_t pim, pam, pom;
bea0279b 2510 SCHIB *schib = &sch->curr_status;
8f3cf012
XFR		 2511
2512 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom",
2513 dev_id->cssid, dev_id->ssid, dev_id->devid);
2514 fd = fopen(fid_path, "r");
2515 if (fd == NULL) {
2516 error_report("%s: open %s failed", __func__, fid_path);
2517 g_free(fid_path);
2518 return -EINVAL;
2519 }
2520
2521 if (fscanf(fd, "%x %x %x", &pim, &pam, &pom) != 3) {
2522 fclose(fd);
2523 g_free(fid_path);
2524 return -EINVAL;
2525 }
2526
bea0279b
DB		 2527 schib->pmcw.pim = pim;
2528 schib->pmcw.pam = pam;
2529 schib->pmcw.pom = pom;
8f3cf012
XFR		 2530 fclose(fd);
2531 g_free(fid_path);
2532
2533 return 0;
2534}
2535
2536static int css_sch_get_chpid_type(uint8_t chpid, uint32_t *type,
2537 CssDevId *dev_id)
2538{
2539 char *fid_path;
2540 FILE *fd;
2541
2542 fid_path = g_strdup_printf("/sys/devices/css%x/chp0.%02x/type",
2543 dev_id->cssid, chpid);
2544 fd = fopen(fid_path, "r");
2545 if (fd == NULL) {
2546 error_report("%s: open %s failed", __func__, fid_path);
2547 g_free(fid_path);
2548 return -EINVAL;
2549 }
2550
2551 if (fscanf(fd, "%x", type) != 1) {
2552 fclose(fd);
2553 g_free(fid_path);
2554 return -EINVAL;
2555 }
2556
2557 fclose(fd);
2558 g_free(fid_path);
2559
2560 return 0;
2561}
2562
2563/*
2564 * We currently retrieve the real device information from sysfs to build the
2565 * guest subchannel information block without considering the migration feature.
2566 * We need to revisit this problem when we want to add migration support.
2567 */
2568int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id)
2569{
2570 CssImage *css = channel_subsys.css[sch->cssid];
bea0279b 2571 SCHIB *schib = &sch->curr_status;
8f3cf012
XFR		 2572 uint32_t type;
2573 int i, ret;
2574
2575 assert(css != NULL);
bea0279b
DB		 2576 memset(&schib->pmcw, 0, sizeof(PMCW));
2577 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV;
8f3cf012 2578 /* We are dealing with I/O subchannels only. */
bea0279b 2579 schib->pmcw.devno = sch->devno;
8f3cf012
XFR		 2580
2581 /* Grab path mask from sysfs. */
2582 ret = css_sch_get_path_masks(sch, dev_id);
2583 if (ret) {
2584 return ret;
2585 }
2586
2587 /* Grab chpids from sysfs. */
2588 ret = css_sch_get_chpids(sch, dev_id);
2589 if (ret) {
2590 return ret;
2591 }
2592
2593 /* Build chpid type. */
bea0279b
DB		 2594 for (i = 0; i < ARRAY_SIZE(schib->pmcw.chpid); i++) {
2595 if (schib->pmcw.chpid[i] && !css->chpids[schib->pmcw.chpid[i]].in_use) {
2596 ret = css_sch_get_chpid_type(schib->pmcw.chpid[i], &type, dev_id);
8f3cf012
XFR		 2597 if (ret) {
2598 return ret;
2599 }
bea0279b 2600 css_add_chpid(sch->cssid, schib->pmcw.chpid[i], type, false);
8f3cf012
XFR		 2601 }
2602 }
2603
bea0279b
DB		 2604 memset(&schib->scsw, 0, sizeof(SCSW));
2605 schib->mba = 0;
2606 for (i = 0; i < ARRAY_SIZE(schib->mda); i++) {
2607 schib->mda[i] = 0;
8f3cf012
XFR		 2608 }
2609
2610 return 0;
2611}
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