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CommitLineData
8cba80c3
FB
1/*
2 * s390 PCI BUS
3 *
4 * Copyright 2014 IBM Corp.
5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
6 * Hong Bo Li <lihbbj@cn.ibm.com>
7 * Yi Min Zhao <zyimin@cn.ibm.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or (at
10 * your option) any later version. See the COPYING file in the top-level
11 * directory.
12 */
13
9615495a 14#include "qemu/osdep.h"
3e5cfba3
YMZ
15#include "qapi/error.h"
16#include "qapi/visitor.h"
4771d756 17#include "cpu.h"
8cba80c3 18#include "s390-pci-bus.h"
259a4f0a 19#include "s390-pci-inst.h"
a9c94277 20#include "hw/pci/pci_bus.h"
a27bd6c7 21#include "hw/qdev-properties.h"
3fc92a24 22#include "hw/pci/pci_bridge.h"
a9c94277
MA
23#include "hw/pci/msi.h"
24#include "qemu/error-report.h"
0b8fa32f 25#include "qemu/module.h"
8cba80c3 26
229913f0
DA
27#ifndef DEBUG_S390PCI_BUS
28#define DEBUG_S390PCI_BUS 0
8cba80c3
FB
29#endif
30
229913f0
DA
31#define DPRINTF(fmt, ...) \
32 do { \
33 if (DEBUG_S390PCI_BUS) { \
34 fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); \
35 } \
36 } while (0)
37
a975a24a 38S390pciState *s390_get_phb(void)
e7d33695
YMZ
39{
40 static S390pciState *phb;
41
42 if (!phb) {
43 phb = S390_PCI_HOST_BRIDGE(
44 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
45 assert(phb != NULL);
46 }
47
48 return phb;
49}
50
1c5deaec 51int pci_chsc_sei_nt2_get_event(void *res)
8cba80c3
FB
52{
53 ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res;
54 PciCcdfAvail *accdf;
55 PciCcdfErr *eccdf;
56 int rc = 1;
57 SeiContainer *sei_cont;
e7d33695 58 S390pciState *s = s390_get_phb();
8cba80c3
FB
59
60 sei_cont = QTAILQ_FIRST(&s->pending_sei);
61 if (sei_cont) {
62 QTAILQ_REMOVE(&s->pending_sei, sei_cont, link);
63 nt2_res->nt = 2;
64 nt2_res->cc = sei_cont->cc;
d3321fc7 65 nt2_res->length = cpu_to_be16(sizeof(ChscSeiNt2Res));
8cba80c3
FB
66 switch (sei_cont->cc) {
67 case 1: /* error event */
68 eccdf = (PciCcdfErr *)nt2_res->ccdf;
69 eccdf->fid = cpu_to_be32(sei_cont->fid);
70 eccdf->fh = cpu_to_be32(sei_cont->fh);
71 eccdf->e = cpu_to_be32(sei_cont->e);
72 eccdf->faddr = cpu_to_be64(sei_cont->faddr);
73 eccdf->pec = cpu_to_be16(sei_cont->pec);
74 break;
75 case 2: /* availability event */
76 accdf = (PciCcdfAvail *)nt2_res->ccdf;
77 accdf->fid = cpu_to_be32(sei_cont->fid);
78 accdf->fh = cpu_to_be32(sei_cont->fh);
79 accdf->pec = cpu_to_be16(sei_cont->pec);
80 break;
81 default:
82 abort();
83 }
84 g_free(sei_cont);
85 rc = 0;
86 }
87
88 return rc;
89}
90
1c5deaec 91int pci_chsc_sei_nt2_have_event(void)
8cba80c3 92{
e7d33695 93 S390pciState *s = s390_get_phb();
8cba80c3
FB
94
95 return !QTAILQ_EMPTY(&s->pending_sei);
96}
97
a975a24a
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98S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s,
99 S390PCIBusDevice *pbdev)
4e3bfc16 100{
e70377df
PM
101 S390PCIBusDevice *ret = pbdev ? QTAILQ_NEXT(pbdev, link) :
102 QTAILQ_FIRST(&s->zpci_devs);
4e3bfc16 103
e70377df
PM
104 while (ret && ret->state == ZPCI_FS_RESERVED) {
105 ret = QTAILQ_NEXT(ret, link);
4e3bfc16
YMZ
106 }
107
e70377df 108 return ret;
4e3bfc16
YMZ
109}
110
a975a24a 111S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid)
8cba80c3
FB
112{
113 S390PCIBusDevice *pbdev;
8cba80c3 114
e70377df
PM
115 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) {
116 if (pbdev->fid == fid) {
8cba80c3
FB
117 return pbdev;
118 }
119 }
120
121 return NULL;
122}
123
8f5cb693 124void s390_pci_sclp_configure(SCCB *sccb)
8cba80c3 125{
80b7a265 126 IoaCfgSccb *psccb = (IoaCfgSccb *)sccb;
a975a24a
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127 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(s390_get_phb(),
128 be32_to_cpu(psccb->aid));
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129 uint16_t rc;
130
5d1abf23 131 if (!pbdev) {
8f5cb693
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132 DPRINTF("sclp config no dev found\n");
133 rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
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YMZ
134 goto out;
135 }
136
137 switch (pbdev->state) {
138 case ZPCI_FS_RESERVED:
139 rc = SCLP_RC_ADAPTER_IN_RESERVED_STATE;
140 break;
141 case ZPCI_FS_STANDBY:
142 pbdev->state = ZPCI_FS_DISABLED;
143 rc = SCLP_RC_NORMAL_COMPLETION;
144 break;
145 default:
146 rc = SCLP_RC_NO_ACTION_REQUIRED;
8f5cb693 147 }
3b40ea29 148out:
8f5cb693
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149 psccb->header.response_code = cpu_to_be16(rc);
150}
151
e0998fe8
DH
152static void s390_pci_perform_unplug(S390PCIBusDevice *pbdev)
153{
154 HotplugHandler *hotplug_ctrl;
155
156 /* Unplug the PCI device */
157 if (pbdev->pdev) {
07578b0a
DH
158 DeviceState *pdev = DEVICE(pbdev->pdev);
159
160 hotplug_ctrl = qdev_get_hotplug_handler(pdev);
161 hotplug_handler_unplug(hotplug_ctrl, pdev, &error_abort);
162 object_unparent(OBJECT(pdev));
e0998fe8
DH
163 }
164
165 /* Unplug the zPCI device */
166 hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(pbdev));
167 hotplug_handler_unplug(hotplug_ctrl, DEVICE(pbdev), &error_abort);
07578b0a 168 object_unparent(OBJECT(pbdev));
e0998fe8
DH
169}
170
8f5cb693
YMZ
171void s390_pci_sclp_deconfigure(SCCB *sccb)
172{
80b7a265 173 IoaCfgSccb *psccb = (IoaCfgSccb *)sccb;
a975a24a
YMZ
174 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(s390_get_phb(),
175 be32_to_cpu(psccb->aid));
8f5cb693
YMZ
176 uint16_t rc;
177
5d1abf23 178 if (!pbdev) {
8f5cb693 179 DPRINTF("sclp deconfig no dev found\n");
8cba80c3 180 rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
5d1abf23
YMZ
181 goto out;
182 }
183
184 switch (pbdev->state) {
185 case ZPCI_FS_RESERVED:
186 rc = SCLP_RC_ADAPTER_IN_RESERVED_STATE;
187 break;
188 case ZPCI_FS_STANDBY:
189 rc = SCLP_RC_NO_ACTION_REQUIRED;
190 break;
191 default:
192 if (pbdev->summary_ind) {
193 pci_dereg_irqs(pbdev);
194 }
de91ea92
YMZ
195 if (pbdev->iommu->enabled) {
196 pci_dereg_ioat(pbdev->iommu);
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197 }
198 pbdev->state = ZPCI_FS_STANDBY;
199 rc = SCLP_RC_NORMAL_COMPLETION;
93d16d81 200
9f2a46b1 201 if (pbdev->unplug_requested) {
e0998fe8 202 s390_pci_perform_unplug(pbdev);
93d16d81 203 }
8cba80c3 204 }
3b40ea29 205out:
8cba80c3 206 psccb->header.response_code = cpu_to_be16(rc);
8cba80c3
FB
207}
208
a975a24a 209static S390PCIBusDevice *s390_pci_find_dev_by_uid(S390pciState *s, uint16_t uid)
3e5cfba3 210{
3e5cfba3 211 S390PCIBusDevice *pbdev;
3e5cfba3 212
e70377df 213 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) {
3e5cfba3
YMZ
214 if (pbdev->uid == uid) {
215 return pbdev;
216 }
217 }
218
219 return NULL;
220}
221
ceb7054f
YMZ
222S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s,
223 const char *target)
3e5cfba3 224{
3e5cfba3 225 S390PCIBusDevice *pbdev;
3e5cfba3
YMZ
226
227 if (!target) {
228 return NULL;
229 }
230
e70377df 231 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) {
3e5cfba3
YMZ
232 if (!strcmp(pbdev->target, target)) {
233 return pbdev;
234 }
235 }
236
237 return NULL;
238}
239
e0998fe8
DH
240static S390PCIBusDevice *s390_pci_find_dev_by_pci(S390pciState *s,
241 PCIDevice *pci_dev)
242{
243 S390PCIBusDevice *pbdev;
244
245 if (!pci_dev) {
246 return NULL;
247 }
248
249 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) {
250 if (pbdev->pdev == pci_dev) {
251 return pbdev;
252 }
253 }
254
255 return NULL;
256}
257
a975a24a 258S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx)
8cba80c3 259{
df8dd91b 260 return g_hash_table_lookup(s->zpci_table, &idx);
8cba80c3
FB
261}
262
a975a24a 263S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh)
8cba80c3 264{
df8dd91b
YMZ
265 uint32_t idx = FH_MASK_INDEX & fh;
266 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_idx(s, idx);
8cba80c3 267
df8dd91b
YMZ
268 if (pbdev && pbdev->fh == fh) {
269 return pbdev;
8cba80c3
FB
270 }
271
272 return NULL;
273}
274
275static void s390_pci_generate_event(uint8_t cc, uint16_t pec, uint32_t fh,
276 uint32_t fid, uint64_t faddr, uint32_t e)
277{
b7022d9a 278 SeiContainer *sei_cont;
e7d33695 279 S390pciState *s = s390_get_phb();
8cba80c3 280
96f64aa8 281 sei_cont = g_new0(SeiContainer, 1);
8cba80c3
FB
282 sei_cont->fh = fh;
283 sei_cont->fid = fid;
284 sei_cont->cc = cc;
285 sei_cont->pec = pec;
286 sei_cont->faddr = faddr;
287 sei_cont->e = e;
288
289 QTAILQ_INSERT_TAIL(&s->pending_sei, sei_cont, link);
290 css_generate_css_crws(0);
291}
292
293static void s390_pci_generate_plug_event(uint16_t pec, uint32_t fh,
294 uint32_t fid)
295{
296 s390_pci_generate_event(2, pec, fh, fid, 0, 0);
297}
298
5d1abf23
YMZ
299void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
300 uint64_t faddr, uint32_t e)
8cba80c3
FB
301{
302 s390_pci_generate_event(1, pec, fh, fid, faddr, e);
303}
304
305static void s390_pci_set_irq(void *opaque, int irq, int level)
306{
307 /* nothing to do */
308}
309
310static int s390_pci_map_irq(PCIDevice *pci_dev, int irq_num)
311{
312 /* nothing to do */
313 return 0;
314}
315
316static uint64_t s390_pci_get_table_origin(uint64_t iota)
317{
318 return iota & ~ZPCI_IOTA_RTTO_FLAG;
319}
320
321static unsigned int calc_rtx(dma_addr_t ptr)
322{
323 return ((unsigned long) ptr >> ZPCI_RT_SHIFT) & ZPCI_INDEX_MASK;
324}
325
326static unsigned int calc_sx(dma_addr_t ptr)
327{
328 return ((unsigned long) ptr >> ZPCI_ST_SHIFT) & ZPCI_INDEX_MASK;
329}
330
331static unsigned int calc_px(dma_addr_t ptr)
332{
333 return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK;
334}
335
336static uint64_t get_rt_sto(uint64_t entry)
337{
338 return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX)
339 ? (entry & ZPCI_RTE_ADDR_MASK)
340 : 0;
341}
342
343static uint64_t get_st_pto(uint64_t entry)
344{
345 return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX)
346 ? (entry & ZPCI_STE_ADDR_MASK)
347 : 0;
348}
349
0125861e
YMZ
350static bool rt_entry_isvalid(uint64_t entry)
351{
352 return (entry & ZPCI_TABLE_VALID_MASK) == ZPCI_TABLE_VALID;
353}
354
355static bool pt_entry_isvalid(uint64_t entry)
356{
357 return (entry & ZPCI_PTE_VALID_MASK) == ZPCI_PTE_VALID;
358}
359
360static bool entry_isprotected(uint64_t entry)
361{
362 return (entry & ZPCI_TABLE_PROT_MASK) == ZPCI_TABLE_PROTECTED;
363}
364
365/* ett is expected table type, -1 page table, 0 segment table, 1 region table */
366static uint64_t get_table_index(uint64_t iova, int8_t ett)
367{
368 switch (ett) {
369 case ZPCI_ETT_PT:
370 return calc_px(iova);
371 case ZPCI_ETT_ST:
372 return calc_sx(iova);
373 case ZPCI_ETT_RT:
374 return calc_rtx(iova);
375 }
376
377 return -1;
378}
379
380static bool entry_isvalid(uint64_t entry, int8_t ett)
381{
382 switch (ett) {
383 case ZPCI_ETT_PT:
384 return pt_entry_isvalid(entry);
385 case ZPCI_ETT_ST:
386 case ZPCI_ETT_RT:
387 return rt_entry_isvalid(entry);
388 }
389
390 return false;
391}
392
393/* Return true if address translation is done */
394static bool translate_iscomplete(uint64_t entry, int8_t ett)
395{
396 switch (ett) {
397 case 0:
398 return (entry & ZPCI_TABLE_FC) ? true : false;
399 case 1:
400 return false;
401 }
402
403 return true;
404}
405
406static uint64_t get_frame_size(int8_t ett)
407{
408 switch (ett) {
409 case ZPCI_ETT_PT:
410 return 1ULL << 12;
411 case ZPCI_ETT_ST:
412 return 1ULL << 20;
413 case ZPCI_ETT_RT:
414 return 1ULL << 31;
415 }
416
417 return 0;
418}
419
420static uint64_t get_next_table_origin(uint64_t entry, int8_t ett)
421{
422 switch (ett) {
423 case ZPCI_ETT_PT:
424 return entry & ZPCI_PTE_ADDR_MASK;
425 case ZPCI_ETT_ST:
426 return get_st_pto(entry);
427 case ZPCI_ETT_RT:
428 return get_rt_sto(entry);
429 }
430
431 return 0;
432}
433
434/**
435 * table_translate: do translation within one table and return the following
436 * table origin
437 *
438 * @entry: the entry being translated, the result is stored in this.
439 * @to: the address of table origin.
440 * @ett: expected table type, 1 region table, 0 segment table and -1 page table.
441 * @error: error code
442 */
443static uint64_t table_translate(S390IOTLBEntry *entry, uint64_t to, int8_t ett,
444 uint16_t *error)
445{
446 uint64_t tx, te, nto = 0;
447 uint16_t err = 0;
448
449 tx = get_table_index(entry->iova, ett);
450 te = address_space_ldq(&address_space_memory, to + tx * sizeof(uint64_t),
451 MEMTXATTRS_UNSPECIFIED, NULL);
452
453 if (!te) {
454 err = ERR_EVENT_INVALTE;
8cba80c3
FB
455 goto out;
456 }
457
0125861e
YMZ
458 if (!entry_isvalid(te, ett)) {
459 entry->perm &= IOMMU_NONE;
8cba80c3
FB
460 goto out;
461 }
462
0125861e
YMZ
463 if (ett == ZPCI_ETT_RT && ((te & ZPCI_TABLE_LEN_RTX) != ZPCI_TABLE_LEN_RTX
464 || te & ZPCI_TABLE_OFFSET_MASK)) {
465 err = ERR_EVENT_INVALTL;
466 goto out;
467 }
8cba80c3 468
0125861e
YMZ
469 nto = get_next_table_origin(te, ett);
470 if (!nto) {
471 err = ERR_EVENT_TT;
472 goto out;
473 }
474
475 if (entry_isprotected(te)) {
476 entry->perm &= IOMMU_RO;
477 } else {
478 entry->perm &= IOMMU_RW;
479 }
480
481 if (translate_iscomplete(te, ett)) {
482 switch (ett) {
483 case ZPCI_ETT_PT:
484 entry->translated_addr = te & ZPCI_PTE_ADDR_MASK;
485 break;
486 case ZPCI_ETT_ST:
487 entry->translated_addr = (te & ZPCI_SFAA_MASK) |
488 (entry->iova & ~ZPCI_SFAA_MASK);
489 break;
490 }
491 nto = 0;
492 }
8cba80c3 493out:
0125861e
YMZ
494 if (err) {
495 entry->perm = IOMMU_NONE;
496 *error = err;
497 }
498 entry->len = get_frame_size(ett);
499 return nto;
500}
501
502uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr,
503 S390IOTLBEntry *entry)
504{
505 uint64_t to = s390_pci_get_table_origin(g_iota);
506 int8_t ett = 1;
507 uint16_t error = 0;
508
509 entry->iova = addr & PAGE_MASK;
510 entry->translated_addr = 0;
511 entry->perm = IOMMU_RW;
512
513 if (entry_isprotected(g_iota)) {
514 entry->perm &= IOMMU_RO;
515 }
516
517 while (to) {
518 to = table_translate(entry, to, ett--, &error);
519 }
520
521 return error;
8cba80c3
FB
522}
523
3df9d748 524static IOMMUTLBEntry s390_translate_iommu(IOMMUMemoryRegion *mr, hwaddr addr,
2c91bcf2 525 IOMMUAccessFlags flag, int iommu_idx)
8cba80c3 526{
de91ea92 527 S390PCIIOMMU *iommu = container_of(mr, S390PCIIOMMU, iommu_mr);
b3f05d8c
YMZ
528 S390IOTLBEntry *entry;
529 uint64_t iova = addr & PAGE_MASK;
0125861e 530 uint16_t error = 0;
8cba80c3
FB
531 IOMMUTLBEntry ret = {
532 .target_as = &address_space_memory,
533 .iova = 0,
534 .translated_addr = 0,
535 .addr_mask = ~(hwaddr)0,
536 .perm = IOMMU_NONE,
537 };
538
de91ea92 539 switch (iommu->pbdev->state) {
5d1abf23
YMZ
540 case ZPCI_FS_ENABLED:
541 case ZPCI_FS_BLOCKED:
de91ea92 542 if (!iommu->enabled) {
5d1abf23
YMZ
543 return ret;
544 }
545 break;
546 default:
dce1b089
YMZ
547 return ret;
548 }
549
8cba80c3
FB
550 DPRINTF("iommu trans addr 0x%" PRIx64 "\n", addr);
551
de91ea92 552 if (addr < iommu->pba || addr > iommu->pal) {
0125861e
YMZ
553 error = ERR_EVENT_OORANGE;
554 goto err;
8cba80c3
FB
555 }
556
b3f05d8c
YMZ
557 entry = g_hash_table_lookup(iommu->iotlb, &iova);
558 if (entry) {
559 ret.iova = entry->iova;
560 ret.translated_addr = entry->translated_addr;
561 ret.addr_mask = entry->len - 1;
562 ret.perm = entry->perm;
563 } else {
564 ret.iova = iova;
565 ret.addr_mask = ~PAGE_MASK;
566 ret.perm = IOMMU_NONE;
567 }
8cba80c3 568
0125861e
YMZ
569 if (flag != IOMMU_NONE && !(flag & ret.perm)) {
570 error = ERR_EVENT_TPROTE;
571 }
572err:
573 if (error) {
574 iommu->pbdev->state = ZPCI_FS_ERROR;
575 s390_pci_generate_error_event(error, iommu->pbdev->fh,
576 iommu->pbdev->fid, addr, 0);
8cba80c3 577 }
8cba80c3
FB
578 return ret;
579}
580
6c5e7402
YMZ
581static void s390_pci_iommu_replay(IOMMUMemoryRegion *iommu,
582 IOMMUNotifier *notifier)
583{
584 /* It's impossible to plug a pci device on s390x that already has iommu
585 * mappings which need to be replayed, that is due to the "one iommu per
586 * zpci device" construct. But when we support migration of vfio-pci
587 * devices in future, we need to revisit this.
588 */
589 return;
590}
591
03805be0
YMZ
592static S390PCIIOMMU *s390_pci_get_iommu(S390pciState *s, PCIBus *bus,
593 int devfn)
594{
595 uint64_t key = (uintptr_t)bus;
596 S390PCIIOMMUTable *table = g_hash_table_lookup(s->iommu_table, &key);
597 S390PCIIOMMU *iommu;
598
599 if (!table) {
96f64aa8 600 table = g_new0(S390PCIIOMMUTable, 1);
03805be0
YMZ
601 table->key = key;
602 g_hash_table_insert(s->iommu_table, &table->key, table);
603 }
604
605 iommu = table->iommu[PCI_SLOT(devfn)];
606 if (!iommu) {
607 iommu = S390_PCI_IOMMU(object_new(TYPE_S390_PCI_IOMMU));
608
609 char *mr_name = g_strdup_printf("iommu-root-%02x:%02x.%01x",
610 pci_bus_num(bus),
611 PCI_SLOT(devfn),
612 PCI_FUNC(devfn));
613 char *as_name = g_strdup_printf("iommu-pci-%02x:%02x.%01x",
614 pci_bus_num(bus),
615 PCI_SLOT(devfn),
616 PCI_FUNC(devfn));
617 memory_region_init(&iommu->mr, OBJECT(iommu), mr_name, UINT64_MAX);
618 address_space_init(&iommu->as, &iommu->mr, as_name);
b3f05d8c
YMZ
619 iommu->iotlb = g_hash_table_new_full(g_int64_hash, g_int64_equal,
620 NULL, g_free);
03805be0
YMZ
621 table->iommu[PCI_SLOT(devfn)] = iommu;
622
623 g_free(mr_name);
624 g_free(as_name);
625 }
626
627 return iommu;
628}
629
8cba80c3
FB
630static AddressSpace *s390_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
631{
632 S390pciState *s = opaque;
03805be0 633 S390PCIIOMMU *iommu = s390_pci_get_iommu(s, bus, devfn);
8cba80c3 634
03805be0 635 return &iommu->as;
8cba80c3
FB
636}
637
638static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
639{
45175361 640 uint8_t expected, actual;
8cba80c3 641 hwaddr len = 1;
45175361
HP
642 /* avoid multiple fetches */
643 uint8_t volatile *ind_addr;
8cba80c3 644
85eb7c18 645 ind_addr = cpu_physical_memory_map(ind_loc, &len, true);
8cba80c3
FB
646 if (!ind_addr) {
647 s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0);
648 return -1;
649 }
45175361 650 actual = *ind_addr;
8cba80c3 651 do {
45175361
HP
652 expected = actual;
653 actual = atomic_cmpxchg(ind_addr, expected, expected | to_be_set);
654 } while (actual != expected);
655 cpu_physical_memory_unmap((void *)ind_addr, len, 1, len);
8cba80c3 656
45175361 657 return actual;
8cba80c3
FB
658}
659
660static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data,
661 unsigned int size)
662{
8f955950 663 S390PCIBusDevice *pbdev = opaque;
8cba80c3
FB
664 uint32_t vec = data & ZPCI_MSI_VEC_MASK;
665 uint64_t ind_bit;
666 uint32_t sum_bit;
8cba80c3 667
ceb7054f
YMZ
668 assert(pbdev);
669 DPRINTF("write_msix data 0x%" PRIx64 " idx %d vec 0x%x\n", data,
670 pbdev->idx, vec);
8cba80c3 671
5d1abf23 672 if (pbdev->state != ZPCI_FS_ENABLED) {
3be5c207
YMZ
673 return;
674 }
675
8cba80c3
FB
676 ind_bit = pbdev->routes.adapter.ind_offset;
677 sum_bit = pbdev->routes.adapter.summary_offset;
678
679 set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8,
680 0x80 >> ((ind_bit + vec) % 8));
681 if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8,
682 0x80 >> (sum_bit % 8))) {
25a08b8d 683 css_adapter_interrupt(CSS_IO_ADAPTER_PCI, pbdev->isc);
8cba80c3 684 }
8cba80c3
FB
685}
686
687static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size)
688{
689 return 0xffffffff;
690}
691
692static const MemoryRegionOps s390_msi_ctrl_ops = {
693 .write = s390_msi_ctrl_write,
694 .read = s390_msi_ctrl_read,
695 .endianness = DEVICE_LITTLE_ENDIAN,
696};
697
de91ea92 698void s390_pci_iommu_enable(S390PCIIOMMU *iommu)
f0a399db 699{
7df1dac5
MR
700 /*
701 * The iommu region is initialized against a 0-mapped address space,
702 * so the smallest IOMMU region we can define runs from 0 to the end
703 * of the PCI address space.
704 */
de91ea92 705 char *name = g_strdup_printf("iommu-s390-%04x", iommu->pbdev->uid);
1221a474
AK
706 memory_region_init_iommu(&iommu->iommu_mr, sizeof(iommu->iommu_mr),
707 TYPE_S390_IOMMU_MEMORY_REGION, OBJECT(&iommu->mr),
7df1dac5 708 name, iommu->pal + 1);
de91ea92 709 iommu->enabled = true;
3df9d748 710 memory_region_add_subregion(&iommu->mr, 0, MEMORY_REGION(&iommu->iommu_mr));
de91ea92 711 g_free(name);
71583888 712}
f0a399db 713
de91ea92 714void s390_pci_iommu_disable(S390PCIIOMMU *iommu)
71583888 715{
de91ea92 716 iommu->enabled = false;
b3f05d8c 717 g_hash_table_remove_all(iommu->iotlb);
3df9d748 718 memory_region_del_subregion(&iommu->mr, MEMORY_REGION(&iommu->iommu_mr));
de91ea92 719 object_unparent(OBJECT(&iommu->iommu_mr));
f0a399db
YMZ
720}
721
a975a24a 722static void s390_pci_iommu_free(S390pciState *s, PCIBus *bus, int32_t devfn)
8cba80c3 723{
03805be0
YMZ
724 uint64_t key = (uintptr_t)bus;
725 S390PCIIOMMUTable *table = g_hash_table_lookup(s->iommu_table, &key);
726 S390PCIIOMMU *iommu = table ? table->iommu[PCI_SLOT(devfn)] : NULL;
8cba80c3 727
03805be0
YMZ
728 if (!table || !iommu) {
729 return;
8cba80c3 730 }
03805be0
YMZ
731
732 table->iommu[PCI_SLOT(devfn)] = NULL;
b3f05d8c 733 g_hash_table_destroy(iommu->iotlb);
03805be0
YMZ
734 address_space_destroy(&iommu->as);
735 object_unparent(OBJECT(&iommu->mr));
736 object_unparent(OBJECT(iommu));
737 object_unref(OBJECT(iommu));
8cba80c3
FB
738}
739
b576d582 740static void s390_pcihost_realize(DeviceState *dev, Error **errp)
8cba80c3
FB
741{
742 PCIBus *b;
743 BusState *bus;
744 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
745 S390pciState *s = S390_PCI_HOST_BRIDGE(dev);
b576d582 746 Error *local_err = NULL;
8cba80c3
FB
747
748 DPRINTF("host_init\n");
749
b576d582
TH
750 b = pci_register_root_bus(dev, NULL, s390_pci_set_irq, s390_pci_map_irq,
751 NULL, get_system_memory(), get_system_io(), 0,
752 64, TYPE_PCI_BUS);
8cba80c3
FB
753 pci_setup_iommu(b, s390_pci_dma_iommu, s);
754
755 bus = BUS(b);
9bc6bfdf 756 qbus_set_hotplug_handler(bus, OBJECT(dev));
8cba80c3 757 phb->bus = b;
90a0f9af 758
b576d582 759 s->bus = S390_PCI_BUS(qbus_create(TYPE_S390_PCI_BUS, dev, NULL));
9bc6bfdf 760 qbus_set_hotplug_handler(BUS(s->bus), OBJECT(dev));
90a0f9af 761
03805be0
YMZ
762 s->iommu_table = g_hash_table_new_full(g_int64_hash, g_int64_equal,
763 NULL, g_free);
df8dd91b 764 s->zpci_table = g_hash_table_new_full(g_int_hash, g_int_equal, NULL, NULL);
d2f07120 765 s->bus_no = 0;
8cba80c3 766 QTAILQ_INIT(&s->pending_sei);
e70377df 767 QTAILQ_INIT(&s->zpci_devs);
dde522bb 768
1497c160 769 css_register_io_adapters(CSS_IO_ADAPTER_PCI, true, false,
b576d582 770 S390_ADAPTER_SUPPRESSIBLE, &local_err);
b2322003 771 error_propagate(errp, local_err);
8cba80c3
FB
772}
773
857cc719 774static int s390_pci_msix_init(S390PCIBusDevice *pbdev)
8cba80c3 775{
857cc719 776 char *name;
8cba80c3
FB
777 uint8_t pos;
778 uint16_t ctrl;
779 uint32_t table, pba;
780
781 pos = pci_find_capability(pbdev->pdev, PCI_CAP_ID_MSIX);
782 if (!pos) {
857cc719 783 return -1;
8cba80c3
FB
784 }
785
ce1307e1 786 ctrl = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_FLAGS,
8cba80c3
FB
787 pci_config_size(pbdev->pdev), sizeof(ctrl));
788 table = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_TABLE,
789 pci_config_size(pbdev->pdev), sizeof(table));
790 pba = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_PBA,
791 pci_config_size(pbdev->pdev), sizeof(pba));
792
793 pbdev->msix.table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
794 pbdev->msix.table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
795 pbdev->msix.pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
796 pbdev->msix.pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
797 pbdev->msix.entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
8f955950
YMZ
798
799 name = g_strdup_printf("msix-s390-%04x", pbdev->uid);
8f955950
YMZ
800 memory_region_init_io(&pbdev->msix_notify_mr, OBJECT(pbdev),
801 &s390_msi_ctrl_ops, pbdev, name, PAGE_SIZE);
802 memory_region_add_subregion(&pbdev->iommu->mr, ZPCI_MSI_ADDR,
803 &pbdev->msix_notify_mr);
8f955950 804 g_free(name);
857cc719
YMZ
805
806 return 0;
8f955950
YMZ
807}
808
809static void s390_pci_msix_free(S390PCIBusDevice *pbdev)
810{
811 memory_region_del_subregion(&pbdev->iommu->mr, &pbdev->msix_notify_mr);
812 object_unparent(OBJECT(&pbdev->msix_notify_mr));
813}
814
a975a24a 815static S390PCIBusDevice *s390_pci_device_new(S390pciState *s,
b6e67ecc 816 const char *target, Error **errp)
3e5cfba3 817{
b6e67ecc
DH
818 Error *local_err = NULL;
819 DeviceState *dev;
3e5cfba3 820
df707969 821 dev = qdev_try_new(TYPE_S390_PCI_DEVICE);
3e5cfba3 822 if (!dev) {
b6e67ecc 823 error_setg(errp, "zPCI device could not be created");
3e5cfba3
YMZ
824 return NULL;
825 }
826
778a2dc5 827 if (!object_property_set_str(OBJECT(dev), "target", target, &local_err)) {
b6e67ecc
DH
828 object_unparent(OBJECT(dev));
829 error_propagate_prepend(errp, local_err,
830 "zPCI device could not be created: ");
831 return NULL;
832 }
118bfd76 833 if (!qdev_realize_and_unref(dev, BUS(s->bus), &local_err)) {
b6e67ecc
DH
834 object_unparent(OBJECT(dev));
835 error_propagate_prepend(errp, local_err,
836 "zPCI device could not be created: ");
837 return NULL;
838 }
3e5cfba3
YMZ
839
840 return S390_PCI_DEVICE(dev);
841}
842
a975a24a 843static bool s390_pci_alloc_idx(S390pciState *s, S390PCIBusDevice *pbdev)
e70377df
PM
844{
845 uint32_t idx;
e70377df
PM
846
847 idx = s->next_idx;
a975a24a 848 while (s390_pci_find_dev_by_idx(s, idx)) {
e70377df
PM
849 idx = (idx + 1) & FH_MASK_INDEX;
850 if (idx == s->next_idx) {
851 return false;
852 }
853 }
854
855 pbdev->idx = idx;
e70377df
PM
856 return true;
857}
858
6069bcde
DH
859static void s390_pcihost_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
860 Error **errp)
861{
862 S390pciState *s = S390_PCI_HOST_BRIDGE(hotplug_dev);
863
703fef6f
DH
864 if (!s390_has_feat(S390_FEAT_ZPCI)) {
865 warn_report("Plugging a PCI/zPCI device without the 'zpci' CPU "
866 "feature enabled; the guest will not be able to see/use "
867 "this device");
868 }
869
6069bcde
DH
870 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
871 PCIDevice *pdev = PCI_DEVICE(dev);
872
873 if (pdev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
874 error_setg(errp, "multifunction not supported in s390");
875 return;
876 }
877 } else if (object_dynamic_cast(OBJECT(dev), TYPE_S390_PCI_DEVICE)) {
878 S390PCIBusDevice *pbdev = S390_PCI_DEVICE(dev);
879
880 if (!s390_pci_alloc_idx(s, pbdev)) {
881 error_setg(errp, "no slot for plugging zpci device");
882 return;
883 }
884 }
885}
886
150f4625
DH
887static void s390_pci_update_subordinate(PCIDevice *dev, uint32_t nr)
888{
889 uint32_t old_nr;
890
891 pci_default_write_config(dev, PCI_SUBORDINATE_BUS, nr, 1);
892 while (!pci_bus_is_root(pci_get_bus(dev))) {
893 dev = pci_get_bus(dev)->parent_dev;
894
895 old_nr = pci_default_read_config(dev, PCI_SUBORDINATE_BUS, 1);
896 if (old_nr < nr) {
897 pci_default_write_config(dev, PCI_SUBORDINATE_BUS, nr, 1);
898 }
899 }
900}
901
fa2a7751
DH
902static void s390_pcihost_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
903 Error **errp)
8cba80c3 904{
19375e9b 905 S390pciState *s = S390_PCI_HOST_BRIDGE(hotplug_dev);
af9ed379
YMZ
906 PCIDevice *pdev = NULL;
907 S390PCIBusDevice *pbdev = NULL;
3e5cfba3 908
3fc92a24 909 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
3fc92a24
PM
910 PCIBridge *pb = PCI_BRIDGE(dev);
911
150f4625 912 pdev = PCI_DEVICE(dev);
3fc92a24
PM
913 pci_bridge_map_irq(pb, dev->id, s390_pci_map_irq);
914 pci_setup_iommu(&pb->sec_bus, s390_pci_dma_iommu, s);
915
9bc6bfdf 916 qbus_set_hotplug_handler(BUS(&pb->sec_bus), OBJECT(s));
d2f07120
PM
917
918 if (dev->hotplugged) {
d30a7507
DH
919 pci_default_write_config(pdev, PCI_PRIMARY_BUS,
920 pci_dev_bus_num(pdev), 1);
d2f07120
PM
921 s->bus_no += 1;
922 pci_default_write_config(pdev, PCI_SECONDARY_BUS, s->bus_no, 1);
150f4625
DH
923
924 s390_pci_update_subordinate(pdev, s->bus_no);
d2f07120 925 }
3fc92a24 926 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
af9ed379
YMZ
927 pdev = PCI_DEVICE(dev);
928
929 if (!dev->id) {
930 /* In the case the PCI device does not define an id */
931 /* we generate one based on the PCI address */
932 dev->id = g_strdup_printf("auto_%02x:%02x.%01x",
cdc57472 933 pci_dev_bus_num(pdev),
af9ed379
YMZ
934 PCI_SLOT(pdev->devfn),
935 PCI_FUNC(pdev->devfn));
936 }
937
a975a24a 938 pbdev = s390_pci_find_dev_by_target(s, dev->id);
3e5cfba3 939 if (!pbdev) {
b6e67ecc 940 pbdev = s390_pci_device_new(s, dev->id, errp);
af9ed379 941 if (!pbdev) {
0d36d791 942 return;
af9ed379 943 }
3e5cfba3 944 }
8cba80c3 945
af9ed379
YMZ
946 if (object_dynamic_cast(OBJECT(dev), "vfio-pci")) {
947 pbdev->fh |= FH_SHM_VFIO;
948 } else {
949 pbdev->fh |= FH_SHM_EMUL;
950 }
8cba80c3 951
af9ed379 952 pbdev->pdev = pdev;
fd56e061 953 pbdev->iommu = s390_pci_get_iommu(s, pci_get_bus(pdev), pdev->devfn);
de91ea92 954 pbdev->iommu->pbdev = pbdev;
2c28c490 955 pbdev->state = ZPCI_FS_DISABLED;
8f955950 956
857cc719
YMZ
957 if (s390_pci_msix_init(pbdev)) {
958 error_setg(errp, "MSI-X support is mandatory "
959 "in the S390 architecture");
960 return;
961 }
8cba80c3 962
af9ed379 963 if (dev->hotplugged) {
d57d6abc 964 s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED ,
af9ed379
YMZ
965 pbdev->fh, pbdev->fid);
966 }
967 } else if (object_dynamic_cast(OBJECT(dev), TYPE_S390_PCI_DEVICE)) {
af9ed379 968 pbdev = S390_PCI_DEVICE(dev);
af9ed379 969
6069bcde
DH
970 /* the allocated idx is actually getting used */
971 s->next_idx = (pbdev->idx + 1) & FH_MASK_INDEX;
e70377df
PM
972 pbdev->fh = pbdev->idx;
973 QTAILQ_INSERT_TAIL(&s->zpci_devs, pbdev, link);
df8dd91b 974 g_hash_table_insert(s->zpci_table, &pbdev->idx, pbdev);
6ed675c9
LQ
975 } else {
976 g_assert_not_reached();
8cba80c3 977 }
8cba80c3
FB
978}
979
fa2a7751
DH
980static void s390_pcihost_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
981 Error **errp)
8cba80c3 982{
19375e9b 983 S390pciState *s = S390_PCI_HOST_BRIDGE(hotplug_dev);
af9ed379 984 S390PCIBusDevice *pbdev = NULL;
af9ed379 985
e0998fe8
DH
986 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
987 PCIDevice *pci_dev = PCI_DEVICE(dev);
988 PCIBus *bus;
989 int32_t devfn;
990
991 pbdev = s390_pci_find_dev_by_pci(s, PCI_DEVICE(dev));
992 g_assert(pbdev);
993
994 s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED,
995 pbdev->fh, pbdev->fid);
996 bus = pci_get_bus(pci_dev);
997 devfn = pci_dev->devfn;
981c3dcd 998 qdev_unrealize(dev);
e0998fe8
DH
999
1000 s390_pci_msix_free(pbdev);
1001 s390_pci_iommu_free(s, bus, devfn);
1002 pbdev->pdev = NULL;
1003 pbdev->state = ZPCI_FS_RESERVED;
1004 } else if (object_dynamic_cast(OBJECT(dev), TYPE_S390_PCI_DEVICE)) {
1005 pbdev = S390_PCI_DEVICE(dev);
e0998fe8
DH
1006 pbdev->fid = 0;
1007 QTAILQ_REMOVE(&s->zpci_devs, pbdev, link);
1008 g_hash_table_remove(s->zpci_table, &pbdev->idx);
981c3dcd 1009 qdev_unrealize(dev);
e0998fe8
DH
1010 }
1011}
1012
1013static void s390_pcihost_unplug_request(HotplugHandler *hotplug_dev,
1014 DeviceState *dev,
1015 Error **errp)
1016{
1017 S390pciState *s = S390_PCI_HOST_BRIDGE(hotplug_dev);
1018 S390PCIBusDevice *pbdev;
1019
3fc92a24
PM
1020 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
1021 error_setg(errp, "PCI bridge hot unplug currently not supported");
3fc92a24 1022 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
e0998fe8
DH
1023 /*
1024 * Redirect the unplug request to the zPCI device and remember that
1025 * we've checked the PCI device already (to prevent endless recursion).
1026 */
1027 pbdev = s390_pci_find_dev_by_pci(s, PCI_DEVICE(dev));
1028 g_assert(pbdev);
1029 pbdev->pci_unplug_request_processed = true;
1030 qdev_unplug(DEVICE(pbdev), errp);
af9ed379
YMZ
1031 } else if (object_dynamic_cast(OBJECT(dev), TYPE_S390_PCI_DEVICE)) {
1032 pbdev = S390_PCI_DEVICE(dev);
8cba80c3 1033
e0998fe8
DH
1034 /*
1035 * If unplug was initially requested for the zPCI device, we
1036 * first have to redirect to the PCI device, which will in return
1037 * redirect back to us after performing its checks (if the request
1038 * is not blocked, e.g. because it's a PCI bridge).
1039 */
1040 if (pbdev->pdev && !pbdev->pci_unplug_request_processed) {
1041 qdev_unplug(DEVICE(pbdev->pdev), errp);
3549f8c9
DH
1042 return;
1043 }
e0998fe8 1044 pbdev->pci_unplug_request_processed = false;
93d16d81 1045
e0998fe8
DH
1046 switch (pbdev->state) {
1047 case ZPCI_FS_STANDBY:
1048 case ZPCI_FS_RESERVED:
1049 s390_pci_perform_unplug(pbdev);
1050 break;
1051 default:
9f2a46b1
DH
1052 /*
1053 * Allow to send multiple requests, e.g. if the guest crashed
1054 * before releasing the device, we would not be able to send
1055 * another request to the same VM (e.g. fresh OS).
1056 */
1057 pbdev->unplug_requested = true;
e0998fe8
DH
1058 s390_pci_generate_plug_event(HP_EVENT_DECONFIGURE_REQUEST,
1059 pbdev->fh, pbdev->fid);
e0998fe8
DH
1060 }
1061 } else {
1062 g_assert_not_reached();
8cba80c3 1063 }
8cba80c3
FB
1064}
1065
d2f07120
PM
1066static void s390_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
1067 void *opaque)
1068{
1069 S390pciState *s = opaque;
d2f07120
PM
1070 PCIBus *sec_bus = NULL;
1071
1072 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
1073 PCI_HEADER_TYPE_BRIDGE)) {
1074 return;
1075 }
1076
1077 (s->bus_no)++;
d30a7507 1078 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1);
d2f07120
PM
1079 pci_default_write_config(pdev, PCI_SECONDARY_BUS, s->bus_no, 1);
1080 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, s->bus_no, 1);
1081
1082 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
1083 if (!sec_bus) {
1084 return;
1085 }
1086
d30a7507 1087 /* Assign numbers to all child bridges. The last is the highest number. */
d2f07120
PM
1088 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
1089 s390_pci_enumerate_bridge, s);
1090 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, s->bus_no, 1);
1091}
1092
1093static void s390_pcihost_reset(DeviceState *dev)
1094{
1095 S390pciState *s = S390_PCI_HOST_BRIDGE(dev);
1096 PCIBus *bus = s->parent_obj.bus;
2313a88f
DH
1097 S390PCIBusDevice *pbdev, *next;
1098
1099 /* Process all pending unplug requests */
1100 QTAILQ_FOREACH_SAFE(pbdev, &s->zpci_devs, link, next) {
1101 if (pbdev->unplug_requested) {
1102 if (pbdev->summary_ind) {
1103 pci_dereg_irqs(pbdev);
1104 }
1105 if (pbdev->iommu->enabled) {
1106 pci_dereg_ioat(pbdev->iommu);
1107 }
1108 pbdev->state = ZPCI_FS_STANDBY;
1109 s390_pci_perform_unplug(pbdev);
1110 }
1111 }
d2f07120 1112
d30a7507
DH
1113 /*
1114 * When resetting a PCI bridge, the assigned numbers are set to 0. So
1115 * on every system reset, we also have to reassign numbers.
1116 */
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PM
1117 s->bus_no = 0;
1118 pci_for_each_device(bus, pci_bus_num(bus), s390_pci_enumerate_bridge, s);
1119}
1120
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1121static void s390_pcihost_class_init(ObjectClass *klass, void *data)
1122{
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1123 DeviceClass *dc = DEVICE_CLASS(klass);
1124 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
1125
d2f07120 1126 dc->reset = s390_pcihost_reset;
b576d582 1127 dc->realize = s390_pcihost_realize;
6069bcde 1128 hc->pre_plug = s390_pcihost_pre_plug;
fa2a7751 1129 hc->plug = s390_pcihost_plug;
e0998fe8 1130 hc->unplug_request = s390_pcihost_unplug_request;
fa2a7751 1131 hc->unplug = s390_pcihost_unplug;
226419d6 1132 msi_nonbroken = true;
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FB
1133}
1134
1135static const TypeInfo s390_pcihost_info = {
1136 .name = TYPE_S390_PCI_HOST_BRIDGE,
1137 .parent = TYPE_PCI_HOST_BRIDGE,
1138 .instance_size = sizeof(S390pciState),
1139 .class_init = s390_pcihost_class_init,
1140 .interfaces = (InterfaceInfo[]) {
1141 { TYPE_HOTPLUG_HANDLER },
1142 { }
1143 }
1144};
1145
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1146static const TypeInfo s390_pcibus_info = {
1147 .name = TYPE_S390_PCI_BUS,
1148 .parent = TYPE_BUS,
1149 .instance_size = sizeof(S390PCIBus),
1150};
1151
a975a24a 1152static uint16_t s390_pci_generate_uid(S390pciState *s)
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1153{
1154 uint16_t uid = 0;
1155
1156 do {
1157 uid++;
a975a24a 1158 if (!s390_pci_find_dev_by_uid(s, uid)) {
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1159 return uid;
1160 }
1161 } while (uid < ZPCI_MAX_UID);
1162
1163 return UID_UNDEFINED;
1164}
1165
a975a24a 1166static uint32_t s390_pci_generate_fid(S390pciState *s, Error **errp)
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1167{
1168 uint32_t fid = 0;
1169
35b6e94b 1170 do {
a975a24a 1171 if (!s390_pci_find_dev_by_fid(s, fid)) {
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1172 return fid;
1173 }
35b6e94b 1174 } while (fid++ != ZPCI_MAX_FID);
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1175
1176 error_setg(errp, "no free fid could be found");
1177 return 0;
1178}
1179
1180static void s390_pci_device_realize(DeviceState *dev, Error **errp)
1181{
1182 S390PCIBusDevice *zpci = S390_PCI_DEVICE(dev);
a975a24a 1183 S390pciState *s = s390_get_phb();
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1184
1185 if (!zpci->target) {
1186 error_setg(errp, "target must be defined");
1187 return;
1188 }
1189
a975a24a 1190 if (s390_pci_find_dev_by_target(s, zpci->target)) {
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1191 error_setg(errp, "target %s already has an associated zpci device",
1192 zpci->target);
1193 return;
1194 }
1195
1196 if (zpci->uid == UID_UNDEFINED) {
a975a24a 1197 zpci->uid = s390_pci_generate_uid(s);
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1198 if (!zpci->uid) {
1199 error_setg(errp, "no free uid could be found");
1200 return;
1201 }
a975a24a 1202 } else if (s390_pci_find_dev_by_uid(s, zpci->uid)) {
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1203 error_setg(errp, "uid %u already in use", zpci->uid);
1204 return;
1205 }
1206
1207 if (!zpci->fid_defined) {
1208 Error *local_error = NULL;
1209
a975a24a 1210 zpci->fid = s390_pci_generate_fid(s, &local_error);
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1211 if (local_error) {
1212 error_propagate(errp, local_error);
1213 return;
1214 }
a975a24a 1215 } else if (s390_pci_find_dev_by_fid(s, zpci->fid)) {
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1216 error_setg(errp, "fid %u already in use", zpci->fid);
1217 return;
1218 }
1219
1220 zpci->state = ZPCI_FS_RESERVED;
6e92c70c 1221 zpci->fmb.format = ZPCI_FMB_FORMAT;
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1222}
1223
1224static void s390_pci_device_reset(DeviceState *dev)
1225{
1226 S390PCIBusDevice *pbdev = S390_PCI_DEVICE(dev);
1227
1228 switch (pbdev->state) {
1229 case ZPCI_FS_RESERVED:
1230 return;
1231 case ZPCI_FS_STANDBY:
1232 break;
1233 default:
1234 pbdev->fh &= ~FH_MASK_ENABLE;
1235 pbdev->state = ZPCI_FS_DISABLED;
1236 break;
1237 }
1238
1239 if (pbdev->summary_ind) {
1240 pci_dereg_irqs(pbdev);
1241 }
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1242 if (pbdev->iommu->enabled) {
1243 pci_dereg_ioat(pbdev->iommu);
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1244 }
1245
6e92c70c 1246 fmb_timer_free(pbdev);
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1247}
1248
1249static void s390_pci_get_fid(Object *obj, Visitor *v, const char *name,
1250 void *opaque, Error **errp)
1251{
1252 Property *prop = opaque;
1253 uint32_t *ptr = qdev_get_prop_ptr(DEVICE(obj), prop);
1254
1255 visit_type_uint32(v, name, ptr, errp);
1256}
1257
1258static void s390_pci_set_fid(Object *obj, Visitor *v, const char *name,
1259 void *opaque, Error **errp)
1260{
1261 DeviceState *dev = DEVICE(obj);
1262 S390PCIBusDevice *zpci = S390_PCI_DEVICE(obj);
1263 Property *prop = opaque;
1264 uint32_t *ptr = qdev_get_prop_ptr(dev, prop);
1265
1266 if (dev->realized) {
1267 qdev_prop_set_after_realize(dev, name, errp);
1268 return;
1269 }
1270
5af3a056
MA
1271 if (!visit_type_uint32(v, name, ptr, errp)) {
1272 return;
1273 }
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1274 zpci->fid_defined = true;
1275}
1276
1b6b7d10 1277static const PropertyInfo s390_pci_fid_propinfo = {
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1278 .name = "zpci_fid",
1279 .get = s390_pci_get_fid,
1280 .set = s390_pci_set_fid,
1281};
1282
1283#define DEFINE_PROP_S390_PCI_FID(_n, _s, _f) \
1284 DEFINE_PROP(_n, _s, _f, s390_pci_fid_propinfo, uint32_t)
1285
1286static Property s390_pci_device_properties[] = {
1287 DEFINE_PROP_UINT16("uid", S390PCIBusDevice, uid, UID_UNDEFINED),
1288 DEFINE_PROP_S390_PCI_FID("fid", S390PCIBusDevice, fid),
1289 DEFINE_PROP_STRING("target", S390PCIBusDevice, target),
1290 DEFINE_PROP_END_OF_LIST(),
1291};
1292
aede5d5d
CH
1293static const VMStateDescription s390_pci_device_vmstate = {
1294 .name = TYPE_S390_PCI_DEVICE,
1295 /*
1296 * TODO: add state handling here, so migration works at least with
1297 * emulated pci devices on s390x
1298 */
1299 .unmigratable = 1,
1300};
1301
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1302static void s390_pci_device_class_init(ObjectClass *klass, void *data)
1303{
1304 DeviceClass *dc = DEVICE_CLASS(klass);
1305
1306 dc->desc = "zpci device";
bd2aef10 1307 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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1308 dc->reset = s390_pci_device_reset;
1309 dc->bus_type = TYPE_S390_PCI_BUS;
1310 dc->realize = s390_pci_device_realize;
4f67d30b 1311 device_class_set_props(dc, s390_pci_device_properties);
aede5d5d 1312 dc->vmsd = &s390_pci_device_vmstate;
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YMZ
1313}
1314
1315static const TypeInfo s390_pci_device_info = {
1316 .name = TYPE_S390_PCI_DEVICE,
1317 .parent = TYPE_DEVICE,
1318 .instance_size = sizeof(S390PCIBusDevice),
1319 .class_init = s390_pci_device_class_init,
1320};
1321
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1322static TypeInfo s390_pci_iommu_info = {
1323 .name = TYPE_S390_PCI_IOMMU,
1324 .parent = TYPE_OBJECT,
1325 .instance_size = sizeof(S390PCIIOMMU),
1326};
1327
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AK
1328static void s390_iommu_memory_region_class_init(ObjectClass *klass, void *data)
1329{
1330 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
1331
1332 imrc->translate = s390_translate_iommu;
6c5e7402 1333 imrc->replay = s390_pci_iommu_replay;
1221a474
AK
1334}
1335
1336static const TypeInfo s390_iommu_memory_region_info = {
1337 .parent = TYPE_IOMMU_MEMORY_REGION,
1338 .name = TYPE_S390_IOMMU_MEMORY_REGION,
1339 .class_init = s390_iommu_memory_region_class_init,
1340};
1341
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1342static void s390_pci_register_types(void)
1343{
1344 type_register_static(&s390_pcihost_info);
90a0f9af 1345 type_register_static(&s390_pcibus_info);
3e5cfba3 1346 type_register_static(&s390_pci_device_info);
de91ea92 1347 type_register_static(&s390_pci_iommu_info);
1221a474 1348 type_register_static(&s390_iommu_memory_region_info);
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FB
1349}
1350
1351type_init(s390_pci_register_types)