]> git.proxmox.com Git - mirror_qemu.git/blame - hw/scsi/megasas.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
megasas: do not read command more than once from frame
[mirror_qemu.git] / hw / scsi / megasas.c
CommitLineData
e8f943c3
HR		 1/*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
a4ab4792 21#include "qemu/osdep.h"
83c9f4ca
PB		 22#include "hw/hw.h"
23#include "hw/pci/pci.h"
9c17d615 24#include "sysemu/dma.h"
4be74634 25#include "sysemu/block-backend.h"
4522b69c 26#include "hw/pci/msi.h"
83c9f4ca 27#include "hw/pci/msix.h"
1de7afc9 28#include "qemu/iov.h"
0d09e41a
PB		 29#include "hw/scsi/scsi.h"
30#include "block/scsi.h"
e8f943c3 31#include "trace.h"
1108b2f8 32#include "qapi/error.h"
47b43a1f 33#include "mfi.h"
e8f943c3 34
e23d0498
HR		 35#define MEGASAS_VERSION_GEN1 "1.70"
36#define MEGASAS_VERSION_GEN2 "1.80"
e8f943c3
HR		 37#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
38#define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
e23d0498 39#define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
e8f943c3
HR		 40#define MEGASAS_MAX_SGE 128 /* Firmware limit */
41#define MEGASAS_DEFAULT_SGE 80
42#define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
43#define MEGASAS_MAX_ARRAYS 128
44
fb654157 45#define MEGASAS_HBA_SERIAL "QEMU123456"
76b523db
HR		 46#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
47#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
48
e8f943c3
HR		 49#define MEGASAS_FLAG_USE_JBOD 0
50#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
b4b4a57f 51#define MEGASAS_FLAG_USE_QUEUE64 1
e8f943c3
HR		 52#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
53
a97ad268 54static const char *mfi_frame_desc[] = {
e8f943c3
HR		 55 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
56 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
57
58typedef struct MegasasCmd {
59 uint32_t index;
60 uint16_t flags;
61 uint16_t count;
62 uint64_t context;
63
a8170e5e
AK		 64 hwaddr pa;
65 hwaddr pa_size;
50b93533 66 uint32_t dcmd_opcode;
e8f943c3
HR		 67 union mfi_frame *frame;
68 SCSIRequest *req;
69 QEMUSGList qsg;
70 void *iov_buf;
71 size_t iov_size;
72 size_t iov_offset;
73 struct MegasasState *state;
74} MegasasCmd;
75
76typedef struct MegasasState {
52190c1e
AF		 77 /*< private >*/
78 PCIDevice parent_obj;
79 /*< public >*/
80
e8f943c3
HR		 81 MemoryRegion mmio_io;
82 MemoryRegion port_io;
83 MemoryRegion queue_io;
84 uint32_t frame_hi;
85
86 int fw_state;
87 uint32_t fw_sge;
88 uint32_t fw_cmds;
89 uint32_t flags;
90 int fw_luns;
91 int intr_mask;
92 int doorbell;
93 int busy;
e23d0498
HR		 94 int diag;
95 int adp_reset;
b4b4a57f
C		 96 OnOffAuto msi;
97 OnOffAuto msix;
e8f943c3
HR		 98
99 MegasasCmd *event_cmd;
100 int event_locale;
101 int event_class;
102 int event_count;
103 int shutdown_event;
104 int boot_event;
105
76b523db 106 uint64_t sas_addr;
fb654157 107 char *hba_serial;
76b523db 108
e8f943c3
HR		 109 uint64_t reply_queue_pa;
110 void *reply_queue;
111 int reply_queue_len;
112 int reply_queue_head;
113 int reply_queue_tail;
114 uint64_t consumer_pa;
115 uint64_t producer_pa;
116
117 MegasasCmd frames[MEGASAS_MAX_FRAMES];
6df5718b 118 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
e8f943c3
HR		 119 SCSIBus bus;
120} MegasasState;
121
e23d0498
HR		 122typedef struct MegasasBaseClass {
123 PCIDeviceClass parent_class;
124 const char *product_name;
125 const char *product_version;
126 int mmio_bar;
127 int ioport_bar;
128 int osts;
129} MegasasBaseClass;
130
131#define TYPE_MEGASAS_BASE "megasas-base"
132#define TYPE_MEGASAS_GEN1 "megasas"
133#define TYPE_MEGASAS_GEN2 "megasas-gen2"
c79e16ae
PC		 134
135#define MEGASAS(obj) \
e23d0498
HR		 136 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
137
138#define MEGASAS_DEVICE_CLASS(oc) \
139 OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
140#define MEGASAS_DEVICE_GET_CLASS(oc) \
141 OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
c79e16ae 142
e8f943c3
HR		 143#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
144
145static bool megasas_intr_enabled(MegasasState *s)
146{
147 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
148 MEGASAS_INTR_DISABLED_MASK) {
149 return true;
150 }
151 return false;
152}
153
154static bool megasas_use_queue64(MegasasState *s)
155{
156 return s->flags & MEGASAS_MASK_USE_QUEUE64;
157}
158
159static bool megasas_use_msix(MegasasState *s)
160{
b4b4a57f 161 return s->msix != ON_OFF_AUTO_OFF;
e8f943c3
HR		 162}
163
164static bool megasas_is_jbod(MegasasState *s)
165{
166 return s->flags & MEGASAS_MASK_USE_JBOD;
167}
168
16578c6f
PB		 169static void megasas_frame_set_cmd_status(MegasasState *s,
170 unsigned long frame, uint8_t v)
e8f943c3 171{
16578c6f
PB		 172 PCIDevice *pci = &s->parent_obj;
173 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status), v);
e8f943c3
HR		 174}
175
16578c6f
PB		 176static void megasas_frame_set_scsi_status(MegasasState *s,
177 unsigned long frame, uint8_t v)
e8f943c3 178{
16578c6f
PB		 179 PCIDevice *pci = &s->parent_obj;
180 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status), v);
e8f943c3
HR		 181}
182
183/*
184 * Context is considered opaque, but the HBA firmware is running
185 * in little endian mode. So convert it to little endian, too.
186 */
16578c6f
PB		 187static uint64_t megasas_frame_get_context(MegasasState *s,
188 unsigned long frame)
e8f943c3 189{
16578c6f
PB		 190 PCIDevice *pci = &s->parent_obj;
191 return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context));
e8f943c3
HR		 192}
193
194static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
195{
196 return cmd->flags & MFI_FRAME_IEEE_SGL;
197}
198
199static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
200{
201 return cmd->flags & MFI_FRAME_SGL64;
202}
203
204static bool megasas_frame_is_sense64(MegasasCmd *cmd)
205{
206 return cmd->flags & MFI_FRAME_SENSE64;
207}
208
209static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
210 union mfi_sgl *sgl)
211{
212 uint64_t addr;
213
214 if (megasas_frame_is_ieee_sgl(cmd)) {
215 addr = le64_to_cpu(sgl->sg_skinny->addr);
216 } else if (megasas_frame_is_sgl64(cmd)) {
217 addr = le64_to_cpu(sgl->sg64->addr);
218 } else {
219 addr = le32_to_cpu(sgl->sg32->addr);
220 }
221 return addr;
222}
223
224static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
225 union mfi_sgl *sgl)
226{
227 uint32_t len;
228
229 if (megasas_frame_is_ieee_sgl(cmd)) {
230 len = le32_to_cpu(sgl->sg_skinny->len);
231 } else if (megasas_frame_is_sgl64(cmd)) {
232 len = le32_to_cpu(sgl->sg64->len);
233 } else {
234 len = le32_to_cpu(sgl->sg32->len);
235 }
236 return len;
237}
238
239static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
240 union mfi_sgl *sgl)
241{
242 uint8_t *next = (uint8_t *)sgl;
243
244 if (megasas_frame_is_ieee_sgl(cmd)) {
245 next += sizeof(struct mfi_sg_skinny);
246 } else if (megasas_frame_is_sgl64(cmd)) {
247 next += sizeof(struct mfi_sg64);
248 } else {
249 next += sizeof(struct mfi_sg32);
250 }
251
252 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
253 return NULL;
254 }
255 return (union mfi_sgl *)next;
256}
257
258static void megasas_soft_reset(MegasasState *s);
259
260static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
261{
262 int i;
263 int iov_count = 0;
264 size_t iov_size = 0;
265
266 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
267 iov_count = cmd->frame->header.sge_count;
268 if (iov_count > MEGASAS_MAX_SGE) {
269 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
270 MEGASAS_MAX_SGE);
271 return iov_count;
272 }
52190c1e 273 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
e8f943c3
HR		 274 for (i = 0; i < iov_count; i++) {
275 dma_addr_t iov_pa, iov_size_p;
276
277 if (!sgl) {
278 trace_megasas_iovec_sgl_underflow(cmd->index, i);
279 goto unmap;
280 }
281 iov_pa = megasas_sgl_get_addr(cmd, sgl);
282 iov_size_p = megasas_sgl_get_len(cmd, sgl);
283 if (!iov_pa || !iov_size_p) {
284 trace_megasas_iovec_sgl_invalid(cmd->index, i,
285 iov_pa, iov_size_p);
286 goto unmap;
287 }
288 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
289 sgl = megasas_sgl_next(cmd, sgl);
290 iov_size += (size_t)iov_size_p;
291 }
292 if (cmd->iov_size > iov_size) {
293 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
294 } else if (cmd->iov_size < iov_size) {
d17e7448 295 trace_megasas_iovec_underflow(cmd->index, iov_size, cmd->iov_size);
e8f943c3
HR		 296 }
297 cmd->iov_offset = 0;
298 return 0;
299unmap:
300 qemu_sglist_destroy(&cmd->qsg);
301 return iov_count - i;
302}
303
e8f943c3
HR		 304/*
305 * passthrough sense and io sense are at the same offset
306 */
307static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
308 uint8_t sense_len)
309{
1016b239 310 PCIDevice *pcid = PCI_DEVICE(cmd->state);
e8f943c3 311 uint32_t pa_hi = 0, pa_lo;
a8170e5e 312 hwaddr pa;
20fd62d3 313 int frame_sense_len;
e8f943c3 314
20fd62d3
PB		 315 frame_sense_len = cmd->frame->header.sense_len;
316 if (sense_len > frame_sense_len) {
317 sense_len = frame_sense_len;
e8f943c3
HR		 318 }
319 if (sense_len) {
320 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
321 if (megasas_frame_is_sense64(cmd)) {
322 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
323 }
324 pa = ((uint64_t) pa_hi << 32) | pa_lo;
1016b239 325 pci_dma_write(pcid, pa, sense_ptr, sense_len);
e8f943c3
HR		 326 cmd->frame->header.sense_len = sense_len;
327 }
328 return sense_len;
329}
330
331static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
332{
333 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
334 uint8_t sense_len = 18;
335
336 memset(sense_buf, 0, sense_len);
337 sense_buf[0] = 0xf0;
338 sense_buf[2] = sense.key;
339 sense_buf[7] = 10;
340 sense_buf[12] = sense.asc;
341 sense_buf[13] = sense.ascq;
342 megasas_build_sense(cmd, sense_buf, sense_len);
343}
344
345static void megasas_copy_sense(MegasasCmd *cmd)
346{
347 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
348 uint8_t sense_len;
349
350 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
351 SCSI_SENSE_BUF_SIZE);
352 megasas_build_sense(cmd, sense_buf, sense_len);
353}
354
355/*
356 * Format an INQUIRY CDB
357 */
358static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
359{
360 memset(cdb, 0, 6);
361 cdb[0] = INQUIRY;
362 if (pg > 0) {
363 cdb[1] = 0x1;
364 cdb[2] = pg;
365 }
366 cdb[3] = (len >> 8) & 0xff;
367 cdb[4] = (len & 0xff);
368 return len;
369}
370
371/*
372 * Encode lba and len into a READ_16/WRITE_16 CDB
373 */
374static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
375 uint32_t len, bool is_write)
376{
377 memset(cdb, 0x0, 16);
378 if (is_write) {
379 cdb[0] = WRITE_16;
380 } else {
381 cdb[0] = READ_16;
382 }
383 cdb[2] = (lba >> 56) & 0xff;
384 cdb[3] = (lba >> 48) & 0xff;
385 cdb[4] = (lba >> 40) & 0xff;
386 cdb[5] = (lba >> 32) & 0xff;
387 cdb[6] = (lba >> 24) & 0xff;
388 cdb[7] = (lba >> 16) & 0xff;
389 cdb[8] = (lba >> 8) & 0xff;
390 cdb[9] = (lba) & 0xff;
391 cdb[10] = (len >> 24) & 0xff;
392 cdb[11] = (len >> 16) & 0xff;
393 cdb[12] = (len >> 8) & 0xff;
394 cdb[13] = (len) & 0xff;
395}
396
397/*
398 * Utility functions
399 */
400static uint64_t megasas_fw_time(void)
401{
402 struct tm curtime;
e8f943c3
HR		 403
404 qemu_get_timedate(&curtime, 0);
9be38598 405 return ((uint64_t)curtime.tm_sec & 0xff) << 48 |
e8f943c3
HR		 406 ((uint64_t)curtime.tm_min & 0xff) << 40 |
407 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
408 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
409 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
410 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
e8f943c3
HR		 411}
412
76b523db
HR		 413/*
414 * Default disk sata address
415 * 0x1221 is the magic number as
416 * present in real hardware,
417 * so use it here, too.
418 */
419static uint64_t megasas_get_sata_addr(uint16_t id)
e8f943c3 420{
76b523db 421 uint64_t addr = (0x1221ULL << 48);
8ef2eb8d 422 return addr | ((uint64_t)id << 24);
e8f943c3
HR		 423}
424
425/*
426 * Frame handling
427 */
428static int megasas_next_index(MegasasState *s, int index, int limit)
429{
430 index++;
431 if (index == limit) {
432 index = 0;
433 }
434 return index;
435}
436
437static MegasasCmd *megasas_lookup_frame(MegasasState *s,
a8170e5e 438 hwaddr frame)
e8f943c3
HR		 439{
440 MegasasCmd *cmd = NULL;
441 int num = 0, index;
442
443 index = s->reply_queue_head;
444
445 while (num < s->fw_cmds) {
446 if (s->frames[index].pa && s->frames[index].pa == frame) {
447 cmd = &s->frames[index];
448 break;
449 }
450 index = megasas_next_index(s, index, s->fw_cmds);
451 num++;
452 }
453
454 return cmd;
455}
456
6df5718b 457static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
e8f943c3 458{
6df5718b 459 PCIDevice *p = PCI_DEVICE(s);
e8f943c3 460
75f19f8c
PB		 461 if (cmd->pa_size) {
462 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
463 }
6df5718b
HR		 464 cmd->frame = NULL;
465 cmd->pa = 0;
75f19f8c 466 cmd->pa_size = 0;
6df5718b 467 clear_bit(cmd->index, s->frame_map);
e8f943c3
HR		 468}
469
6df5718b
HR		 470/*
471 * This absolutely needs to be locked if
472 * qemu ever goes multithreaded.
473 */
e8f943c3 474static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
a8170e5e 475 hwaddr frame, uint64_t context, int count)
e8f943c3 476{
1016b239 477 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3
HR		 478 MegasasCmd *cmd = NULL;
479 int frame_size = MFI_FRAME_SIZE * 16;
a8170e5e 480 hwaddr frame_size_p = frame_size;
6df5718b 481 unsigned long index;
e8f943c3 482
6df5718b
HR		 483 index = 0;
484 while (index < s->fw_cmds) {
485 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
486 if (!s->frames[index].pa)
487 break;
488 /* Busy frame found */
489 trace_megasas_qf_mapped(index);
490 }
491 if (index >= s->fw_cmds) {
492 /* All frames busy */
493 trace_megasas_qf_busy(frame);
e8f943c3
HR		 494 return NULL;
495 }
6df5718b
HR		 496 cmd = &s->frames[index];
497 set_bit(index, s->frame_map);
498 trace_megasas_qf_new(index, frame);
499
500 cmd->pa = frame;
501 /* Map all possible frames */
502 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
503 if (frame_size_p != frame_size) {
504 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
505 if (cmd->frame) {
506 megasas_unmap_frame(s, cmd);
e8f943c3 507 }
6df5718b
HR		 508 s->event_count++;
509 return NULL;
510 }
511 cmd->pa_size = frame_size_p;
512 cmd->context = context;
513 if (!megasas_use_queue64(s)) {
514 cmd->context &= (uint64_t)0xFFFFFFFF;
e8f943c3
HR		 515 }
516 cmd->count = count;
50b93533 517 cmd->dcmd_opcode = -1;
e8f943c3
HR		 518 s->busy++;
519
aaf2a859 520 if (s->consumer_pa) {
16578c6f 521 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
aaf2a859 522 }
e8f943c3 523 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
aaf2a859 524 s->reply_queue_head, s->reply_queue_tail, s->busy);
e8f943c3
HR		 525
526 return cmd;
527}
528
529static void megasas_complete_frame(MegasasState *s, uint64_t context)
530{
52190c1e 531 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 532 int tail, queue_offset;
533
534 /* Decrement busy count */
535 s->busy--;
e8f943c3
HR		 536 if (s->reply_queue_pa) {
537 /*
538 * Put command on the reply queue.
539 * Context is opaque, but emulation is running in
540 * little endian. So convert it.
541 */
e8f943c3 542 if (megasas_use_queue64(s)) {
7957ee71 543 queue_offset = s->reply_queue_head * sizeof(uint64_t);
16578c6f 544 stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
e8f943c3 545 } else {
7957ee71 546 queue_offset = s->reply_queue_head * sizeof(uint32_t);
16578c6f 547 stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
e8f943c3 548 }
16578c6f 549 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
aaf2a859 550 trace_megasas_qf_complete(context, s->reply_queue_head,
7957ee71 551 s->reply_queue_tail, s->busy);
e8f943c3
HR		 552 }
553
554 if (megasas_intr_enabled(s)) {
7957ee71 555 /* Update reply queue pointer */
16578c6f 556 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
7957ee71
HR		 557 tail = s->reply_queue_head;
558 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
559 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
560 s->busy);
16578c6f 561 stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head);
e8f943c3 562 /* Notify HBA */
7957ee71
HR		 563 if (msix_enabled(pci_dev)) {
564 trace_megasas_msix_raise(0);
565 msix_notify(pci_dev, 0);
566 } else if (msi_enabled(pci_dev)) {
567 trace_megasas_msi_raise(0);
568 msi_notify(pci_dev, 0);
569 } else {
570 s->doorbell++;
571 if (s->doorbell == 1) {
e8f943c3 572 trace_megasas_irq_raise();
9e64f8a3 573 pci_irq_assert(pci_dev);
e8f943c3
HR		 574 }
575 }
576 } else {
577 trace_megasas_qf_complete_noirq(context);
578 }
579}
580
9e55d588
PB		 581static void megasas_complete_command(MegasasCmd *cmd)
582{
583 qemu_sglist_destroy(&cmd->qsg);
584 cmd->iov_size = 0;
585 cmd->iov_offset = 0;
586
587 cmd->req->hba_private = NULL;
588 scsi_req_unref(cmd->req);
589 cmd->req = NULL;
590
591 megasas_unmap_frame(cmd->state, cmd);
592 megasas_complete_frame(cmd->state, cmd->context);
593}
594
e8f943c3
HR		 595static void megasas_reset_frames(MegasasState *s)
596{
597 int i;
598 MegasasCmd *cmd;
599
600 for (i = 0; i < s->fw_cmds; i++) {
601 cmd = &s->frames[i];
602 if (cmd->pa) {
6df5718b 603 megasas_unmap_frame(s, cmd);
e8f943c3
HR		 604 }
605 }
6df5718b 606 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
e8f943c3
HR		 607}
608
609static void megasas_abort_command(MegasasCmd *cmd)
610{
9e55d588
PB		 611 /* Never abort internal commands. */
612 if (cmd->req != NULL) {
e2b06058 613 scsi_req_cancel(cmd->req);
e8f943c3
HR		 614 }
615}
616
617static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
618{
1016b239 619 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3 620 uint32_t pa_hi, pa_lo;
96f8f23a
HR		 621 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
622 struct mfi_init_qinfo *initq = NULL;
e8f943c3
HR		 623 uint32_t flags;
624 int ret = MFI_STAT_OK;
625
96f8f23a
HR		 626 if (s->reply_queue_pa) {
627 trace_megasas_initq_mapped(s->reply_queue_pa);
628 goto out;
629 }
e8f943c3
HR		 630 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
631 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
632 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
633 trace_megasas_init_firmware((uint64_t)iq_pa);
1016b239 634 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
e8f943c3
HR		 635 if (!initq || initq_size != sizeof(*initq)) {
636 trace_megasas_initq_map_failed(cmd->index);
637 s->event_count++;
638 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
639 goto out;
640 }
641 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
642 if (s->reply_queue_len > s->fw_cmds) {
643 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
644 s->event_count++;
645 ret = MFI_STAT_INVALID_PARAMETER;
646 goto out;
647 }
648 pa_lo = le32_to_cpu(initq->rq_addr_lo);
649 pa_hi = le32_to_cpu(initq->rq_addr_hi);
650 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
651 pa_lo = le32_to_cpu(initq->ci_addr_lo);
652 pa_hi = le32_to_cpu(initq->ci_addr_hi);
653 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
654 pa_lo = le32_to_cpu(initq->pi_addr_lo);
655 pa_hi = le32_to_cpu(initq->pi_addr_hi);
656 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
16578c6f 657 s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa);
b60bdd1f 658 s->reply_queue_head %= MEGASAS_MAX_FRAMES;
16578c6f 659 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
b60bdd1f 660 s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
e8f943c3
HR		 661 flags = le32_to_cpu(initq->flags);
662 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
663 s->flags |= MEGASAS_MASK_USE_QUEUE64;
664 }
665 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
666 s->reply_queue_len, s->reply_queue_head,
667 s->reply_queue_tail, flags);
668 megasas_reset_frames(s);
669 s->fw_state = MFI_FWSTATE_OPERATIONAL;
670out:
671 if (initq) {
1016b239 672 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
e8f943c3
HR		 673 }
674 return ret;
675}
676
677static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
678{
679 dma_addr_t iov_pa, iov_size;
d016071c 680 int iov_count;
e8f943c3
HR		 681
682 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
d016071c
PB		 683 iov_count = cmd->frame->header.sge_count;
684 if (!iov_count) {
e8f943c3
HR		 685 trace_megasas_dcmd_zero_sge(cmd->index);
686 cmd->iov_size = 0;
687 return 0;
d016071c
PB		 688 } else if (iov_count > 1) {
689 trace_megasas_dcmd_invalid_sge(cmd->index, iov_count);
e8f943c3 690 cmd->iov_size = 0;
765a7070 691 return -EINVAL;
e8f943c3
HR		 692 }
693 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
694 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
52190c1e 695 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
e8f943c3
HR		 696 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
697 cmd->iov_size = iov_size;
765a7070 698 return 0;
e8f943c3
HR		 699}
700
701static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
702{
703 trace_megasas_finish_dcmd(cmd->index, iov_size);
704
e8f943c3
HR		 705 if (iov_size > cmd->iov_size) {
706 if (megasas_frame_is_ieee_sgl(cmd)) {
707 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
708 } else if (megasas_frame_is_sgl64(cmd)) {
709 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
710 } else {
711 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
712 }
713 }
e8f943c3
HR		 714}
715
716static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
717{
52190c1e 718 PCIDevice *pci_dev = PCI_DEVICE(s);
e23d0498
HR		 719 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
720 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 721 struct mfi_ctrl_info info;
722 size_t dcmd_size = sizeof(info);
723 BusChild *kid;
3f2cd4dd 724 int num_pd_disks = 0;
e8f943c3 725
36fef36b 726 memset(&info, 0x0, dcmd_size);
e8f943c3
HR		 727 if (cmd->iov_size < dcmd_size) {
728 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
729 dcmd_size);
730 return MFI_STAT_INVALID_PARAMETER;
731 }
732
e23d0498
HR		 733 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
734 info.pci.device = cpu_to_le16(pci_class->device_id);
735 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
736 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
e8f943c3 737
76b523db
HR		 738 /*
739 * For some reason the firmware supports
740 * only up to 8 device ports.
741 * Despite supporting a far larger number
742 * of devices for the physical devices.
743 * So just display the first 8 devices
744 * in the device port list, independent
745 * of how many logical devices are actually
746 * present.
747 */
748 info.host.type = MFI_INFO_HOST_PCIE;
e8f943c3 749 info.device.type = MFI_INFO_DEV_SAS3G;
76b523db
HR		 750 info.device.port_count = 8;
751 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 752 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
3f2cd4dd 753 uint16_t pd_id;
76b523db 754
3f2cd4dd
HR		 755 if (num_pd_disks < 8) {
756 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
757 info.device.port_addr[num_pd_disks] =
758 cpu_to_le64(megasas_get_sata_addr(pd_id));
76b523db 759 }
3f2cd4dd 760 num_pd_disks++;
76b523db 761 }
e8f943c3 762
e23d0498 763 memcpy(info.product_name, base_class->product_name, 24);
fb654157 764 snprintf(info.serial_number, 32, "%s", s->hba_serial);
69fbd0ea 765 snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version());
e8f943c3 766 memcpy(info.image_component[0].name, "APP", 3);
e23d0498
HR		 767 snprintf(info.image_component[0].version, 10, "%s-QEMU",
768 base_class->product_version);
5a7733b0
OH		 769 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
770 memcpy(info.image_component[0].build_time, "12:34:56", 8);
e8f943c3 771 info.image_component_count = 1;
52190c1e 772 if (pci_dev->has_rom) {
e8f943c3
HR		 773 uint8_t biosver[32];
774 uint8_t *ptr;
775
52190c1e 776 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
e8f943c3 777 memcpy(biosver, ptr + 0x41, 31);
844864fb 778 biosver[31] = 0;
e8f943c3
HR		 779 memcpy(info.image_component[1].name, "BIOS", 4);
780 memcpy(info.image_component[1].version, biosver,
781 strlen((const char *)biosver));
782 info.image_component_count++;
783 }
784 info.current_fw_time = cpu_to_le32(megasas_fw_time());
785 info.max_arms = 32;
786 info.max_spans = 8;
787 info.max_arrays = MEGASAS_MAX_ARRAYS;
3f2cd4dd 788 info.max_lds = MFI_MAX_LD;
e8f943c3
HR		 789 info.max_cmds = cpu_to_le16(s->fw_cmds);
790 info.max_sg_elements = cpu_to_le16(s->fw_sge);
791 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
3f2cd4dd
HR		 792 if (!megasas_is_jbod(s))
793 info.lds_present = cpu_to_le16(num_pd_disks);
794 info.pd_present = cpu_to_le16(num_pd_disks);
795 info.pd_disks_present = cpu_to_le16(num_pd_disks);
e8f943c3
HR		 796 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
797 MFI_INFO_HW_MEM |
798 MFI_INFO_HW_FLASH);
799 info.memory_size = cpu_to_le16(512);
800 info.nvram_size = cpu_to_le16(32);
801 info.flash_size = cpu_to_le16(16);
802 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
803 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
804 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
805 MFI_INFO_AOPS_MIXED_ARRAY);
806 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
807 MFI_INFO_LDOPS_ACCESS_POLICY |
808 MFI_INFO_LDOPS_IO_POLICY |
809 MFI_INFO_LDOPS_WRITE_POLICY |
810 MFI_INFO_LDOPS_READ_POLICY);
811 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
812 info.stripe_sz_ops.min = 3;
786a4ea8 813 info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
e8f943c3
HR		 814 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
815 info.properties.intr_throttle_cnt = cpu_to_le16(16);
816 info.properties.intr_throttle_timeout = cpu_to_le16(50);
817 info.properties.rebuild_rate = 30;
818 info.properties.patrol_read_rate = 30;
819 info.properties.bgi_rate = 30;
820 info.properties.cc_rate = 30;
821 info.properties.recon_rate = 30;
822 info.properties.cache_flush_interval = 4;
823 info.properties.spinup_drv_cnt = 2;
824 info.properties.spinup_delay = 6;
825 info.properties.ecc_bucket_size = 15;
826 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
827 info.properties.expose_encl_devices = 1;
828 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
829 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
830 MFI_INFO_PDOPS_FORCE_OFFLINE);
831 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
832 MFI_INFO_PDMIX_SATA |
833 MFI_INFO_PDMIX_LD);
834
835 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
836 return MFI_STAT_OK;
837}
838
839static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
840{
841 struct mfi_defaults info;
842 size_t dcmd_size = sizeof(struct mfi_defaults);
843
844 memset(&info, 0x0, dcmd_size);
845 if (cmd->iov_size < dcmd_size) {
846 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
847 dcmd_size);
848 return MFI_STAT_INVALID_PARAMETER;
849 }
850
76b523db 851 info.sas_addr = cpu_to_le64(s->sas_addr);
e8f943c3
HR		 852 info.stripe_size = 3;
853 info.flush_time = 4;
854 info.background_rate = 30;
855 info.allow_mix_in_enclosure = 1;
856 info.allow_mix_in_ld = 1;
857 info.direct_pd_mapping = 1;
858 /* Enable for BIOS support */
859 info.bios_enumerate_lds = 1;
860 info.disable_ctrl_r = 1;
861 info.expose_enclosure_devices = 1;
862 info.disable_preboot_cli = 1;
863 info.cluster_disable = 1;
864
865 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
866 return MFI_STAT_OK;
867}
868
869static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
870{
871 struct mfi_bios_data info;
872 size_t dcmd_size = sizeof(info);
873
874 memset(&info, 0x0, dcmd_size);
875 if (cmd->iov_size < dcmd_size) {
876 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
877 dcmd_size);
878 return MFI_STAT_INVALID_PARAMETER;
879 }
880 info.continue_on_error = 1;
881 info.verbose = 1;
882 if (megasas_is_jbod(s)) {
883 info.expose_all_drives = 1;
884 }
885
886 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
887 return MFI_STAT_OK;
888}
889
890static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
891{
892 uint64_t fw_time;
893 size_t dcmd_size = sizeof(fw_time);
894
895 fw_time = cpu_to_le64(megasas_fw_time());
896
897 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
898 return MFI_STAT_OK;
899}
900
901static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
902{
903 uint64_t fw_time;
904
905 /* This is a dummy; setting of firmware time is not allowed */
906 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
907
908 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
909 fw_time = cpu_to_le64(megasas_fw_time());
910 return MFI_STAT_OK;
911}
912
913static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
914{
915 struct mfi_evt_log_state info;
916 size_t dcmd_size = sizeof(info);
917
918 memset(&info, 0, dcmd_size);
919
920 info.newest_seq_num = cpu_to_le32(s->event_count);
921 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
922 info.boot_seq_num = cpu_to_le32(s->boot_event);
923
924 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
925 return MFI_STAT_OK;
926}
927
928static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
929{
930 union mfi_evt event;
931
932 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
933 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
934 sizeof(struct mfi_evt_detail));
935 return MFI_STAT_INVALID_PARAMETER;
936 }
937 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
938 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
939 s->event_locale = event.members.locale;
940 s->event_class = event.members.class;
941 s->event_cmd = cmd;
942 /* Decrease busy count; event frame doesn't count here */
943 s->busy--;
944 cmd->iov_size = sizeof(struct mfi_evt_detail);
945 return MFI_STAT_INVALID_STATUS;
946}
947
948static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
949{
950 struct mfi_pd_list info;
951 size_t dcmd_size = sizeof(info);
952 BusChild *kid;
953 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
e8f943c3
HR		 954
955 memset(&info, 0, dcmd_size);
956 offset = 8;
957 dcmd_limit = offset + sizeof(struct mfi_pd_address);
958 if (cmd->iov_size < dcmd_limit) {
959 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
960 dcmd_limit);
961 return MFI_STAT_INVALID_PARAMETER;
962 }
963
964 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
3f2cd4dd
HR		 965 if (max_pd_disks > MFI_MAX_SYS_PDS) {
966 max_pd_disks = MFI_MAX_SYS_PDS;
e8f943c3 967 }
e8f943c3 968 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 969 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
3f2cd4dd
HR		 970 uint16_t pd_id;
971
972 if (num_pd_disks >= max_pd_disks)
973 break;
e8f943c3 974
3f2cd4dd
HR		 975 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
976 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
e8f943c3
HR		 977 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
978 info.addr[num_pd_disks].encl_index = 0;
3f2cd4dd 979 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
e8f943c3
HR		 980 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
981 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
982 info.addr[num_pd_disks].sas_addr[0] =
3f2cd4dd 983 cpu_to_le64(megasas_get_sata_addr(pd_id));
e8f943c3
HR		 984 num_pd_disks++;
985 offset += sizeof(struct mfi_pd_address);
986 }
987 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
988 max_pd_disks, offset);
989
990 info.size = cpu_to_le32(offset);
991 info.count = cpu_to_le32(num_pd_disks);
992
993 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
994 return MFI_STAT_OK;
995}
996
997static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
998{
999 uint16_t flags;
1000
1001 /* mbox0 contains flags */
1002 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1003 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
1004 if (flags == MR_PD_QUERY_TYPE_ALL ||
1005 megasas_is_jbod(s)) {
1006 return megasas_dcmd_pd_get_list(s, cmd);
1007 }
1008
1009 return MFI_STAT_OK;
1010}
1011
1012static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1013 MegasasCmd *cmd)
1014{
1015 struct mfi_pd_info *info = cmd->iov_buf;
1016 size_t dcmd_size = sizeof(struct mfi_pd_info);
e8f943c3 1017 uint64_t pd_size;
3f2cd4dd 1018 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
e8f943c3
HR		 1019 uint8_t cmdbuf[6];
1020 SCSIRequest *req;
1021 size_t len, resid;
1022
1023 if (!cmd->iov_buf) {
0bd0adbe 1024 cmd->iov_buf = g_malloc0(dcmd_size);
e8f943c3
HR		 1025 info = cmd->iov_buf;
1026 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1027 info->vpd_page83[0] = 0x7f;
1028 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1029 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1030 if (!req) {
1031 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1032 "PD get info std inquiry");
1033 g_free(cmd->iov_buf);
1034 cmd->iov_buf = NULL;
1035 return MFI_STAT_FLASH_ALLOC_FAIL;
1036 }
1037 trace_megasas_dcmd_internal_submit(cmd->index,
1038 "PD get info std inquiry", lun);
1039 len = scsi_req_enqueue(req);
1040 if (len > 0) {
1041 cmd->iov_size = len;
1042 scsi_req_continue(req);
1043 }
1044 return MFI_STAT_INVALID_STATUS;
1045 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1046 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1047 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1048 if (!req) {
1049 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1050 "PD get info vpd inquiry");
1051 return MFI_STAT_FLASH_ALLOC_FAIL;
1052 }
1053 trace_megasas_dcmd_internal_submit(cmd->index,
1054 "PD get info vpd inquiry", lun);
1055 len = scsi_req_enqueue(req);
1056 if (len > 0) {
1057 cmd->iov_size = len;
1058 scsi_req_continue(req);
1059 }
1060 return MFI_STAT_INVALID_STATUS;
1061 }
1062 /* Finished, set FW state */
1063 if ((info->inquiry_data[0] >> 5) == 0) {
1064 if (megasas_is_jbod(cmd->state)) {
1065 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1066 } else {
1067 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1068 }
1069 } else {
1070 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1071 }
1072
3f2cd4dd 1073 info->ref.v.device_id = cpu_to_le16(pd_id);
e8f943c3
HR		 1074 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1075 MFI_PD_DDF_TYPE_INTF_SAS);
4be74634 1076 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1077 info->raw_size = cpu_to_le64(pd_size);
1078 info->non_coerced_size = cpu_to_le64(pd_size);
1079 info->coerced_size = cpu_to_le64(pd_size);
1080 info->encl_device_id = 0xFFFF;
1081 info->slot_number = (sdev->id & 0xFF);
1082 info->path_info.count = 1;
1083 info->path_info.sas_addr[0] =
3f2cd4dd 1084 cpu_to_le64(megasas_get_sata_addr(pd_id));
e8f943c3
HR		 1085 info->connected_port_bitmap = 0x1;
1086 info->device_speed = 1;
1087 info->link_speed = 1;
1088 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1089 g_free(cmd->iov_buf);
1090 cmd->iov_size = dcmd_size - resid;
1091 cmd->iov_buf = NULL;
1092 return MFI_STAT_OK;
1093}
1094
1095static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1096{
1097 size_t dcmd_size = sizeof(struct mfi_pd_info);
1098 uint16_t pd_id;
3f2cd4dd 1099 uint8_t target_id, lun_id;
e8f943c3
HR		 1100 SCSIDevice *sdev = NULL;
1101 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1102
1103 if (cmd->iov_size < dcmd_size) {
1104 return MFI_STAT_INVALID_PARAMETER;
1105 }
1106
1107 /* mbox0 has the ID */
1108 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
3f2cd4dd
HR		 1109 target_id = (pd_id >> 8) & 0xFF;
1110 lun_id = pd_id & 0xFF;
1111 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
e8f943c3
HR		 1112 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1113
1114 if (sdev) {
1115 /* Submit inquiry */
1116 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1117 }
1118
1119 return retval;
1120}
1121
1122static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1123{
1124 struct mfi_ld_list info;
1125 size_t dcmd_size = sizeof(info), resid;
3f2cd4dd 1126 uint32_t num_ld_disks = 0, max_ld_disks;
e8f943c3
HR		 1127 uint64_t ld_size;
1128 BusChild *kid;
1129
1130 memset(&info, 0, dcmd_size);
e74a4315 1131 if (cmd->iov_size > dcmd_size) {
e8f943c3
HR		 1132 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1133 dcmd_size);
1134 return MFI_STAT_INVALID_PARAMETER;
1135 }
1136
3f2cd4dd 1137 max_ld_disks = (cmd->iov_size - 8) / 16;
e8f943c3
HR		 1138 if (megasas_is_jbod(s)) {
1139 max_ld_disks = 0;
1140 }
3f2cd4dd
HR		 1141 if (max_ld_disks > MFI_MAX_LD) {
1142 max_ld_disks = MFI_MAX_LD;
1143 }
e8f943c3 1144 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 1145 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
e8f943c3
HR		 1146
1147 if (num_ld_disks >= max_ld_disks) {
1148 break;
1149 }
1150 /* Logical device size is in blocks */
4be74634 1151 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1152 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1153 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1154 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1155 num_ld_disks++;
1156 }
1157 info.ld_count = cpu_to_le32(num_ld_disks);
1158 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1159
1160 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1161 cmd->iov_size = dcmd_size - resid;
1162 return MFI_STAT_OK;
1163}
1164
34bb4d02
HR		 1165static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1166{
1167 uint16_t flags;
d97ae368
HR		 1168 struct mfi_ld_targetid_list info;
1169 size_t dcmd_size = sizeof(info), resid;
1170 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1171 BusChild *kid;
34bb4d02
HR		 1172
1173 /* mbox0 contains flags */
1174 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1175 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
d97ae368
HR		 1176 if (flags != MR_LD_QUERY_TYPE_ALL &&
1177 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1178 max_ld_disks = 0;
1179 }
1180
1181 memset(&info, 0, dcmd_size);
1182 if (cmd->iov_size < 12) {
1183 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1184 dcmd_size);
1185 return MFI_STAT_INVALID_PARAMETER;
1186 }
1187 dcmd_size = sizeof(uint32_t) * 2 + 3;
3f2cd4dd 1188 max_ld_disks = cmd->iov_size - dcmd_size;
d97ae368
HR		 1189 if (megasas_is_jbod(s)) {
1190 max_ld_disks = 0;
34bb4d02 1191 }
3f2cd4dd
HR		 1192 if (max_ld_disks > MFI_MAX_LD) {
1193 max_ld_disks = MFI_MAX_LD;
1194 }
d97ae368 1195 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 1196 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
34bb4d02 1197
d97ae368
HR		 1198 if (num_ld_disks >= max_ld_disks) {
1199 break;
1200 }
1201 info.targetid[num_ld_disks] = sdev->lun;
1202 num_ld_disks++;
1203 dcmd_size++;
1204 }
1205 info.ld_count = cpu_to_le32(num_ld_disks);
1206 info.size = dcmd_size;
1207 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1208
1209 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1210 cmd->iov_size = dcmd_size - resid;
34bb4d02
HR		 1211 return MFI_STAT_OK;
1212}
1213
e8f943c3
HR		 1214static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1215 MegasasCmd *cmd)
1216{
1217 struct mfi_ld_info *info = cmd->iov_buf;
1218 size_t dcmd_size = sizeof(struct mfi_ld_info);
1219 uint8_t cdb[6];
1220 SCSIRequest *req;
1221 ssize_t len, resid;
3f2cd4dd 1222 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
e8f943c3
HR		 1223 uint64_t ld_size;
1224
1225 if (!cmd->iov_buf) {
0bd0adbe 1226 cmd->iov_buf = g_malloc0(dcmd_size);
e8f943c3
HR		 1227 info = cmd->iov_buf;
1228 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1229 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1230 if (!req) {
1231 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1232 "LD get info vpd inquiry");
1233 g_free(cmd->iov_buf);
1234 cmd->iov_buf = NULL;
1235 return MFI_STAT_FLASH_ALLOC_FAIL;
1236 }
1237 trace_megasas_dcmd_internal_submit(cmd->index,
1238 "LD get info vpd inquiry", lun);
1239 len = scsi_req_enqueue(req);
1240 if (len > 0) {
1241 cmd->iov_size = len;
1242 scsi_req_continue(req);
1243 }
1244 return MFI_STAT_INVALID_STATUS;
1245 }
1246
1247 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1248 info->ld_config.properties.ld.v.target_id = lun;
1249 info->ld_config.params.stripe_size = 3;
1250 info->ld_config.params.num_drives = 1;
1251 info->ld_config.params.is_consistent = 1;
1252 /* Logical device size is in blocks */
4be74634 1253 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1254 info->size = cpu_to_le64(ld_size);
1255 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1256 info->ld_config.span[0].start_block = 0;
1257 info->ld_config.span[0].num_blocks = info->size;
1258 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1259
1260 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1261 g_free(cmd->iov_buf);
1262 cmd->iov_size = dcmd_size - resid;
1263 cmd->iov_buf = NULL;
1264 return MFI_STAT_OK;
1265}
1266
1267static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1268{
1269 struct mfi_ld_info info;
1270 size_t dcmd_size = sizeof(info);
1271 uint16_t ld_id;
1272 uint32_t max_ld_disks = s->fw_luns;
1273 SCSIDevice *sdev = NULL;
1274 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1275
1276 if (cmd->iov_size < dcmd_size) {
1277 return MFI_STAT_INVALID_PARAMETER;
1278 }
1279
1280 /* mbox0 has the ID */
1281 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1282 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1283
1284 if (megasas_is_jbod(s)) {
1285 return MFI_STAT_DEVICE_NOT_FOUND;
1286 }
1287
1288 if (ld_id < max_ld_disks) {
1289 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1290 }
1291
1292 if (sdev) {
1293 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1294 }
1295
1296 return retval;
1297}
1298
1299static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1300{
d37af740 1301 uint8_t data[4096] = { 0 };
e8f943c3
HR		 1302 struct mfi_config_data *info;
1303 int num_pd_disks = 0, array_offset, ld_offset;
1304 BusChild *kid;
1305
1306 if (cmd->iov_size > 4096) {
1307 return MFI_STAT_INVALID_PARAMETER;
1308 }
1309
1310 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1311 num_pd_disks++;
1312 }
1313 info = (struct mfi_config_data *)&data;
1314 /*
1315 * Array mapping:
1316 * - One array per SCSI device
1317 * - One logical drive per SCSI device
1318 * spanning the entire device
1319 */
1320 info->array_count = num_pd_disks;
1321 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1322 info->log_drv_count = num_pd_disks;
1323 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1324 info->spares_count = 0;
1325 info->spares_size = sizeof(struct mfi_spare);
1326 info->size = sizeof(struct mfi_config_data) + info->array_size +
1327 info->log_drv_size;
1328 if (info->size > 4096) {
1329 return MFI_STAT_INVALID_PARAMETER;
1330 }
1331
1332 array_offset = sizeof(struct mfi_config_data);
1333 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1334
1335 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 1336 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
3f2cd4dd 1337 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
e8f943c3
HR		 1338 struct mfi_array *array;
1339 struct mfi_ld_config *ld;
1340 uint64_t pd_size;
1341 int i;
1342
1343 array = (struct mfi_array *)(data + array_offset);
4be74634 1344 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1345 array->size = cpu_to_le64(pd_size);
1346 array->num_drives = 1;
1347 array->array_ref = cpu_to_le16(sdev_id);
1348 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1349 array->pd[0].ref.v.seq_num = 0;
1350 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1351 array->pd[0].encl.pd = 0xFF;
1352 array->pd[0].encl.slot = (sdev->id & 0xFF);
1353 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1354 array->pd[i].ref.v.device_id = 0xFFFF;
1355 array->pd[i].ref.v.seq_num = 0;
1356 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1357 array->pd[i].encl.pd = 0xFF;
1358 array->pd[i].encl.slot = 0xFF;
1359 }
1360 array_offset += sizeof(struct mfi_array);
1361 ld = (struct mfi_ld_config *)(data + ld_offset);
1362 memset(ld, 0, sizeof(struct mfi_ld_config));
3f2cd4dd 1363 ld->properties.ld.v.target_id = sdev->id;
e8f943c3
HR		 1364 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1365 MR_LD_CACHE_READ_ADAPTIVE;
1366 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1367 MR_LD_CACHE_READ_ADAPTIVE;
1368 ld->params.state = MFI_LD_STATE_OPTIMAL;
1369 ld->params.stripe_size = 3;
1370 ld->params.num_drives = 1;
1371 ld->params.span_depth = 1;
1372 ld->params.is_consistent = 1;
1373 ld->span[0].start_block = 0;
1374 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1375 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1376 ld_offset += sizeof(struct mfi_ld_config);
1377 }
1378
1379 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1380 return MFI_STAT_OK;
1381}
1382
1383static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1384{
1385 struct mfi_ctrl_props info;
1386 size_t dcmd_size = sizeof(info);
1387
1388 memset(&info, 0x0, dcmd_size);
1389 if (cmd->iov_size < dcmd_size) {
1390 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1391 dcmd_size);
1392 return MFI_STAT_INVALID_PARAMETER;
1393 }
1394 info.pred_fail_poll_interval = cpu_to_le16(300);
1395 info.intr_throttle_cnt = cpu_to_le16(16);
1396 info.intr_throttle_timeout = cpu_to_le16(50);
1397 info.rebuild_rate = 30;
1398 info.patrol_read_rate = 30;
1399 info.bgi_rate = 30;
1400 info.cc_rate = 30;
1401 info.recon_rate = 30;
1402 info.cache_flush_interval = 4;
1403 info.spinup_drv_cnt = 2;
1404 info.spinup_delay = 6;
1405 info.ecc_bucket_size = 15;
1406 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1407 info.expose_encl_devices = 1;
1408
1409 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1410 return MFI_STAT_OK;
1411}
1412
1413static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1414{
4be74634 1415 blk_drain_all();
e8f943c3
HR		 1416 return MFI_STAT_OK;
1417}
1418
1419static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1420{
1421 s->fw_state = MFI_FWSTATE_READY;
1422 return MFI_STAT_OK;
1423}
1424
200b6966 1425/* Some implementations use CLUSTER RESET LD to simulate a device reset */
e8f943c3
HR		 1426static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1427{
200b6966
HR		 1428 uint16_t target_id;
1429 int i;
1430
1431 /* mbox0 contains the device index */
1432 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1433 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1434 for (i = 0; i < s->fw_cmds; i++) {
1435 MegasasCmd *tmp_cmd = &s->frames[i];
1436 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1437 SCSIDevice *d = tmp_cmd->req->dev;
1438 qdev_reset_all(&d->qdev);
1439 }
1440 }
1441 return MFI_STAT_OK;
e8f943c3
HR		 1442}
1443
1444static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1445{
10d6530c
HR		 1446 struct mfi_ctrl_props info;
1447 size_t dcmd_size = sizeof(info);
1448
1449 if (cmd->iov_size < dcmd_size) {
1450 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1451 dcmd_size);
1452 return MFI_STAT_INVALID_PARAMETER;
1453 }
1b858980 1454 dma_buf_write((uint8_t *)&info, dcmd_size, &cmd->qsg);
10d6530c 1455 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
e8f943c3
HR		 1456 return MFI_STAT_OK;
1457}
1458
1459static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1460{
1461 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1462 return MFI_STAT_OK;
1463}
1464
1465static const struct dcmd_cmd_tbl_t {
1466 int opcode;
1467 const char *desc;
1468 int (*func)(MegasasState *s, MegasasCmd *cmd);
1469} dcmd_cmd_tbl[] = {
1470 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1471 megasas_dcmd_dummy },
1472 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1473 megasas_ctrl_get_info },
1474 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1475 megasas_dcmd_get_properties },
1476 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1477 megasas_dcmd_set_properties },
1478 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1479 megasas_dcmd_dummy },
1480 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1481 megasas_dcmd_dummy },
1482 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1483 megasas_dcmd_dummy },
1484 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1485 megasas_dcmd_dummy },
1486 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1487 megasas_dcmd_dummy },
1488 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1489 megasas_event_info },
1490 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1491 megasas_dcmd_dummy },
1492 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1493 megasas_event_wait },
1494 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1495 megasas_ctrl_shutdown },
1496 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1497 megasas_dcmd_dummy },
1498 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1499 megasas_dcmd_get_fw_time },
1500 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1501 megasas_dcmd_set_fw_time },
1502 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1503 megasas_dcmd_get_bios_info },
1504 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1505 megasas_dcmd_dummy },
1506 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1507 megasas_mfc_get_defaults },
1508 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1509 megasas_dcmd_dummy },
1510 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1511 megasas_cache_flush },
1512 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1513 megasas_dcmd_pd_get_list },
1514 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1515 megasas_dcmd_pd_list_query },
1516 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1517 megasas_dcmd_pd_get_info },
1518 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1519 megasas_dcmd_dummy },
1520 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1521 megasas_dcmd_dummy },
1522 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1523 megasas_dcmd_dummy },
1524 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1525 megasas_dcmd_dummy },
1526 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1527 megasas_dcmd_ld_get_list},
34bb4d02
HR		 1528 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1529 megasas_dcmd_ld_list_query },
e8f943c3
HR		 1530 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1531 megasas_dcmd_ld_get_info },
1532 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1533 megasas_dcmd_dummy },
1534 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1535 megasas_dcmd_dummy },
1536 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1537 megasas_dcmd_dummy },
1538 { MFI_DCMD_CFG_READ, "CFG_READ",
1539 megasas_dcmd_cfg_read },
1540 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1541 megasas_dcmd_dummy },
1542 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1543 megasas_dcmd_dummy },
1544 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1545 megasas_dcmd_dummy },
1546 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1547 megasas_dcmd_dummy },
1548 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1549 megasas_dcmd_dummy },
1550 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1551 megasas_dcmd_dummy },
1552 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1553 megasas_dcmd_dummy },
1554 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1555 megasas_dcmd_dummy },
1556 { MFI_DCMD_CLUSTER, "CLUSTER",
1557 megasas_dcmd_dummy },
1558 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1559 megasas_dcmd_dummy },
1560 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1561 megasas_cluster_reset_ld },
1562 { -1, NULL, NULL }
1563};
1564
1565static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1566{
e8f943c3 1567 int retval = 0;
765a7070 1568 size_t len;
e8f943c3
HR		 1569 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1570
50b93533
PB		 1571 cmd->dcmd_opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1572 trace_megasas_handle_dcmd(cmd->index, cmd->dcmd_opcode);
765a7070 1573 if (megasas_map_dcmd(s, cmd) < 0) {
e8f943c3
HR		 1574 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1575 }
50b93533 1576 while (cmdptr->opcode != -1 && cmdptr->opcode != cmd->dcmd_opcode) {
e8f943c3
HR		 1577 cmdptr++;
1578 }
765a7070 1579 len = cmd->iov_size;
e8f943c3 1580 if (cmdptr->opcode == -1) {
50b93533 1581 trace_megasas_dcmd_unhandled(cmd->index, cmd->dcmd_opcode, len);
e8f943c3
HR		 1582 retval = megasas_dcmd_dummy(s, cmd);
1583 } else {
1584 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1585 retval = cmdptr->func(s, cmd);
1586 }
1587 if (retval != MFI_STAT_INVALID_STATUS) {
1588 megasas_finish_dcmd(cmd, len);
1589 }
1590 return retval;
1591}
1592
1593static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
578fb500 1594 SCSIRequest *req, size_t resid)
e8f943c3 1595{
e8f943c3
HR		 1596 int retval = MFI_STAT_OK;
1597 int lun = req->lun;
1598
50b93533 1599 trace_megasas_dcmd_internal_finish(cmd->index, cmd->dcmd_opcode, lun);
578fb500 1600 cmd->iov_size -= resid;
50b93533 1601 switch (cmd->dcmd_opcode) {
e8f943c3
HR		 1602 case MFI_DCMD_PD_GET_INFO:
1603 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1604 break;
1605 case MFI_DCMD_LD_GET_INFO:
1606 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1607 break;
1608 default:
50b93533 1609 trace_megasas_dcmd_internal_invalid(cmd->index, cmd->dcmd_opcode);
e8f943c3
HR		 1610 retval = MFI_STAT_INVALID_DCMD;
1611 break;
1612 }
1613 if (retval != MFI_STAT_INVALID_STATUS) {
1614 megasas_finish_dcmd(cmd, cmd->iov_size);
1615 }
1616 return retval;
1617}
1618
1619static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1620{
1621 int len;
1622
1623 len = scsi_req_enqueue(cmd->req);
1624 if (len < 0) {
1625 len = -len;
1626 }
1627 if (len > 0) {
1628 if (len > cmd->iov_size) {
1629 if (is_write) {
1630 trace_megasas_iov_write_overflow(cmd->index, len,
1631 cmd->iov_size);
1632 } else {
1633 trace_megasas_iov_read_overflow(cmd->index, len,
1634 cmd->iov_size);
1635 }
1636 }
1637 if (len < cmd->iov_size) {
1638 if (is_write) {
1639 trace_megasas_iov_write_underflow(cmd->index, len,
1640 cmd->iov_size);
1641 } else {
1642 trace_megasas_iov_read_underflow(cmd->index, len,
1643 cmd->iov_size);
1644 }
1645 cmd->iov_size = len;
1646 }
1647 scsi_req_continue(cmd->req);
1648 }
1649 return len;
1650}
1651
1652static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
578fb500 1653 int frame_cmd)
e8f943c3
HR		 1654{
1655 uint8_t *cdb;
e8f943c3
HR		 1656 bool is_write;
1657 struct SCSIDevice *sdev = NULL;
578fb500 1658 bool is_logical = (frame_cmd == MFI_CMD_LD_SCSI_IO);
e8f943c3
HR		 1659
1660 cdb = cmd->frame->pass.cdb;
1661
3f2cd4dd
HR		 1662 if (is_logical) {
1663 if (cmd->frame->header.target_id >= MFI_MAX_LD ||
1664 cmd->frame->header.lun_id != 0) {
1665 trace_megasas_scsi_target_not_present(
578fb500 1666 mfi_frame_desc[frame_cmd], is_logical,
3f2cd4dd
HR		 1667 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1668 return MFI_STAT_DEVICE_NOT_FOUND;
1669 }
e8f943c3 1670 }
3f2cd4dd
HR		 1671 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1672 cmd->frame->header.lun_id);
1673
e8f943c3
HR		 1674 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1675 trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd],
578fb500
PB		 1676 trace_megasas_handle_scsi(mfi_frame_desc[frame_cmd], is_logical,
1677 cmd->frame->header.target_id,
e8f943c3
HR		 1678 cmd->frame->header.lun_id, sdev, cmd->iov_size);
1679
1680 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1681 trace_megasas_scsi_target_not_present(
578fb500 1682 mfi_frame_desc[frame_cmd], is_logical,
e8f943c3
HR		 1683 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1684 return MFI_STAT_DEVICE_NOT_FOUND;
1685 }
1686
1687 if (cmd->frame->header.cdb_len > 16) {
1688 trace_megasas_scsi_invalid_cdb_len(
578fb500 1689 mfi_frame_desc[frame_cmd], is_logical,
e8f943c3
HR		 1690 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1691 cmd->frame->header.cdb_len);
1692 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1693 cmd->frame->header.scsi_status = CHECK_CONDITION;
1694 s->event_count++;
1695 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1696 }
1697
1698 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1699 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1700 cmd->frame->header.scsi_status = CHECK_CONDITION;
1701 s->event_count++;
1702 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1703 }
1704
1705 cmd->req = scsi_req_new(sdev, cmd->index,
1706 cmd->frame->header.lun_id, cdb, cmd);
1707 if (!cmd->req) {
1708 trace_megasas_scsi_req_alloc_failed(
578fb500 1709 mfi_frame_desc[frame_cmd],
e8f943c3
HR		 1710 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1711 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1712 cmd->frame->header.scsi_status = BUSY;
1713 s->event_count++;
1714 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1715 }
1716
1717 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
aaf2a859 1718 if (cmd->iov_size) {
e8f943c3 1719 if (is_write) {
aaf2a859 1720 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
e8f943c3 1721 } else {
aaf2a859 1722 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
e8f943c3
HR		 1723 }
1724 } else {
1725 trace_megasas_scsi_nodata(cmd->index);
1726 }
aaf2a859 1727 megasas_enqueue_req(cmd, is_write);
e8f943c3
HR		 1728 return MFI_STAT_INVALID_STATUS;
1729}
1730
578fb500 1731static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd, int frame_cmd)
e8f943c3
HR		 1732{
1733 uint32_t lba_count, lba_start_hi, lba_start_lo;
1734 uint64_t lba_start;
578fb500 1735 bool is_write = (frame_cmd == MFI_CMD_LD_WRITE);
e8f943c3
HR		 1736 uint8_t cdb[16];
1737 int len;
1738 struct SCSIDevice *sdev = NULL;
1739
1740 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1741 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1742 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1743 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1744
3f2cd4dd
HR		 1745 if (cmd->frame->header.target_id < MFI_MAX_LD &&
1746 cmd->frame->header.lun_id == 0) {
e8f943c3
HR		 1747 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1748 cmd->frame->header.lun_id);
1749 }
1750
1751 trace_megasas_handle_io(cmd->index,
578fb500 1752 mfi_frame_desc[frame_cmd],
e8f943c3
HR		 1753 cmd->frame->header.target_id,
1754 cmd->frame->header.lun_id,
1755 (unsigned long)lba_start, (unsigned long)lba_count);
1756 if (!sdev) {
1757 trace_megasas_io_target_not_present(cmd->index,
578fb500 1758 mfi_frame_desc[frame_cmd],
e8f943c3
HR		 1759 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1760 return MFI_STAT_DEVICE_NOT_FOUND;
1761 }
1762
1763 if (cmd->frame->header.cdb_len > 16) {
1764 trace_megasas_scsi_invalid_cdb_len(
578fb500 1765 mfi_frame_desc[frame_cmd], 1,
e8f943c3
HR		 1766 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1767 cmd->frame->header.cdb_len);
1768 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1769 cmd->frame->header.scsi_status = CHECK_CONDITION;
1770 s->event_count++;
1771 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1772 }
1773
1774 cmd->iov_size = lba_count * sdev->blocksize;
1775 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1776 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1777 cmd->frame->header.scsi_status = CHECK_CONDITION;
1778 s->event_count++;
1779 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1780 }
1781
1782 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1783 cmd->req = scsi_req_new(sdev, cmd->index,
1784 cmd->frame->header.lun_id, cdb, cmd);
1785 if (!cmd->req) {
1786 trace_megasas_scsi_req_alloc_failed(
578fb500 1787 mfi_frame_desc[frame_cmd],
e8f943c3
HR		 1788 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1789 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1790 cmd->frame->header.scsi_status = BUSY;
1791 s->event_count++;
1792 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1793 }
1794 len = megasas_enqueue_req(cmd, is_write);
1795 if (len > 0) {
1796 if (is_write) {
1797 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1798 } else {
1799 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1800 }
1801 }
1802 return MFI_STAT_INVALID_STATUS;
1803}
1804
e8f943c3
HR		 1805static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1806{
1807 MegasasCmd *cmd = req->hba_private;
1808
578fb500 1809 if (cmd->dcmd_opcode != -1) {
e8f943c3
HR		 1810 return NULL;
1811 } else {
1812 return &cmd->qsg;
1813 }
1814}
1815
1816static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1817{
1818 MegasasCmd *cmd = req->hba_private;
1819 uint8_t *buf;
e8f943c3
HR		 1820
1821 trace_megasas_io_complete(cmd->index, len);
1822
578fb500 1823 if (cmd->dcmd_opcode != -1) {
e8f943c3
HR		 1824 scsi_req_continue(req);
1825 return;
1826 }
1827
1828 buf = scsi_req_get_buf(req);
50b93533 1829 if (cmd->dcmd_opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
e8f943c3
HR		 1830 struct mfi_pd_info *info = cmd->iov_buf;
1831
1832 if (info->inquiry_data[0] == 0x7f) {
1833 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1834 memcpy(info->inquiry_data, buf, len);
1835 } else if (info->vpd_page83[0] == 0x7f) {
1836 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1837 memcpy(info->vpd_page83, buf, len);
1838 }
1839 scsi_req_continue(req);
50b93533 1840 } else if (cmd->dcmd_opcode == MFI_DCMD_LD_GET_INFO) {
e8f943c3
HR		 1841 struct mfi_ld_info *info = cmd->iov_buf;
1842
1843 if (cmd->iov_buf) {
1844 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1845 scsi_req_continue(req);
1846 }
1847 }
1848}
1849
1850static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1851 size_t resid)
1852{
1853 MegasasCmd *cmd = req->hba_private;
1854 uint8_t cmd_status = MFI_STAT_OK;
1855
1856 trace_megasas_command_complete(cmd->index, status, resid);
1857
9e55d588
PB		 1858 if (req->io_canceled) {
1859 return;
1860 }
1861
1862 if (cmd->req == NULL) {
e8f943c3
HR		 1863 /*
1864 * Internal command complete
1865 */
578fb500 1866 cmd_status = megasas_finish_internal_dcmd(cmd, req, resid);
e8f943c3
HR		 1867 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1868 return;
1869 }
1870 } else {
1871 req->status = status;
1872 trace_megasas_scsi_complete(cmd->index, req->status,
1873 cmd->iov_size, req->cmd.xfer);
1874 if (req->status != GOOD) {
1875 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1876 }
1877 if (req->status == CHECK_CONDITION) {
1878 megasas_copy_sense(cmd);
1879 }
1880
e8f943c3 1881 cmd->frame->header.scsi_status = req->status;
e8f943c3
HR		 1882 }
1883 cmd->frame->header.cmd_status = cmd_status;
9e55d588 1884 megasas_complete_command(cmd);
e8f943c3
HR		 1885}
1886
9e55d588 1887static void megasas_command_cancelled(SCSIRequest *req)
e8f943c3
HR		 1888{
1889 MegasasCmd *cmd = req->hba_private;
1890
9e55d588
PB		 1891 if (!cmd) {
1892 return;
e8f943c3 1893 }
9e55d588
PB		 1894 cmd->frame->header.cmd_status = MFI_STAT_SCSI_IO_FAILED;
1895 megasas_complete_command(cmd);
e8f943c3
HR		 1896}
1897
1898static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1899{
1900 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
a8170e5e 1901 hwaddr abort_addr, addr_hi, addr_lo;
e8f943c3
HR		 1902 MegasasCmd *abort_cmd;
1903
1904 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1905 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1906 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1907
1908 abort_cmd = megasas_lookup_frame(s, abort_addr);
1909 if (!abort_cmd) {
1910 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1911 s->event_count++;
1912 return MFI_STAT_OK;
1913 }
1914 if (!megasas_use_queue64(s)) {
1915 abort_ctx &= (uint64_t)0xFFFFFFFF;
1916 }
1917 if (abort_cmd->context != abort_ctx) {
d17e7448
EB		 1918 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->context,
1919 abort_cmd->index);
e8f943c3
HR		 1920 s->event_count++;
1921 return MFI_STAT_ABORT_NOT_POSSIBLE;
1922 }
1923 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1924 megasas_abort_command(abort_cmd);
1925 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1926 s->event_cmd = NULL;
1927 }
1928 s->event_count++;
1929 return MFI_STAT_OK;
1930}
1931
1932static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1933 uint32_t frame_count)
1934{
1935 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1936 uint64_t frame_context;
578fb500 1937 int frame_cmd;
e8f943c3
HR		 1938 MegasasCmd *cmd;
1939
1940 /*
1941 * Always read 64bit context, top bits will be
1942 * masked out if required in megasas_enqueue_frame()
1943 */
16578c6f 1944 frame_context = megasas_frame_get_context(s, frame_addr);
e8f943c3
HR		 1945
1946 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1947 if (!cmd) {
1948 /* reply queue full */
1949 trace_megasas_frame_busy(frame_addr);
16578c6f
PB		 1950 megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1951 megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
e8f943c3
HR		 1952 megasas_complete_frame(s, frame_context);
1953 s->event_count++;
1954 return;
1955 }
578fb500
PB		 1956 frame_cmd = cmd->frame->header.frame_cmd;
1957 switch (frame_cmd) {
e8f943c3
HR		 1958 case MFI_CMD_INIT:
1959 frame_status = megasas_init_firmware(s, cmd);
1960 break;
1961 case MFI_CMD_DCMD:
1962 frame_status = megasas_handle_dcmd(s, cmd);
1963 break;
1964 case MFI_CMD_ABORT:
1965 frame_status = megasas_handle_abort(s, cmd);
1966 break;
1967 case MFI_CMD_PD_SCSI_IO:
e8f943c3 1968 case MFI_CMD_LD_SCSI_IO:
578fb500 1969 frame_status = megasas_handle_scsi(s, cmd, frame_cmd);
e8f943c3
HR		 1970 break;
1971 case MFI_CMD_LD_READ:
1972 case MFI_CMD_LD_WRITE:
578fb500 1973 frame_status = megasas_handle_io(s, cmd, frame_cmd);
e8f943c3
HR		 1974 break;
1975 default:
578fb500 1976 trace_megasas_unhandled_frame_cmd(cmd->index, frame_cmd);
e8f943c3
HR		 1977 s->event_count++;
1978 break;
1979 }
1980 if (frame_status != MFI_STAT_INVALID_STATUS) {
421cc3e7
PB		 1981 if (cmd->frame) {
1982 cmd->frame->header.cmd_status = frame_status;
1983 } else {
1984 megasas_frame_set_cmd_status(s, frame_addr, frame_status);
1985 }
6df5718b 1986 megasas_unmap_frame(s, cmd);
e8f943c3
HR		 1987 megasas_complete_frame(s, cmd->context);
1988 }
1989}
1990
a8170e5e 1991static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
e8f943c3
HR		 1992 unsigned size)
1993{
1994 MegasasState *s = opaque;
e23d0498
HR		 1995 PCIDevice *pci_dev = PCI_DEVICE(s);
1996 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 1997 uint32_t retval = 0;
1998
1999 switch (addr) {
2000 case MFI_IDB:
2001 retval = 0;
77bb6b17 2002 trace_megasas_mmio_readl("MFI_IDB", retval);
e8f943c3
HR		 2003 break;
2004 case MFI_OMSG0:
2005 case MFI_OSP0:
e23d0498 2006 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
e8f943c3
HR		 2007 (s->fw_state & MFI_FWSTATE_MASK) |
2008 ((s->fw_sge & 0xff) << 16) |
2009 (s->fw_cmds & 0xFFFF);
77bb6b17
HR		 2010 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2011 retval);
e8f943c3
HR		 2012 break;
2013 case MFI_OSTS:
2014 if (megasas_intr_enabled(s) && s->doorbell) {
e23d0498 2015 retval = base_class->osts;
e8f943c3 2016 }
77bb6b17 2017 trace_megasas_mmio_readl("MFI_OSTS", retval);
e8f943c3
HR		 2018 break;
2019 case MFI_OMSK:
2020 retval = s->intr_mask;
77bb6b17 2021 trace_megasas_mmio_readl("MFI_OMSK", retval);
e8f943c3
HR		 2022 break;
2023 case MFI_ODCR0:
7957ee71 2024 retval = s->doorbell ? 1 : 0;
77bb6b17 2025 trace_megasas_mmio_readl("MFI_ODCR0", retval);
e8f943c3 2026 break;
e23d0498
HR		 2027 case MFI_DIAG:
2028 retval = s->diag;
77bb6b17 2029 trace_megasas_mmio_readl("MFI_DIAG", retval);
e23d0498
HR		 2030 break;
2031 case MFI_OSP1:
2032 retval = 15;
77bb6b17 2033 trace_megasas_mmio_readl("MFI_OSP1", retval);
e23d0498 2034 break;
e8f943c3
HR		 2035 default:
2036 trace_megasas_mmio_invalid_readl(addr);
2037 break;
2038 }
e8f943c3
HR		 2039 return retval;
2040}
2041
e23d0498
HR		 2042static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2043
a8170e5e 2044static void megasas_mmio_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2045 uint64_t val, unsigned size)
2046{
2047 MegasasState *s = opaque;
52190c1e 2048 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 2049 uint64_t frame_addr;
2050 uint32_t frame_count;
2051 int i;
2052
e8f943c3
HR		 2053 switch (addr) {
2054 case MFI_IDB:
77bb6b17 2055 trace_megasas_mmio_writel("MFI_IDB", val);
e8f943c3
HR		 2056 if (val & MFI_FWINIT_ABORT) {
2057 /* Abort all pending cmds */
2058 for (i = 0; i < s->fw_cmds; i++) {
2059 megasas_abort_command(&s->frames[i]);
2060 }
2061 }
2062 if (val & MFI_FWINIT_READY) {
2063 /* move to FW READY */
2064 megasas_soft_reset(s);
2065 }
2066 if (val & MFI_FWINIT_MFIMODE) {
2067 /* discard MFIs */
2068 }
e23d0498
HR		 2069 if (val & MFI_FWINIT_STOP_ADP) {
2070 /* Terminal error, stop processing */
2071 s->fw_state = MFI_FWSTATE_FAULT;
2072 }
e8f943c3
HR		 2073 break;
2074 case MFI_OMSK:
77bb6b17 2075 trace_megasas_mmio_writel("MFI_OMSK", val);
e8f943c3 2076 s->intr_mask = val;
4522b69c
HR		 2077 if (!megasas_intr_enabled(s) &&
2078 !msi_enabled(pci_dev) &&
2079 !msix_enabled(pci_dev)) {
e8f943c3 2080 trace_megasas_irq_lower();
9e64f8a3 2081 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2082 }
2083 if (megasas_intr_enabled(s)) {
4522b69c
HR		 2084 if (msix_enabled(pci_dev)) {
2085 trace_megasas_msix_enabled(0);
2086 } else if (msi_enabled(pci_dev)) {
2087 trace_megasas_msi_enabled(0);
2088 } else {
2089 trace_megasas_intr_enabled();
2090 }
e8f943c3
HR		 2091 } else {
2092 trace_megasas_intr_disabled();
e23d0498 2093 megasas_soft_reset(s);
e8f943c3
HR		 2094 }
2095 break;
2096 case MFI_ODCR0:
77bb6b17 2097 trace_megasas_mmio_writel("MFI_ODCR0", val);
e8f943c3 2098 s->doorbell = 0;
7957ee71
HR		 2099 if (megasas_intr_enabled(s)) {
2100 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
e8f943c3 2101 trace_megasas_irq_lower();
9e64f8a3 2102 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2103 }
2104 }
2105 break;
2106 case MFI_IQPH:
77bb6b17 2107 trace_megasas_mmio_writel("MFI_IQPH", val);
e8f943c3
HR		 2108 /* Received high 32 bits of a 64 bit MFI frame address */
2109 s->frame_hi = val;
2110 break;
2111 case MFI_IQPL:
77bb6b17 2112 trace_megasas_mmio_writel("MFI_IQPL", val);
e8f943c3 2113 /* Received low 32 bits of a 64 bit MFI frame address */
e23d0498 2114 /* Fallthrough */
e8f943c3 2115 case MFI_IQP:
77bb6b17
HR		 2116 if (addr == MFI_IQP) {
2117 trace_megasas_mmio_writel("MFI_IQP", val);
2118 /* Received 64 bit MFI frame address */
2119 s->frame_hi = 0;
2120 }
e8f943c3
HR		 2121 frame_addr = (val & ~0x1F);
2122 /* Add possible 64 bit offset */
2123 frame_addr |= ((uint64_t)s->frame_hi << 32);
2124 s->frame_hi = 0;
2125 frame_count = (val >> 1) & 0xF;
2126 megasas_handle_frame(s, frame_addr, frame_count);
2127 break;
e23d0498 2128 case MFI_SEQ:
77bb6b17 2129 trace_megasas_mmio_writel("MFI_SEQ", val);
e23d0498 2130 /* Magic sequence to start ADP reset */
0f590e79
PP		 2131 if (adp_reset_seq[s->adp_reset++] == val) {
2132 if (s->adp_reset == 6) {
2133 s->adp_reset = 0;
2134 s->diag = MFI_DIAG_WRITE_ENABLE;
2135 }
e23d0498
HR		 2136 } else {
2137 s->adp_reset = 0;
2138 s->diag = 0;
2139 }
e23d0498
HR		 2140 break;
2141 case MFI_DIAG:
77bb6b17 2142 trace_megasas_mmio_writel("MFI_DIAG", val);
e23d0498
HR		 2143 /* ADP reset */
2144 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2145 (val & MFI_DIAG_RESET_ADP)) {
2146 s->diag |= MFI_DIAG_RESET_ADP;
2147 megasas_soft_reset(s);
2148 s->adp_reset = 0;
2149 s->diag = 0;
2150 }
2151 break;
e8f943c3
HR		 2152 default:
2153 trace_megasas_mmio_invalid_writel(addr, val);
2154 break;
2155 }
2156}
2157
2158static const MemoryRegionOps megasas_mmio_ops = {
2159 .read = megasas_mmio_read,
2160 .write = megasas_mmio_write,
2161 .endianness = DEVICE_LITTLE_ENDIAN,
2162 .impl = {
2163 .min_access_size = 8,
2164 .max_access_size = 8,
2165 }
2166};
2167
a8170e5e 2168static uint64_t megasas_port_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2169 unsigned size)
2170{
2171 return megasas_mmio_read(opaque, addr & 0xff, size);
2172}
2173
a8170e5e 2174static void megasas_port_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2175 uint64_t val, unsigned size)
2176{
2177 megasas_mmio_write(opaque, addr & 0xff, val, size);
2178}
2179
2180static const MemoryRegionOps megasas_port_ops = {
2181 .read = megasas_port_read,
2182 .write = megasas_port_write,
2183 .endianness = DEVICE_LITTLE_ENDIAN,
2184 .impl = {
2185 .min_access_size = 4,
2186 .max_access_size = 4,
2187 }
2188};
2189
a8170e5e 2190static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2191 unsigned size)
2192{
2193 return 0;
2194}
2195
55875fc4
SP		 2196static void megasas_queue_write(void *opaque, hwaddr addr,
2197 uint64_t val, unsigned size)
2198{
2199 return;
2200}
2201
e8f943c3
HR		 2202static const MemoryRegionOps megasas_queue_ops = {
2203 .read = megasas_queue_read,
55875fc4 2204 .write = megasas_queue_write,
e8f943c3
HR		 2205 .endianness = DEVICE_LITTLE_ENDIAN,
2206 .impl = {
2207 .min_access_size = 8,
2208 .max_access_size = 8,
2209 }
2210};
2211
2212static void megasas_soft_reset(MegasasState *s)
2213{
2214 int i;
2215 MegasasCmd *cmd;
2216
8d72db68 2217 trace_megasas_reset(s->fw_state);
e8f943c3
HR		 2218 for (i = 0; i < s->fw_cmds; i++) {
2219 cmd = &s->frames[i];
2220 megasas_abort_command(cmd);
2221 }
8d72db68
HR		 2222 if (s->fw_state == MFI_FWSTATE_READY) {
2223 BusChild *kid;
2224
2225 /*
2226 * The EFI firmware doesn't handle UA,
2227 * so we need to clear the Power On/Reset UA
2228 * after the initial reset.
2229 */
2230 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 2231 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
8d72db68
HR		 2232
2233 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2234 scsi_device_unit_attention_reported(sdev);
2235 }
2236 }
e8f943c3
HR		 2237 megasas_reset_frames(s);
2238 s->reply_queue_len = s->fw_cmds;
2239 s->reply_queue_pa = 0;
2240 s->consumer_pa = 0;
2241 s->producer_pa = 0;
2242 s->fw_state = MFI_FWSTATE_READY;
2243 s->doorbell = 0;
2244 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2245 s->frame_hi = 0;
2246 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2247 s->event_count++;
2248 s->boot_event = s->event_count;
2249}
2250
2251static void megasas_scsi_reset(DeviceState *dev)
2252{
c79e16ae 2253 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2254
2255 megasas_soft_reset(s);
2256}
2257
e23d0498 2258static const VMStateDescription vmstate_megasas_gen1 = {
e8f943c3
HR		 2259 .name = "megasas",
2260 .version_id = 0,
2261 .minimum_version_id = 0,
d49805ae 2262 .fields = (VMStateField[]) {
52190c1e 2263 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
23335f62 2264 VMSTATE_MSIX(parent_obj, MegasasState),
e8f943c3
HR		 2265
2266 VMSTATE_INT32(fw_state, MegasasState),
2267 VMSTATE_INT32(intr_mask, MegasasState),
2268 VMSTATE_INT32(doorbell, MegasasState),
2269 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2270 VMSTATE_UINT64(consumer_pa, MegasasState),
2271 VMSTATE_UINT64(producer_pa, MegasasState),
2272 VMSTATE_END_OF_LIST()
2273 }
2274};
2275
e23d0498
HR		 2276static const VMStateDescription vmstate_megasas_gen2 = {
2277 .name = "megasas-gen2",
2278 .version_id = 0,
2279 .minimum_version_id = 0,
2280 .minimum_version_id_old = 0,
2281 .fields = (VMStateField[]) {
20daa90a 2282 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
e23d0498
HR		 2283 VMSTATE_MSIX(parent_obj, MegasasState),
2284
2285 VMSTATE_INT32(fw_state, MegasasState),
2286 VMSTATE_INT32(intr_mask, MegasasState),
2287 VMSTATE_INT32(doorbell, MegasasState),
2288 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2289 VMSTATE_UINT64(consumer_pa, MegasasState),
2290 VMSTATE_UINT64(producer_pa, MegasasState),
2291 VMSTATE_END_OF_LIST()
2292 }
2293};
2294
18fc611b 2295static void megasas_scsi_uninit(PCIDevice *d)
e8f943c3 2296{
c79e16ae 2297 MegasasState *s = MEGASAS(d);
e8f943c3 2298
4522b69c
HR		 2299 if (megasas_use_msix(s)) {
2300 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2301 }
afea4e14 2302 msi_uninit(d);
e8f943c3
HR		 2303}
2304
2305static const struct SCSIBusInfo megasas_scsi_info = {
2306 .tcq = true,
2307 .max_target = MFI_MAX_LD,
2308 .max_lun = 255,
2309
2310 .transfer_data = megasas_xfer_complete,
2311 .get_sg_list = megasas_get_sg_list,
2312 .complete = megasas_command_complete,
9e55d588 2313 .cancel = megasas_command_cancelled,
e8f943c3
HR		 2314};
2315
ae071cc8 2316static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
e8f943c3 2317{
c79e16ae 2318 MegasasState *s = MEGASAS(dev);
e23d0498 2319 MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 2320 uint8_t *pci_conf;
2321 int i, bar_type;
1108b2f8
C		 2322 Error *err = NULL;
2323 int ret;
e8f943c3 2324
52190c1e 2325 pci_conf = dev->config;
e8f943c3
HR		 2326
2327 /* PCI latency timer = 0 */
2328 pci_conf[PCI_LATENCY_TIMER] = 0;
2329 /* Interrupt pin 1 */
2330 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2331
afea4e14 2332 if (s->msi != ON_OFF_AUTO_OFF) {
1108b2f8
C		 2333 ret = msi_init(dev, 0x50, 1, true, false, &err);
2334 /* Any error other than -ENOTSUP(board's MSI support is broken)
2335 * is a programming error */
2336 assert(!ret || ret == -ENOTSUP);
2337 if (ret && s->msi == ON_OFF_AUTO_ON) {
2338 /* Can't satisfy user's explicit msi=on request, fail */
2339 error_append_hint(&err, "You have to use msi=auto (default) or "
2340 "msi=off with this machine type.\n");
2341 error_propagate(errp, err);
2342 return;
2343 } else if (ret) {
2344 /* With msi=auto, we fall back to MSI off silently */
2345 s->msi = ON_OFF_AUTO_OFF;
2346 error_free(err);
2347 }
2348 }
2349
29776739 2350 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
e8f943c3 2351 "megasas-mmio", 0x4000);
29776739 2352 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
e8f943c3 2353 "megasas-io", 256);
29776739 2354 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
e8f943c3
HR		 2355 "megasas-queue", 0x40000);
2356
e8f943c3 2357 if (megasas_use_msix(s) &&
e23d0498 2358 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
ee640c62
C		 2359 &s->mmio_io, b->mmio_bar, 0x3800, 0x68, NULL)) {
2360 /* TODO: check msix_init's error, and should fail on msix=on */
b4b4a57f 2361 s->msix = ON_OFF_AUTO_OFF;
e8f943c3 2362 }
ee640c62 2363
e23d0498
HR		 2364 if (pci_is_express(dev)) {
2365 pcie_endpoint_cap_init(dev, 0xa0);
2366 }
e8f943c3
HR		 2367
2368 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
e23d0498
HR		 2369 pci_register_bar(dev, b->ioport_bar,
2370 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2371 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
52190c1e 2372 pci_register_bar(dev, 3, bar_type, &s->queue_io);
e8f943c3
HR		 2373
2374 if (megasas_use_msix(s)) {
52190c1e 2375 msix_vector_use(dev, 0);
e8f943c3
HR		 2376 }
2377
8d72db68 2378 s->fw_state = MFI_FWSTATE_READY;
76b523db
HR		 2379 if (!s->sas_addr) {
2380 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2381 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2382 s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2383 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2384 s->sas_addr |= PCI_FUNC(dev->devfn);
2385 }
fb654157 2386 if (!s->hba_serial) {
23335f62 2387 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
fb654157 2388 }
e8f943c3
HR		 2389 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2390 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2391 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2392 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2393 } else {
2394 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2395 }
2396 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2397 s->fw_cmds = MEGASAS_MAX_FRAMES;
2398 }
2399 trace_megasas_init(s->fw_sge, s->fw_cmds,
e8f943c3 2400 megasas_is_jbod(s) ? "jbod" : "raid");
3f2cd4dd
HR		 2401
2402 if (megasas_is_jbod(s)) {
2403 s->fw_luns = MFI_MAX_SYS_PDS;
2404 } else {
2405 s->fw_luns = MFI_MAX_LD;
2406 }
e8f943c3
HR		 2407 s->producer_pa = 0;
2408 s->consumer_pa = 0;
2409 for (i = 0; i < s->fw_cmds; i++) {
2410 s->frames[i].index = i;
2411 s->frames[i].context = -1;
2412 s->frames[i].pa = 0;
2413 s->frames[i].state = s;
2414 }
2415
b1187b51
AF		 2416 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2417 &megasas_scsi_info, NULL);
e8f943c3
HR		 2418}
2419
e23d0498 2420static Property megasas_properties_gen1[] = {
e8f943c3
HR		 2421 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2422 MEGASAS_DEFAULT_SGE),
2423 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2424 MEGASAS_DEFAULT_FRAMES),
fb654157 2425 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
c7bcc85d 2426 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
b4b4a57f
C		 2427 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2428 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
e8f943c3
HR		 2429 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2430 MEGASAS_FLAG_USE_JBOD, false),
2431 DEFINE_PROP_END_OF_LIST(),
2432};
2433
e23d0498
HR		 2434static Property megasas_properties_gen2[] = {
2435 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2436 MEGASAS_DEFAULT_SGE),
2437 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2438 MEGASAS_GEN2_DEFAULT_FRAMES),
2439 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2440 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
b4b4a57f
C		 2441 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2442 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
e23d0498
HR		 2443 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2444 MEGASAS_FLAG_USE_JBOD, false),
2445 DEFINE_PROP_END_OF_LIST(),
2446};
2447
2448typedef struct MegasasInfo {
2449 const char *name;
2450 const char *desc;
2451 const char *product_name;
2452 const char *product_version;
2453 uint16_t device_id;
2454 uint16_t subsystem_id;
2455 int ioport_bar;
2456 int mmio_bar;
2457 bool is_express;
2458 int osts;
2459 const VMStateDescription *vmsd;
2460 Property *props;
2461} MegasasInfo;
2462
2463static struct MegasasInfo megasas_devices[] = {
2464 {
2465 .name = TYPE_MEGASAS_GEN1,
2466 .desc = "LSI MegaRAID SAS 1078",
2467 .product_name = "LSI MegaRAID SAS 8708EM2",
2468 .product_version = MEGASAS_VERSION_GEN1,
2469 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2470 .subsystem_id = 0x1013,
2471 .ioport_bar = 2,
2472 .mmio_bar = 0,
2473 .osts = MFI_1078_RM | 1,
2474 .is_express = false,
2475 .vmsd = &vmstate_megasas_gen1,
2476 .props = megasas_properties_gen1,
2477 },{
2478 .name = TYPE_MEGASAS_GEN2,
2479 .desc = "LSI MegaRAID SAS 2108",
2480 .product_name = "LSI MegaRAID SAS 9260-8i",
2481 .product_version = MEGASAS_VERSION_GEN2,
2482 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2483 .subsystem_id = 0x9261,
2484 .ioport_bar = 0,
2485 .mmio_bar = 1,
2486 .osts = MFI_GEN2_RM,
2487 .is_express = true,
2488 .vmsd = &vmstate_megasas_gen2,
2489 .props = megasas_properties_gen2,
2490 }
2491};
2492
e8f943c3
HR		 2493static void megasas_class_init(ObjectClass *oc, void *data)
2494{
2495 DeviceClass *dc = DEVICE_CLASS(oc);
2496 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
e23d0498
HR		 2497 MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc);
2498 const MegasasInfo *info = data;
e8f943c3 2499
ae071cc8 2500 pc->realize = megasas_scsi_realize;
e8f943c3
HR		 2501 pc->exit = megasas_scsi_uninit;
2502 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
e23d0498 2503 pc->device_id = info->device_id;
e8f943c3 2504 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
e23d0498 2505 pc->subsystem_id = info->subsystem_id;
e8f943c3 2506 pc->class_id = PCI_CLASS_STORAGE_RAID;
e23d0498
HR		 2507 pc->is_express = info->is_express;
2508 e->mmio_bar = info->mmio_bar;
2509 e->ioport_bar = info->ioport_bar;
2510 e->osts = info->osts;
2511 e->product_name = info->product_name;
2512 e->product_version = info->product_version;
2513 dc->props = info->props;
e8f943c3 2514 dc->reset = megasas_scsi_reset;
e23d0498 2515 dc->vmsd = info->vmsd;
125ee0ed 2516 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
e23d0498 2517 dc->desc = info->desc;
e8f943c3
HR		 2518}
2519
2520static const TypeInfo megasas_info = {
e23d0498 2521 .name = TYPE_MEGASAS_BASE,
e8f943c3
HR		 2522 .parent = TYPE_PCI_DEVICE,
2523 .instance_size = sizeof(MegasasState),
e23d0498
HR		 2524 .class_size = sizeof(MegasasBaseClass),
2525 .abstract = true,
e8f943c3
HR		 2526};
2527
2528static void megasas_register_types(void)
2529{
e23d0498
HR		 2530 int i;
2531
e8f943c3 2532 type_register_static(&megasas_info);
e23d0498
HR		 2533 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2534 const MegasasInfo *info = &megasas_devices[i];
2535 TypeInfo type_info = {};
2536
2537 type_info.name = info->name;
2538 type_info.parent = TYPE_MEGASAS_BASE;
2539 type_info.class_data = (void *)info;
2540 type_info.class_init = megasas_class_init;
2541
2542 type_register(&type_info);
2543 }
e8f943c3
HR		 2544}
2545
2546type_init(megasas_register_types)
QEMU mirror