[mirror_qemu.git] / hw / spapr_pci.c

/*
 * QEMU sPAPR PCI host originated from Uninorth PCI host
 *
 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
 * Copyright (C) 2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "pci.h"
#include "pci_host.h"
#include "hw/spapr.h"
#include "hw/spapr_pci.h"
#include "exec-memory.h"
#include <libfdt.h>

#include "hw/pci_internals.h"

static PCIDevice *find_dev(sPAPREnvironment *spapr,
                           uint64_t buid, uint32_t config_addr)
{
    int devfn = (config_addr >> 8) & 0xFF;
    sPAPRPHBState *phb;

    QLIST_FOREACH(phb, &spapr->phbs, list) {
        BusChild *kid;

        if (phb->buid != buid) {
            continue;
        }

        QTAILQ_FOREACH(kid, &phb->host_state.bus->qbus.children, sibling) {
            PCIDevice *dev = (PCIDevice *)kid->child;
            if (dev->devfn == devfn) {
                return dev;
            }
        }
    }

    return NULL;
}

static uint32_t rtas_pci_cfgaddr(uint32_t arg)
{
    /* This handles the encoding of extended config space addresses */
    return ((arg >> 20) & 0xf00) | (arg & 0xff);
}

static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid,
                                   uint32_t addr, uint32_t size,
                                   target_ulong rets)
{
    PCIDevice *pci_dev;
    uint32_t val;

    if ((size != 1) && (size != 2) && (size != 4)) {
        /* access must be 1, 2 or 4 bytes */
        rtas_st(rets, 0, -1);
        return;
    }

    pci_dev = find_dev(spapr, buid, addr);
    addr = rtas_pci_cfgaddr(addr);

    if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
        /* Access must be to a valid device, within bounds and
         * naturally aligned */
        rtas_st(rets, 0, -1);
        return;
    }

    val = pci_host_config_read_common(pci_dev, addr,
                                      pci_config_size(pci_dev), size);

    rtas_st(rets, 0, 0);
    rtas_st(rets, 1, val);
}

static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
                                     uint32_t token, uint32_t nargs,
                                     target_ulong args,
                                     uint32_t nret, target_ulong rets)
{
    uint64_t buid;
    uint32_t size, addr;

    if ((nargs != 4) || (nret != 2)) {
        rtas_st(rets, 0, -1);
        return;
    }

    buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
    size = rtas_ld(args, 3);
    addr = rtas_ld(args, 0);

    finish_read_pci_config(spapr, buid, addr, size, rets);
}

static void rtas_read_pci_config(sPAPREnvironment *spapr,
                                 uint32_t token, uint32_t nargs,
                                 target_ulong args,
                                 uint32_t nret, target_ulong rets)
{
    uint32_t size, addr;

    if ((nargs != 2) || (nret != 2)) {
        rtas_st(rets, 0, -1);
        return;
    }

    size = rtas_ld(args, 1);
    addr = rtas_ld(args, 0);

    finish_read_pci_config(spapr, 0, addr, size, rets);
}

static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid,
                                    uint32_t addr, uint32_t size,
                                    uint32_t val, target_ulong rets)
{
    PCIDevice *pci_dev;

    if ((size != 1) && (size != 2) && (size != 4)) {
        /* access must be 1, 2 or 4 bytes */
        rtas_st(rets, 0, -1);
        return;
    }

    pci_dev = find_dev(spapr, buid, addr);
    addr = rtas_pci_cfgaddr(addr);

    if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
        /* Access must be to a valid device, within bounds and
         * naturally aligned */
        rtas_st(rets, 0, -1);
        return;
    }

    pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
                                 val, size);

    rtas_st(rets, 0, 0);
}

static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
                                      uint32_t token, uint32_t nargs,
                                      target_ulong args,
                                      uint32_t nret, target_ulong rets)
{
    uint64_t buid;
    uint32_t val, size, addr;

    if ((nargs != 5) || (nret != 1)) {
        rtas_st(rets, 0, -1);
        return;
    }

    buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
    val = rtas_ld(args, 4);
    size = rtas_ld(args, 3);
    addr = rtas_ld(args, 0);

    finish_write_pci_config(spapr, buid, addr, size, val, rets);
}

static void rtas_write_pci_config(sPAPREnvironment *spapr,
                                  uint32_t token, uint32_t nargs,
                                  target_ulong args,
                                  uint32_t nret, target_ulong rets)
{
    uint32_t val, size, addr;

    if ((nargs != 3) || (nret != 1)) {
        rtas_st(rets, 0, -1);
        return;
    }


    val = rtas_ld(args, 2);
    size = rtas_ld(args, 1);
    addr = rtas_ld(args, 0);

    finish_write_pci_config(spapr, 0, addr, size, val, rets);
}

static int pci_spapr_swizzle(int slot, int pin)
{
    return (slot + pin) % PCI_NUM_PINS;
}

static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
{
    /*
     * Here we need to convert pci_dev + irq_num to some unique value
     * which is less than number of IRQs on the specific bus (4).  We
     * use standard PCI swizzling, that is (slot number + pin number)
     * % 4.
     */
    return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
}

static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
{
    /*
     * Here we use the number returned by pci_spapr_map_irq to find a
     * corresponding qemu_irq.
     */
    sPAPRPHBState *phb = opaque;

    qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
}

static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
                              unsigned size)
{
    switch (size) {
    case 1:
        return cpu_inb(addr);
    case 2:
        return cpu_inw(addr);
    case 4:
        return cpu_inl(addr);
    }
    assert(0);
}

static void spapr_io_write(void *opaque, target_phys_addr_t addr,
                           uint64_t data, unsigned size)
{
    switch (size) {
    case 1:
        cpu_outb(addr, data);
        return;
    case 2:
        cpu_outw(addr, data);
        return;
    case 4:
        cpu_outl(addr, data);
        return;
    }
    assert(0);
}

static const MemoryRegionOps spapr_io_ops = {
    .endianness = DEVICE_LITTLE_ENDIAN,
    .read = spapr_io_read,
    .write = spapr_io_write
};

/*
 * PHB PCI device
 */
static int spapr_phb_init(SysBusDevice *s)
{
    sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
    char *namebuf;
    int i;
    PCIBus *bus;

    phb->dtbusname = g_strdup_printf("pci@%" PRIx64, phb->buid);
    namebuf = alloca(strlen(phb->dtbusname) + 32);

    /* Initialize memory regions */
    sprintf(namebuf, "%s.mmio", phb->dtbusname);
    memory_region_init(&phb->memspace, namebuf, INT64_MAX);

    sprintf(namebuf, "%s.mmio-alias", phb->dtbusname);
    memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
                             SPAPR_PCI_MEM_WIN_BUS_OFFSET, phb->mem_win_size);
    memory_region_add_subregion(get_system_memory(), phb->mem_win_addr,
                                &phb->memwindow);

    /* On ppc, we only have MMIO no specific IO space from the CPU
     * perspective.  In theory we ought to be able to embed the PCI IO
     * memory region direction in the system memory space.  However,
     * if any of the IO BAR subregions use the old_portio mechanism,
     * that won't be processed properly unless accessed from the
     * system io address space.  This hack to bounce things via
     * system_io works around the problem until all the users of
     * old_portion are updated */
    sprintf(namebuf, "%s.io", phb->dtbusname);
    memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
    /* FIXME: fix to support multiple PHBs */
    memory_region_add_subregion(get_system_io(), 0, &phb->iospace);

    sprintf(namebuf, "%s.io-alias", phb->dtbusname);
    memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
                          namebuf, SPAPR_PCI_IO_WIN_SIZE);
    memory_region_add_subregion(get_system_memory(), phb->io_win_addr,
                                &phb->iowindow);

    bus = pci_register_bus(&phb->busdev.qdev,
                           phb->busname ? phb->busname : phb->dtbusname,
                           pci_spapr_set_irq, pci_spapr_map_irq, phb,
                           &phb->memspace, &phb->iospace,
                           PCI_DEVFN(0, 0), PCI_NUM_PINS);
    phb->host_state.bus = bus;

    QLIST_INSERT_HEAD(&spapr->phbs, phb, list);

    /* Initialize the LSI table */
    for (i = 0; i < PCI_NUM_PINS; i++) {
        qemu_irq qirq;
        uint32_t num;

        qirq = spapr_allocate_lsi(0, &num);
        if (!qirq) {
            return -1;
        }

        phb->lsi_table[i].dt_irq = num;
        phb->lsi_table[i].qirq = qirq;
    }

    return 0;
}

static Property spapr_phb_properties[] = {
    DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, 0),
    DEFINE_PROP_STRING("busname", sPAPRPHBState, busname),
    DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, 0),
    DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 0x20000000),
    DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, 0),
    DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 0x10000),
    DEFINE_PROP_END_OF_LIST(),
};

static void spapr_phb_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sdc->init = spapr_phb_init;
    dc->props = spapr_phb_properties;

    spapr_rtas_register("read-pci-config", rtas_read_pci_config);
    spapr_rtas_register("write-pci-config", rtas_write_pci_config);
    spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
    spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
}

static TypeInfo spapr_phb_info = {
    .name          = "spapr-pci-host-bridge",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(sPAPRPHBState),
    .class_init    = spapr_phb_class_init,
};

void spapr_create_phb(sPAPREnvironment *spapr,
                      const char *busname, uint64_t buid,
                      uint64_t mem_win_addr, uint64_t mem_win_size,
                      uint64_t io_win_addr)
{
    DeviceState *dev;

    dev = qdev_create(NULL, spapr_phb_info.name);

    if (busname) {
        qdev_prop_set_string(dev, "busname", g_strdup(busname));
    }
    qdev_prop_set_uint64(dev, "buid", buid);
    qdev_prop_set_uint64(dev, "mem_win_addr", mem_win_addr);
    qdev_prop_set_uint64(dev, "mem_win_size", mem_win_size);
    qdev_prop_set_uint64(dev, "io_win_addr", io_win_addr);

    qdev_init_nofail(dev);
}

/* Macros to operate with address in OF binding to PCI */
#define b_x(x, p, l)    (((x) & ((1<<(l))-1)) << (p))
#define b_n(x)          b_x((x), 31, 1) /* 0 if relocatable */
#define b_p(x)          b_x((x), 30, 1) /* 1 if prefetchable */
#define b_t(x)          b_x((x), 29, 1) /* 1 if the address is aliased */
#define b_ss(x)         b_x((x), 24, 2) /* the space code */
#define b_bbbbbbbb(x)   b_x((x), 16, 8) /* bus number */
#define b_ddddd(x)      b_x((x), 11, 5) /* device number */
#define b_fff(x)        b_x((x), 8, 3)  /* function number */
#define b_rrrrrrrr(x)   b_x((x), 0, 8)  /* register number */

int spapr_populate_pci_devices(sPAPRPHBState *phb,
                               uint32_t xics_phandle,
                               void *fdt)
{
    int bus_off, i, j;
    char nodename[256];
    uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
    struct {
        uint32_t hi;
        uint64_t child;
        uint64_t parent;
        uint64_t size;
    } __attribute__((packed)) ranges[] = {
        {
            cpu_to_be32(b_ss(1)), cpu_to_be64(0),
            cpu_to_be64(phb->io_win_addr),
            cpu_to_be64(memory_region_size(&phb->iospace)),
        },
        {
            cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
            cpu_to_be64(phb->mem_win_addr),
            cpu_to_be64(memory_region_size(&phb->memwindow)),
        },
    };
    uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
    uint32_t interrupt_map_mask[] = {
        cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
    uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];

    /* Start populating the FDT */
    sprintf(nodename, "pci@%" PRIx64, phb->buid);
    bus_off = fdt_add_subnode(fdt, 0, nodename);
    if (bus_off < 0) {
        return bus_off;
    }

#define _FDT(exp) \
    do { \
        int ret = (exp);                                           \
        if (ret < 0) {                                             \
            return ret;                                            \
        }                                                          \
    } while (0)

    /* Write PHB properties */
    _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
    _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
    _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
    _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
    _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
    _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
    _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
    _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
    _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
    _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));

    /* Build the interrupt-map, this must matches what is done
     * in pci_spapr_map_irq
     */
    _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
                     &interrupt_map_mask, sizeof(interrupt_map_mask)));
    for (i = 0; i < PCI_SLOT_MAX; i++) {
        for (j = 0; j < PCI_NUM_PINS; j++) {
            uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
            int lsi_num = pci_spapr_swizzle(i, j);

            irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
            irqmap[1] = 0;
            irqmap[2] = 0;
            irqmap[3] = cpu_to_be32(j+1);
            irqmap[4] = cpu_to_be32(xics_phandle);
            irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].dt_irq);
            irqmap[6] = cpu_to_be32(0x8);
        }
    }
    /* Write interrupt map */
    _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
                     sizeof(interrupt_map)));

    return 0;
}

static void register_types(void)
{
    type_register_static(&spapr_phb_info);
}
type_init(register_types)
Commit	Line	Data
3384f95c DG	1	/*
	2	* QEMU sPAPR PCI host originated from Uninorth PCI host
	3	*
	4	* Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
	5	* Copyright (C) 2011 David Gibson, IBM Corporation.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include "hw.h"
	26	#include "pci.h"
	27	#include "pci_host.h"
	28	#include "hw/spapr.h"
	29	#include "hw/spapr_pci.h"
	30	#include "exec-memory.h"
	31	#include <libfdt.h>
	32
	33	#include "hw/pci_internals.h"
	34
3384f95c DG	35	static PCIDevice find_dev(sPAPREnvironment spapr,
	36	uint64_t buid, uint32_t config_addr)
	37	{
3384f95c DG	38	int devfn = (config_addr >> 8) & 0xFF;
	39	sPAPRPHBState *phb;
	40
	41	QLIST_FOREACH(phb, &spapr->phbs, list) {
0866aca1 AL	42	BusChild *kid;
0866aca1 AL	43
3384f95c DG	44	if (phb->buid != buid) {
	45	continue;
	46	}
	47
0866aca1 AL	48	QTAILQ_FOREACH(kid, &phb->host_state.bus->qbus.children, sibling) {
0866aca1 AL	49	PCIDevice dev = (PCIDevice )kid->child;
3384f95c DG	50	if (dev->devfn == devfn) {
	51	return dev;
	52	}
	53	}
	54	}
	55
	56	return NULL;
	57	}
	58
3f7565c9 BH	59	static uint32_t rtas_pci_cfgaddr(uint32_t arg)
3f7565c9 BH	60	{
92615a5a	61	/* This handles the encoding of extended config space addresses */
3f7565c9 BH	62	return ((arg >> 20) & 0xf00) \| (arg & 0xff);
	63	}
	64
92615a5a DG	65	static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid,
	66	uint32_t addr, uint32_t size,
	67	target_ulong rets)
88045ac5	68	{
92615a5a DG	69	PCIDevice *pci_dev;
	70	uint32_t val;
	71
	72	if ((size != 1) && (size != 2) && (size != 4)) {
	73	/* access must be 1, 2 or 4 bytes */
	74	rtas_st(rets, 0, -1);
	75	return;
88045ac5	76	}
88045ac5	77
92615a5a DG	78	pci_dev = find_dev(spapr, buid, addr);
	79	addr = rtas_pci_cfgaddr(addr);
	80
	81	if (!pci_dev \|\| (addr % size) \|\| (addr >= pci_config_size(pci_dev))) {
	82	/* Access must be to a valid device, within bounds and
	83	* naturally aligned */
	84	rtas_st(rets, 0, -1);
	85	return;
88045ac5	86	}
92615a5a DG	87
	88	val = pci_host_config_read_common(pci_dev, addr,
	89	pci_config_size(pci_dev), size);
	90
	91	rtas_st(rets, 0, 0);
	92	rtas_st(rets, 1, val);
88045ac5 AG	93	}
88045ac5 AG	94
3384f95c DG	95	static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
	96	uint32_t token, uint32_t nargs,
	97	target_ulong args,
	98	uint32_t nret, target_ulong rets)
	99	{
92615a5a DG	100	uint64_t buid;
92615a5a DG	101	uint32_t size, addr;
3384f95c	102
92615a5a	103	if ((nargs != 4) \|\| (nret != 2)) {
3384f95c DG	104	rtas_st(rets, 0, -1);
	105	return;
	106	}
92615a5a DG	107
92615a5a DG	108	buid = ((uint64_t)rtas_ld(args, 1) << 32) \| rtas_ld(args, 2);
3384f95c	109	size = rtas_ld(args, 3);
92615a5a DG	110	addr = rtas_ld(args, 0);
	111
	112	finish_read_pci_config(spapr, buid, addr, size, rets);
3384f95c DG	113	}
	114
	115	static void rtas_read_pci_config(sPAPREnvironment *spapr,
	116	uint32_t token, uint32_t nargs,
	117	target_ulong args,
	118	uint32_t nret, target_ulong rets)
	119	{
92615a5a	120	uint32_t size, addr;
3384f95c	121
92615a5a	122	if ((nargs != 2) \|\| (nret != 2)) {
3384f95c DG	123	rtas_st(rets, 0, -1);
	124	return;
	125	}
92615a5a	126
3384f95c	127	size = rtas_ld(args, 1);
92615a5a DG	128	addr = rtas_ld(args, 0);
	129
	130	finish_read_pci_config(spapr, 0, addr, size, rets);
	131	}
	132
	133	static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid,
	134	uint32_t addr, uint32_t size,
	135	uint32_t val, target_ulong rets)
	136	{
	137	PCIDevice *pci_dev;
	138
	139	if ((size != 1) && (size != 2) && (size != 4)) {
	140	/* access must be 1, 2 or 4 bytes */
	141	rtas_st(rets, 0, -1);
	142	return;
	143	}
	144
	145	pci_dev = find_dev(spapr, buid, addr);
	146	addr = rtas_pci_cfgaddr(addr);
	147
	148	if (!pci_dev \|\| (addr % size) \|\| (addr >= pci_config_size(pci_dev))) {
	149	/* Access must be to a valid device, within bounds and
	150	* naturally aligned */
	151	rtas_st(rets, 0, -1);
	152	return;
	153	}
	154
	155	pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
	156	val, size);
	157
3384f95c	158	rtas_st(rets, 0, 0);
3384f95c DG	159	}
	160
	161	static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
	162	uint32_t token, uint32_t nargs,
	163	target_ulong args,
	164	uint32_t nret, target_ulong rets)
	165	{
92615a5a	166	uint64_t buid;
3384f95c	167	uint32_t val, size, addr;
3384f95c	168
92615a5a	169	if ((nargs != 5) \|\| (nret != 1)) {
3384f95c DG	170	rtas_st(rets, 0, -1);
	171	return;
	172	}
92615a5a DG	173
92615a5a DG	174	buid = ((uint64_t)rtas_ld(args, 1) << 32) \| rtas_ld(args, 2);
3384f95c DG	175	val = rtas_ld(args, 4);
3384f95c DG	176	size = rtas_ld(args, 3);
92615a5a DG	177	addr = rtas_ld(args, 0);
	178
	179	finish_write_pci_config(spapr, buid, addr, size, val, rets);
3384f95c DG	180	}
	181
	182	static void rtas_write_pci_config(sPAPREnvironment *spapr,
	183	uint32_t token, uint32_t nargs,
	184	target_ulong args,
	185	uint32_t nret, target_ulong rets)
	186	{
	187	uint32_t val, size, addr;
3384f95c	188
92615a5a	189	if ((nargs != 3) \|\| (nret != 1)) {
3384f95c DG	190	rtas_st(rets, 0, -1);
	191	return;
	192	}
92615a5a DG	193
92615a5a DG	194
3384f95c DG	195	val = rtas_ld(args, 2);
3384f95c DG	196	size = rtas_ld(args, 1);
92615a5a DG	197	addr = rtas_ld(args, 0);
	198
	199	finish_write_pci_config(spapr, 0, addr, size, val, rets);
3384f95c DG	200	}
3384f95c DG	201
7fb0bd34 DG	202	static int pci_spapr_swizzle(int slot, int pin)
	203	{
	204	return (slot + pin) % PCI_NUM_PINS;
	205	}
	206
3384f95c DG	207	static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
	208	{
	209	/*
	210	* Here we need to convert pci_dev + irq_num to some unique value
7fb0bd34 DG	211	* which is less than number of IRQs on the specific bus (4). We
	212	* use standard PCI swizzling, that is (slot number + pin number)
	213	* % 4.
3384f95c	214	*/
7fb0bd34	215	return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
3384f95c DG	216	}
	217
	218	static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
	219	{
	220	/*
	221	* Here we use the number returned by pci_spapr_map_irq to find a
	222	* corresponding qemu_irq.
	223	*/
	224	sPAPRPHBState *phb = opaque;
	225
	226	qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
	227	}
	228
3384f95c DG	229	static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
	230	unsigned size)
	231	{
	232	switch (size) {
	233	case 1:
	234	return cpu_inb(addr);
	235	case 2:
	236	return cpu_inw(addr);
	237	case 4:
	238	return cpu_inl(addr);
	239	}
	240	assert(0);
	241	}
	242
	243	static void spapr_io_write(void *opaque, target_phys_addr_t addr,
	244	uint64_t data, unsigned size)
	245	{
	246	switch (size) {
	247	case 1:
	248	cpu_outb(addr, data);
	249	return;
	250	case 2:
	251	cpu_outw(addr, data);
	252	return;
	253	case 4:
	254	cpu_outl(addr, data);
	255	return;
	256	}
	257	assert(0);
	258	}
	259
a348f108	260	static const MemoryRegionOps spapr_io_ops = {
3384f95c DG	261	.endianness = DEVICE_LITTLE_ENDIAN,
	262	.read = spapr_io_read,
	263	.write = spapr_io_write
	264	};
	265
298a9710 DG	266	/*
	267	* PHB PCI device
	268	*/
	269	static int spapr_phb_init(SysBusDevice *s)
3384f95c	270	{
298a9710 DG	271	sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
	272	char *namebuf;
	273	int i;
3384f95c	274	PCIBus *bus;
3384f95c	275
298a9710 DG	276	phb->dtbusname = g_strdup_printf("pci@%" PRIx64, phb->buid);
298a9710 DG	277	namebuf = alloca(strlen(phb->dtbusname) + 32);
3384f95c	278
298a9710 DG	279	/* Initialize memory regions */
298a9710 DG	280	sprintf(namebuf, "%s.mmio", phb->dtbusname);
3384f95c DG	281	memory_region_init(&phb->memspace, namebuf, INT64_MAX);
3384f95c DG	282
298a9710	283	sprintf(namebuf, "%s.mmio-alias", phb->dtbusname);
3384f95c	284	memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
298a9710 DG	285	SPAPR_PCI_MEM_WIN_BUS_OFFSET, phb->mem_win_size);
298a9710 DG	286	memory_region_add_subregion(get_system_memory(), phb->mem_win_addr,
3384f95c DG	287	&phb->memwindow);
3384f95c DG	288
3384f95c DG	289	/* On ppc, we only have MMIO no specific IO space from the CPU
	290	* perspective. In theory we ought to be able to embed the PCI IO
	291	* memory region direction in the system memory space. However,
	292	* if any of the IO BAR subregions use the old_portio mechanism,
	293	* that won't be processed properly unless accessed from the
	294	* system io address space. This hack to bounce things via
	295	* system_io works around the problem until all the users of
	296	* old_portion are updated */
298a9710	297	sprintf(namebuf, "%s.io", phb->dtbusname);
3384f95c DG	298	memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
	299	/* FIXME: fix to support multiple PHBs */
	300	memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
	301
298a9710	302	sprintf(namebuf, "%s.io-alias", phb->dtbusname);
3384f95c DG	303	memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
3384f95c DG	304	namebuf, SPAPR_PCI_IO_WIN_SIZE);
298a9710	305	memory_region_add_subregion(get_system_memory(), phb->io_win_addr,
3384f95c DG	306	&phb->iowindow);
3384f95c DG	307
298a9710 DG	308	bus = pci_register_bus(&phb->busdev.qdev,
	309	phb->busname ? phb->busname : phb->dtbusname,
	310	pci_spapr_set_irq, pci_spapr_map_irq, phb,
	311	&phb->memspace, &phb->iospace,
7fb0bd34	312	PCI_DEVFN(0, 0), PCI_NUM_PINS);
298a9710 DG	313	phb->host_state.bus = bus;
	314
	315	QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
	316
	317	/* Initialize the LSI table */
7fb0bd34	318	for (i = 0; i < PCI_NUM_PINS; i++) {
298a9710 DG	319	qemu_irq qirq;
	320	uint32_t num;
	321
	322	qirq = spapr_allocate_lsi(0, &num);
	323	if (!qirq) {
	324	return -1;
	325	}
	326
	327	phb->lsi_table[i].dt_irq = num;
	328	phb->lsi_table[i].qirq = qirq;
	329	}
	330
	331	return 0;
	332	}
	333
	334	static Property spapr_phb_properties[] = {
	335	DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, 0),
	336	DEFINE_PROP_STRING("busname", sPAPRPHBState, busname),
	337	DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, 0),
	338	DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 0x20000000),
	339	DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, 0),
	340	DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 0x10000),
	341	DEFINE_PROP_END_OF_LIST(),
	342	};
	343
	344	static void spapr_phb_class_init(ObjectClass klass, void data)
	345	{
	346	SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
	347	DeviceClass *dc = DEVICE_CLASS(klass);
	348
	349	sdc->init = spapr_phb_init;
	350	dc->props = spapr_phb_properties;
3384f95c DG	351
	352	spapr_rtas_register("read-pci-config", rtas_read_pci_config);
	353	spapr_rtas_register("write-pci-config", rtas_write_pci_config);
	354	spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
	355	spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
298a9710	356	}
3384f95c	357
298a9710 DG	358	static TypeInfo spapr_phb_info = {
	359	.name = "spapr-pci-host-bridge",
	360	.parent = TYPE_SYS_BUS_DEVICE,
	361	.instance_size = sizeof(sPAPRPHBState),
	362	.class_init = spapr_phb_class_init,
	363	};
	364
	365	void spapr_create_phb(sPAPREnvironment *spapr,
	366	const char *busname, uint64_t buid,
	367	uint64_t mem_win_addr, uint64_t mem_win_size,
	368	uint64_t io_win_addr)
	369	{
	370	DeviceState *dev;
	371
	372	dev = qdev_create(NULL, spapr_phb_info.name);
3384f95c	373
298a9710 DG	374	if (busname) {
	375	qdev_prop_set_string(dev, "busname", g_strdup(busname));
	376	}
	377	qdev_prop_set_uint64(dev, "buid", buid);
	378	qdev_prop_set_uint64(dev, "mem_win_addr", mem_win_addr);
	379	qdev_prop_set_uint64(dev, "mem_win_size", mem_win_size);
	380	qdev_prop_set_uint64(dev, "io_win_addr", io_win_addr);
	381
	382	qdev_init_nofail(dev);
3384f95c DG	383	}
	384
	385	/* Macros to operate with address in OF binding to PCI */
	386	#define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
	387	#define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
	388	#define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
	389	#define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
	390	#define b_ss(x) b_x((x), 24, 2) /* the space code */
	391	#define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
	392	#define b_ddddd(x) b_x((x), 11, 5) /* device number */
	393	#define b_fff(x) b_x((x), 8, 3) /* function number */
	394	#define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
	395
3384f95c DG	396	int spapr_populate_pci_devices(sPAPRPHBState *phb,
	397	uint32_t xics_phandle,
	398	void *fdt)
	399	{
7fb0bd34	400	int bus_off, i, j;
3384f95c	401	char nodename[256];
3384f95c DG	402	uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
	403	struct {
	404	uint32_t hi;
	405	uint64_t child;
	406	uint64_t parent;
	407	uint64_t size;
	408	} __attribute__((packed)) ranges[] = {
	409	{
	410	cpu_to_be32(b_ss(1)), cpu_to_be64(0),
	411	cpu_to_be64(phb->io_win_addr),
	412	cpu_to_be64(memory_region_size(&phb->iospace)),
	413	},
	414	{
	415	cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
	416	cpu_to_be64(phb->mem_win_addr),
	417	cpu_to_be64(memory_region_size(&phb->memwindow)),
	418	},
	419	};
	420	uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
	421	uint32_t interrupt_map_mask[] = {
7fb0bd34 DG	422	cpu_to_be32(b_ddddd(-1)\|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
7fb0bd34 DG	423	uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
3384f95c DG	424
	425	/* Start populating the FDT */
	426	sprintf(nodename, "pci@%" PRIx64, phb->buid);
	427	bus_off = fdt_add_subnode(fdt, 0, nodename);
	428	if (bus_off < 0) {
	429	return bus_off;
	430	}
	431
	432	#define _FDT(exp) \
	433	do { \
	434	int ret = (exp); \
	435	if (ret < 0) { \
	436	return ret; \
	437	} \
	438	} while (0)
	439
	440	/* Write PHB properties */
	441	_FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
	442	_FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
	443	_FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
	444	_FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
	445	_FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
	446	_FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
	447	_FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
	448	_FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
	449	_FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
3f7565c9	450	_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
3384f95c	451
4d8d5467 BH	452	/* Build the interrupt-map, this must matches what is done
	453	* in pci_spapr_map_irq
	454	*/
	455	_FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
	456	&interrupt_map_mask, sizeof(interrupt_map_mask)));
7fb0bd34 DG	457	for (i = 0; i < PCI_SLOT_MAX; i++) {
	458	for (j = 0; j < PCI_NUM_PINS; j++) {
	459	uint32_t irqmap = interrupt_map[iPCI_NUM_PINS + j];
	460	int lsi_num = pci_spapr_swizzle(i, j);
	461
	462	irqmap[0] = cpu_to_be32(b_ddddd(i)\|b_fff(0));
	463	irqmap[1] = 0;
	464	irqmap[2] = 0;
	465	irqmap[3] = cpu_to_be32(j+1);
	466	irqmap[4] = cpu_to_be32(xics_phandle);
	467	irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].dt_irq);
	468	irqmap[6] = cpu_to_be32(0x8);
	469	}
3384f95c	470	}
3384f95c DG	471	/* Write interrupt map */
3384f95c DG	472	_FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
7fb0bd34	473	sizeof(interrupt_map)));
3384f95c DG	474
	475	return 0;
	476	}
298a9710 DG	477
	478	static void register_types(void)
	479	{
	480	type_register_static(&spapr_phb_info);
	481	}
	482	type_init(register_types)