[mirror_qemu.git] / hw / sparc / leon3.c

/*
 * QEMU Leon3 System Emulator
 *
 * Copyright (c) 2010-2019 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/irq.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "hw/qdev-properties.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
#include "sysemu/reset.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "elf.h"
#include "trace.h"
#include "exec/address-spaces.h"

#include "hw/sparc/grlib.h"
#include "hw/misc/grlib_ahb_apb_pnp.h"

/* Default system clock.  */
#define CPU_CLK (40 * 1000 * 1000)

#define LEON3_PROM_FILENAME "u-boot.bin"
#define LEON3_PROM_OFFSET    (0x00000000)
#define LEON3_RAM_OFFSET     (0x40000000)

#define MAX_PILS 16

#define LEON3_UART_OFFSET  (0x80000100)
#define LEON3_UART_IRQ     (3)

#define LEON3_IRQMP_OFFSET (0x80000200)

#define LEON3_TIMER_OFFSET (0x80000300)
#define LEON3_TIMER_IRQ    (6)
#define LEON3_TIMER_COUNT  (2)

#define LEON3_APB_PNP_OFFSET (0x800FF000)
#define LEON3_AHB_PNP_OFFSET (0xFFFFF000)

typedef struct ResetData {
    SPARCCPU *cpu;
    uint32_t  entry;            /* save kernel entry in case of reset */
    target_ulong sp;            /* initial stack pointer */
} ResetData;

static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val)
{
    stl_p(code++, 0x82100000); /* mov %g0, %g1                */
    stl_p(code++, 0x84100000); /* mov %g0, %g2                */
    stl_p(code++, 0x03000000 +
      extract32(addr, 10, 22));
                               /* sethi %hi(addr), %g1        */
    stl_p(code++, 0x82106000 +
      extract32(addr, 0, 10));
                               /* or %g1, addr, %g1           */
    stl_p(code++, 0x05000000 +
      extract32(val, 10, 22));
                               /* sethi %hi(val), %g2         */
    stl_p(code++, 0x8410a000 +
      extract32(val, 0, 10));
                               /* or %g2, val, %g2            */
    stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ]             */

    return code;
}

/*
 * When loading a kernel in RAM the machine is expected to be in a different
 * state (eg: initialized by the bootloader). This little code reproduces
 * this behavior.
 */
static void write_bootloader(CPUSPARCState *env, uint8_t *base,
                             hwaddr kernel_addr)
{
    uint32_t *p = (uint32_t *) base;

    /* Initialize the UARTs                                        */
    /* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */
    p = gen_store_u32(p, 0x80000108, 3);

    /* Initialize the TIMER 0                                      */
    /* *GPTIMER_SCALER_RELOAD = 40 - 1;                            */
    p = gen_store_u32(p, 0x80000304, 39);
    /* *GPTIMER0_COUNTER_RELOAD = 0xFFFE;                          */
    p = gen_store_u32(p, 0x80000314, 0xFFFFFFFE);
    /* *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART;        */
    p = gen_store_u32(p, 0x80000318, 3);

    /* JUMP to the entry point                                     */
    stl_p(p++, 0x82100000); /* mov %g0, %g1 */
    stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
                            /* sethi %hi(kernel_addr), %g1 */
    stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
                            /* or kernel_addr, %g1 */
    stl_p(p++, 0x81c04000); /* jmp  %g1 */
    stl_p(p++, 0x01000000); /* nop */
}

static void main_cpu_reset(void *opaque)
{
    ResetData *s   = (ResetData *)opaque;
    CPUState *cpu = CPU(s->cpu);
    CPUSPARCState  *env = &s->cpu->env;

    cpu_reset(cpu);

    cpu->halted = 0;
    env->pc     = s->entry;
    env->npc    = s->entry + 4;
    env->regbase[6] = s->sp;
}

void leon3_irq_ack(void *irq_manager, int intno)
{
    grlib_irqmp_ack((DeviceState *)irq_manager, intno);
}

/*
 * This device assumes that the incoming 'level' value on the
 * qemu_irq is the interrupt number, not just a simple 0/1 level.
 */
static void leon3_set_pil_in(void *opaque, int n, int level)
{
    CPUSPARCState *env = opaque;
    uint32_t pil_in = level;
    CPUState *cs;

    assert(env != NULL);

    env->pil_in = pil_in;

    if (env->pil_in && (env->interrupt_index == 0 ||
                        (env->interrupt_index & ~15) == TT_EXTINT)) {
        unsigned int i;

        for (i = 15; i > 0; i--) {
            if (env->pil_in & (1 << i)) {
                int old_interrupt = env->interrupt_index;

                env->interrupt_index = TT_EXTINT | i;
                if (old_interrupt != env->interrupt_index) {
                    cs = env_cpu(env);
                    trace_leon3_set_irq(i);
                    cpu_interrupt(cs, CPU_INTERRUPT_HARD);
                }
                break;
            }
        }
    } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
        cs = env_cpu(env);
        trace_leon3_reset_irq(env->interrupt_index & 15);
        env->interrupt_index = 0;
        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
    }
}

static void leon3_generic_hw_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *kernel_filename = machine->kernel_filename;
    SPARCCPU *cpu;
    CPUSPARCState   *env;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *prom = g_new(MemoryRegion, 1);
    int         ret;
    char       *filename;
    qemu_irq   *cpu_irqs = NULL;
    int         bios_size;
    int         prom_size;
    ResetData  *reset_info;
    DeviceState *dev;
    int i;
    AHBPnp *ahb_pnp;
    APBPnp *apb_pnp;

    /* Init CPU */
    cpu = SPARC_CPU(cpu_create(machine->cpu_type));
    env = &cpu->env;

    cpu_sparc_set_id(env, 0);

    /* Reset data */
    reset_info        = g_malloc0(sizeof(ResetData));
    reset_info->cpu   = cpu;
    reset_info->sp    = LEON3_RAM_OFFSET + ram_size;
    qemu_register_reset(main_cpu_reset, reset_info);

    ahb_pnp = GRLIB_AHB_PNP(object_new(TYPE_GRLIB_AHB_PNP));
    object_property_set_bool(OBJECT(ahb_pnp), true, "realized", &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
    grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
                            GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
                            GRLIB_CPU_AREA);

    apb_pnp = GRLIB_APB_PNP(object_new(TYPE_GRLIB_APB_PNP));
    object_property_set_bool(OBJECT(apb_pnp), true, "realized", &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
    grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
                            GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
                            GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);

    /* Allocate IRQ manager */
    dev = qdev_create(NULL, TYPE_GRLIB_IRQMP);
    qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in,
                                        env, "pil", 1);
    qdev_connect_gpio_out_named(dev, "grlib-irq", 0,
                                qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0));
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET);
    env->irq_manager = dev;
    env->qemu_irq_ack = leon3_irq_manager;
    cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq, dev, MAX_PILS);
    grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
                            GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
                            2, 0, GRLIB_APBIO_AREA);

    /* Allocate RAM */
    if (ram_size > 1 * GiB) {
        error_report("Too much memory for this machine: %" PRId64 "MB,"
                     " maximum 1G",
                     ram_size / MiB);
        exit(1);
    }

    memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET,
                                machine->ram);

    /* Allocate BIOS */
    prom_size = 8 * MiB;
    memory_region_init_rom(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
    memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);

    /* Load boot prom */
    if (bios_name == NULL) {
        bios_name = LEON3_PROM_FILENAME;
    }
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);

    if (filename) {
        bios_size = get_image_size(filename);
    } else {
        bios_size = -1;
    }

    if (bios_size > prom_size) {
        error_report("could not load prom '%s': file too big", filename);
        exit(1);
    }

    if (bios_size > 0) {
        ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
        if (ret < 0 || ret > prom_size) {
            error_report("could not load prom '%s'", filename);
            exit(1);
        }
    } else if (kernel_filename == NULL && !qtest_enabled()) {
        error_report("Can't read bios image '%s'", filename
                                                   ? filename
                                                   : LEON3_PROM_FILENAME);
        exit(1);
    }
    g_free(filename);

    /* Can directly load an application. */
    if (kernel_filename != NULL) {
        long     kernel_size;
        uint64_t entry;

        kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
                               &entry, NULL, NULL, NULL,
                               1 /* big endian */, EM_SPARC, 0, 0);
        if (kernel_size < 0) {
            kernel_size = load_uimage(kernel_filename, NULL, &entry,
                                      NULL, NULL, NULL);
        }
        if (kernel_size < 0) {
            error_report("could not load kernel '%s'", kernel_filename);
            exit(1);
        }
        if (bios_size <= 0) {
            /*
             * If there is no bios/monitor just start the application but put
             * the machine in an initialized state through a little
             * bootloader.
             */
            uint8_t *bootloader_entry;

            bootloader_entry = memory_region_get_ram_ptr(prom);
            write_bootloader(env, bootloader_entry, entry);
            env->pc = LEON3_PROM_OFFSET;
            env->npc = LEON3_PROM_OFFSET + 4;
            reset_info->entry = LEON3_PROM_OFFSET;
        }
    }

    /* Allocate timers */
    dev = qdev_create(NULL, TYPE_GRLIB_GPTIMER);
    qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT);
    qdev_prop_set_uint32(dev, "frequency", CPU_CLK);
    qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET);
    for (i = 0; i < LEON3_TIMER_COUNT; i++) {
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
                           cpu_irqs[LEON3_TIMER_IRQ + i]);
    }

    grlib_apb_pnp_add_entry(apb_pnp, LEON3_TIMER_OFFSET, 0xFFF,
                            GRLIB_VENDOR_GAISLER, GRLIB_GPTIMER_DEV,
                            0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA);

    /* Allocate uart */
    if (serial_hd(0)) {
        dev = qdev_create(NULL, TYPE_GRLIB_APB_UART);
        qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
        qdev_init_nofail(dev);
        sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[LEON3_UART_IRQ]);
        grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
                                GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
                                LEON3_UART_IRQ, GRLIB_APBIO_AREA);
    }
}

static void leon3_generic_machine_init(MachineClass *mc)
{
    mc->desc = "Leon-3 generic";
    mc->init = leon3_generic_hw_init;
    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3");
    mc->default_ram_id = "leon3.ram";
}

DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init)
Commit	Line	Data
b04d9890 FC	1	/*
	2	* QEMU Leon3 System Emulator
	3	*
bd30132c	4	* Copyright (c) 2010-2019 AdaCore
b04d9890 FC	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
71e8a915	24
db5ebe5f	25	#include "qemu/osdep.h"
0a2e467b	26	#include "qemu/units.h"
29bd7231	27	#include "qemu/error-report.h"
da34e65c	28	#include "qapi/error.h"
4771d756 PB	29	#include "qemu-common.h"
4771d756 PB	30	#include "cpu.h"
64552b6b	31	#include "hw/irq.h"
1de7afc9	32	#include "qemu/timer.h"
83c9f4ca	33	#include "hw/ptimer.h"
a27bd6c7	34	#include "hw/qdev-properties.h"
9c17d615	35	#include "sysemu/sysemu.h"
77612541	36	#include "sysemu/qtest.h"
71e8a915	37	#include "sysemu/reset.h"
83c9f4ca PB	38	#include "hw/boards.h"
83c9f4ca PB	39	#include "hw/loader.h"
b04d9890 FC	40	#include "elf.h"
b04d9890 FC	41	#include "trace.h"
022c62cb	42	#include "exec/address-spaces.h"
b04d9890	43
0d09e41a	44	#include "hw/sparc/grlib.h"
162abf1a	45	#include "hw/misc/grlib_ahb_apb_pnp.h"
b04d9890 FC	46
	47	/* Default system clock. */
	48	#define CPU_CLK (40 * 1000 * 1000)
	49
bd30132c	50	#define LEON3_PROM_FILENAME "u-boot.bin"
dbed0d2d KF	51	#define LEON3_PROM_OFFSET (0x00000000)
dbed0d2d KF	52	#define LEON3_RAM_OFFSET (0x40000000)
b04d9890 FC	53
	54	#define MAX_PILS 16
	55
b70447aa KF	56	#define LEON3_UART_OFFSET (0x80000100)
	57	#define LEON3_UART_IRQ (3)
	58
ea005dae KF	59	#define LEON3_IRQMP_OFFSET (0x80000200)
ea005dae KF	60
948caec8 KF	61	#define LEON3_TIMER_OFFSET (0x80000300)
	62	#define LEON3_TIMER_IRQ (6)
	63	#define LEON3_TIMER_COUNT (2)
	64
162abf1a KF	65	#define LEON3_APB_PNP_OFFSET (0x800FF000)
	66	#define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
	67
b04d9890	68	typedef struct ResetData {
c537d79c	69	SPARCCPU *cpu;
b04d9890	70	uint32_t entry; /* save kernel entry in case of reset */
c1570e2a	71	target_ulong sp; /* initial stack pointer */
b04d9890 FC	72	} ResetData;
b04d9890 FC	73
dbed0d2d KF	74	static uint32_t gen_store_u32(uint32_t code, hwaddr addr, uint32_t val)
	75	{
	76	stl_p(code++, 0x82100000); /* mov %g0, %g1 */
	77	stl_p(code++, 0x84100000); /* mov %g0, %g2 */
	78	stl_p(code++, 0x03000000 +
	79	extract32(addr, 10, 22));
	80	/* sethi %hi(addr), %g1 */
	81	stl_p(code++, 0x82106000 +
	82	extract32(addr, 0, 10));
	83	/* or %g1, addr, %g1 */
	84	stl_p(code++, 0x05000000 +
	85	extract32(val, 10, 22));
	86	/* sethi %hi(val), %g2 */
	87	stl_p(code++, 0x8410a000 +
	88	extract32(val, 0, 10));
	89	/* or %g2, val, %g2 */
	90	stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */
	91
	92	return code;
	93	}
	94
	95	/*
	96	* When loading a kernel in RAM the machine is expected to be in a different
	97	* state (eg: initialized by the bootloader). This little code reproduces
	98	* this behavior.
	99	*/
	100	static void write_bootloader(CPUSPARCState env, uint8_t base,
	101	hwaddr kernel_addr)
	102	{
	103	uint32_t p = (uint32_t ) base;
	104
	105	/* Initialize the UARTs */
	106	/* UART_CONTROL = UART_RECEIVE_ENABLE \| UART_TRANSMIT_ENABLE; /
	107	p = gen_store_u32(p, 0x80000108, 3);
	108
	109	/* Initialize the TIMER 0 */
	110	/* GPTIMER_SCALER_RELOAD = 40 - 1; /
	111	p = gen_store_u32(p, 0x80000304, 39);
	112	/* GPTIMER0_COUNTER_RELOAD = 0xFFFE; /
	113	p = gen_store_u32(p, 0x80000314, 0xFFFFFFFE);
	114	/* GPTIMER0_CONFIG = GPTIMER_ENABLE \| GPTIMER_RESTART; /
	115	p = gen_store_u32(p, 0x80000318, 3);
	116
	117	/* JUMP to the entry point */
	118	stl_p(p++, 0x82100000); /* mov %g0, %g1 */
	119	stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
	120	/* sethi %hi(kernel_addr), %g1 */
	121	stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
	122	/* or kernel_addr, %g1 */
	123	stl_p(p++, 0x81c04000); /* jmp %g1 */
	124	stl_p(p++, 0x01000000); /* nop */
	125	}
	126
b04d9890 FC	127	static void main_cpu_reset(void *opaque)
	128	{
	129	ResetData s = (ResetData )opaque;
259186a7	130	CPUState *cpu = CPU(s->cpu);
c537d79c	131	CPUSPARCState *env = &s->cpu->env;
b04d9890	132
259186a7	133	cpu_reset(cpu);
b04d9890	134
259186a7	135	cpu->halted = 0;
b04d9890 FC	136	env->pc = s->entry;
b04d9890 FC	137	env->npc = s->entry + 4;
c1570e2a	138	env->regbase[6] = s->sp;
b04d9890 FC	139	}
b04d9890 FC	140
60f356e8	141	void leon3_irq_ack(void *irq_manager, int intno)
b04d9890 FC	142	{
b04d9890 FC	143	grlib_irqmp_ack((DeviceState *)irq_manager, intno);
b04d9890 FC	144	}
b04d9890 FC	145
ab4c072d MAL	146	/*
	147	* This device assumes that the incoming 'level' value on the
	148	* qemu_irq is the interrupt number, not just a simple 0/1 level.
	149	*/
	150	static void leon3_set_pil_in(void *opaque, int n, int level)
b04d9890	151	{
ab4c072d MAL	152	CPUSPARCState *env = opaque;
ab4c072d MAL	153	uint32_t pil_in = level;
d8ed887b	154	CPUState *cs;
b04d9890 FC	155
	156	assert(env != NULL);
	157
	158	env->pil_in = pil_in;
	159
	160	if (env->pil_in && (env->interrupt_index == 0 \|\|
	161	(env->interrupt_index & ~15) == TT_EXTINT)) {
	162	unsigned int i;
	163
	164	for (i = 15; i > 0; i--) {
	165	if (env->pil_in & (1 << i)) {
	166	int old_interrupt = env->interrupt_index;
	167
	168	env->interrupt_index = TT_EXTINT \| i;
	169	if (old_interrupt != env->interrupt_index) {
5a59fbce	170	cs = env_cpu(env);
b04d9890	171	trace_leon3_set_irq(i);
c3affe56	172	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
b04d9890 FC	173	}
	174	break;
	175	}
	176	}
	177	} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
5a59fbce	178	cs = env_cpu(env);
b04d9890 FC	179	trace_leon3_reset_irq(env->interrupt_index & 15);
b04d9890 FC	180	env->interrupt_index = 0;
d8ed887b	181	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
b04d9890 FC	182	}
	183	}
	184
3ef96221	185	static void leon3_generic_hw_init(MachineState *machine)
b04d9890	186	{
3ef96221	187	ram_addr_t ram_size = machine->ram_size;
3ef96221	188	const char *kernel_filename = machine->kernel_filename;
60ad0733	189	SPARCCPU *cpu;
98cec4a2	190	CPUSPARCState *env;
a4911d64	191	MemoryRegion *address_space_mem = get_system_memory();
a4911d64	192	MemoryRegion *prom = g_new(MemoryRegion, 1);
b04d9890 FC	193	int ret;
	194	char *filename;
	195	qemu_irq *cpu_irqs = NULL;
	196	int bios_size;
	197	int prom_size;
	198	ResetData *reset_info;
ea005dae	199	DeviceState *dev;
948caec8	200	int i;
162abf1a KF	201	AHBPnp *ahb_pnp;
162abf1a KF	202	APBPnp *apb_pnp;
b04d9890 FC	203
b04d9890 FC	204	/* Init CPU */
e9135ab3	205	cpu = SPARC_CPU(cpu_create(machine->cpu_type));
60ad0733	206	env = &cpu->env;
b04d9890 FC	207
	208	cpu_sparc_set_id(env, 0);
	209
	210	/* Reset data */
7267c094	211	reset_info = g_malloc0(sizeof(ResetData));
c537d79c	212	reset_info->cpu = cpu;
dbed0d2d	213	reset_info->sp = LEON3_RAM_OFFSET + ram_size;
b04d9890 FC	214	qemu_register_reset(main_cpu_reset, reset_info);
b04d9890 FC	215
162abf1a KF	216	ahb_pnp = GRLIB_AHB_PNP(object_new(TYPE_GRLIB_AHB_PNP));
	217	object_property_set_bool(OBJECT(ahb_pnp), true, "realized", &error_fatal);
	218	sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
	219	grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
	220	GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
	221	GRLIB_CPU_AREA);
	222
	223	apb_pnp = GRLIB_APB_PNP(object_new(TYPE_GRLIB_APB_PNP));
	224	object_property_set_bool(OBJECT(apb_pnp), true, "realized", &error_fatal);
	225	sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
	226	grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
	227	GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
	228	GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);
	229
b04d9890	230	/* Allocate IRQ manager */
ea005dae	231	dev = qdev_create(NULL, TYPE_GRLIB_IRQMP);
e23ae617 MAL	232	qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in,
	233	env, "pil", 1);
	234	qdev_connect_gpio_out_named(dev, "grlib-irq", 0,
	235	qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0));
ea005dae KF	236	qdev_init_nofail(dev);
	237	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET);
	238	env->irq_manager = dev;
60f356e8	239	env->qemu_irq_ack = leon3_irq_manager;
ea005dae	240	cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq, dev, MAX_PILS);
162abf1a KF	241	grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
	242	GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
	243	2, 0, GRLIB_APBIO_AREA);
b04d9890 FC	244
b04d9890 FC	245	/* Allocate RAM */
0a2e467b PMD	246	if (ram_size > 1 * GiB) {
	247	error_report("Too much memory for this machine: %" PRId64 "MB,"
	248	" maximum 1G",
	249	ram_size / MiB);
b04d9890 FC	250	exit(1);
	251	}
	252
fe3e7b71 IM	253	memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET,
fe3e7b71 IM	254	machine->ram);
b04d9890 FC	255
b04d9890 FC	256	/* Allocate BIOS */
0a2e467b	257	prom_size = 8 * MiB;
ec7b2175	258	memory_region_init_rom(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
dbed0d2d	259	memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
b04d9890 FC	260
	261	/* Load boot prom */
	262	if (bios_name == NULL) {
bd30132c	263	bios_name = LEON3_PROM_FILENAME;
b04d9890 FC	264	}
	265	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
	266
47dc0ec5 PM	267	if (filename) {
	268	bios_size = get_image_size(filename);
	269	} else {
	270	bios_size = -1;
	271	}
b04d9890 FC	272
b04d9890 FC	273	if (bios_size > prom_size) {
29bd7231	274	error_report("could not load prom '%s': file too big", filename);
b04d9890 FC	275	exit(1);
	276	}
	277
	278	if (bios_size > 0) {
dbed0d2d	279	ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
b04d9890	280	if (ret < 0 \|\| ret > prom_size) {
29bd7231	281	error_report("could not load prom '%s'", filename);
b04d9890 FC	282	exit(1);
b04d9890 FC	283	}
77612541	284	} else if (kernel_filename == NULL && !qtest_enabled()) {
bd30132c KF	285	error_report("Can't read bios image '%s'", filename
	286	? filename
	287	: LEON3_PROM_FILENAME);
b04d9890 FC	288	exit(1);
b04d9890 FC	289	}
d71cdbfd	290	g_free(filename);
b04d9890 FC	291
	292	/* Can directly load an application. */
	293	if (kernel_filename != NULL) {
	294	long kernel_size;
	295	uint64_t entry;
	296
4366e1db	297	kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
6cdda0ff	298	&entry, NULL, NULL, NULL,
7ef295ea	299	1 /* big endian */, EM_SPARC, 0, 0);
9176a580 PMD	300	if (kernel_size < 0) {
	301	kernel_size = load_uimage(kernel_filename, NULL, &entry,
	302	NULL, NULL, NULL);
	303	}
b04d9890	304	if (kernel_size < 0) {
29bd7231	305	error_report("could not load kernel '%s'", kernel_filename);
b04d9890 FC	306	exit(1);
	307	}
	308	if (bios_size <= 0) {
dbed0d2d KF	309	/*
	310	* If there is no bios/monitor just start the application but put
	311	* the machine in an initialized state through a little
	312	* bootloader.
	313	*/
	314	uint8_t *bootloader_entry;
	315
	316	bootloader_entry = memory_region_get_ram_ptr(prom);
	317	write_bootloader(env, bootloader_entry, entry);
	318	env->pc = LEON3_PROM_OFFSET;
	319	env->npc = LEON3_PROM_OFFSET + 4;
	320	reset_info->entry = LEON3_PROM_OFFSET;
b04d9890 FC	321	}
	322	}
	323
	324	/* Allocate timers */
948caec8 KF	325	dev = qdev_create(NULL, TYPE_GRLIB_GPTIMER);
	326	qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT);
	327	qdev_prop_set_uint32(dev, "frequency", CPU_CLK);
	328	qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ);
	329	qdev_init_nofail(dev);
	330
	331	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET);
	332	for (i = 0; i < LEON3_TIMER_COUNT; i++) {
	333	sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
	334	cpu_irqs[LEON3_TIMER_IRQ + i]);
	335	}
b04d9890	336
162abf1a KF	337	grlib_apb_pnp_add_entry(apb_pnp, LEON3_TIMER_OFFSET, 0xFFF,
	338	GRLIB_VENDOR_GAISLER, GRLIB_GPTIMER_DEV,
	339	0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA);
	340
b04d9890	341	/* Allocate uart */
9bca0edb	342	if (serial_hd(0)) {
b70447aa KF	343	dev = qdev_create(NULL, TYPE_GRLIB_APB_UART);
	344	qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
	345	qdev_init_nofail(dev);
	346	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
	347	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[LEON3_UART_IRQ]);
162abf1a KF	348	grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
	349	GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
	350	LEON3_UART_IRQ, GRLIB_APBIO_AREA);
b04d9890 FC	351	}
	352	}
	353
e264d29d	354	static void leon3_generic_machine_init(MachineClass *mc)
b04d9890	355	{
e264d29d EH	356	mc->desc = "Leon-3 generic";
e264d29d EH	357	mc->init = leon3_generic_hw_init;
e9135ab3	358	mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3");
fe3e7b71	359	mc->default_ram_id = "leon3.ram";
b04d9890 FC	360	}
b04d9890 FC	361
e264d29d	362	DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init)