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420557e8 FB |
1 | /* |
2 | * QEMU Sun4m System Emulator | |
3 | * | |
b81b3b10 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
420557e8 FB |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "vl.h" | |
420557e8 FB |
25 | |
26 | #define KERNEL_LOAD_ADDR 0x00004000 | |
b6f479d3 | 27 | #define CMDLINE_ADDR 0x007ff000 |
713c45fa | 28 | #define INITRD_LOAD_ADDR 0x00800000 |
e80cfcfc | 29 | #define PROM_ADDR 0xffd00000 |
8d5f07fa FB |
30 | #define PROM_FILENAMEB "proll.bin" |
31 | #define PROM_FILENAMEE "proll.elf" | |
e80cfcfc | 32 | #define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */ |
420557e8 FB |
33 | #define PHYS_JJ_IDPROM_OFF 0x1FD8 |
34 | #define PHYS_JJ_EEPROM_SIZE 0x2000 | |
e80cfcfc FB |
35 | // IRQs are not PIL ones, but master interrupt controller register |
36 | // bits | |
37 | #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */ | |
6f7e9aec | 38 | #define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */ |
3475187d | 39 | #define PHYS_JJ_SLAVIO 0x70000000 /* Slavio base */ |
6f7e9aec FB |
40 | #define PHYS_JJ_ESPDMA 0x78400000 /* ESP DMA controller */ |
41 | #define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */ | |
42 | #define PHYS_JJ_ESP_IRQ 18 | |
e80cfcfc FB |
43 | #define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */ |
44 | #define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */ | |
45 | #define PHYS_JJ_LE_IRQ 16 | |
46 | #define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */ | |
47 | #define PHYS_JJ_CLOCK_IRQ 7 | |
48 | #define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */ | |
49 | #define PHYS_JJ_CLOCK1_IRQ 19 | |
50 | #define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */ | |
8d5f07fa | 51 | #define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */ |
e80cfcfc FB |
52 | #define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */ |
53 | #define PHYS_JJ_MS_KBD_IRQ 14 | |
54 | #define PHYS_JJ_SER 0x71100000 /* Serial */ | |
55 | #define PHYS_JJ_SER_IRQ 15 | |
e80cfcfc FB |
56 | #define PHYS_JJ_FDC 0x71400000 /* Floppy */ |
57 | #define PHYS_JJ_FLOPPY_IRQ 22 | |
3475187d | 58 | #define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */ |
ba3c64fb | 59 | #define MAX_CPUS 16 |
420557e8 FB |
60 | |
61 | /* TSC handling */ | |
62 | ||
63 | uint64_t cpu_get_tsc() | |
64 | { | |
65 | return qemu_get_clock(vm_clock); | |
66 | } | |
67 | ||
6f7e9aec FB |
68 | int DMA_get_channel_mode (int nchan) |
69 | { | |
70 | return 0; | |
71 | } | |
72 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
73 | { | |
74 | return 0; | |
75 | } | |
76 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
77 | { | |
78 | return 0; | |
79 | } | |
80 | void DMA_hold_DREQ (int nchan) {} | |
81 | void DMA_release_DREQ (int nchan) {} | |
82 | void DMA_schedule(int nchan) {} | |
83 | void DMA_run (void) {} | |
84 | void DMA_init (int high_page_enable) {} | |
85 | void DMA_register_channel (int nchan, | |
86 | DMA_transfer_handler transfer_handler, | |
87 | void *opaque) | |
88 | { | |
89 | } | |
90 | ||
819385c5 | 91 | static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value) |
6f7e9aec | 92 | { |
819385c5 FB |
93 | m48t59_write(nvram, addr++, (value >> 8) & 0xff); |
94 | m48t59_write(nvram, addr++, value & 0xff); | |
6f7e9aec FB |
95 | } |
96 | ||
819385c5 | 97 | static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value) |
6f7e9aec | 98 | { |
819385c5 FB |
99 | m48t59_write(nvram, addr++, value >> 24); |
100 | m48t59_write(nvram, addr++, (value >> 16) & 0xff); | |
101 | m48t59_write(nvram, addr++, (value >> 8) & 0xff); | |
102 | m48t59_write(nvram, addr++, value & 0xff); | |
6f7e9aec FB |
103 | } |
104 | ||
819385c5 | 105 | static void nvram_set_string (m48t59_t *nvram, uint32_t addr, |
6f7e9aec FB |
106 | const unsigned char *str, uint32_t max) |
107 | { | |
108 | unsigned int i; | |
109 | ||
110 | for (i = 0; i < max && str[i] != '\0'; i++) { | |
819385c5 | 111 | m48t59_write(nvram, addr + i, str[i]); |
6f7e9aec | 112 | } |
819385c5 | 113 | m48t59_write(nvram, addr + max - 1, '\0'); |
6f7e9aec | 114 | } |
420557e8 | 115 | |
819385c5 | 116 | static m48t59_t *nvram; |
420557e8 | 117 | |
6f7e9aec FB |
118 | extern int nographic; |
119 | ||
819385c5 | 120 | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
6f7e9aec FB |
121 | int boot_device, uint32_t RAM_size, |
122 | uint32_t kernel_size, | |
123 | int width, int height, int depth) | |
e80cfcfc FB |
124 | { |
125 | unsigned char tmp = 0; | |
126 | int i, j; | |
127 | ||
6f7e9aec FB |
128 | // Try to match PPC NVRAM |
129 | nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); | |
130 | nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ | |
131 | // NVRAM_size, arch not applicable | |
ba3c64fb FB |
132 | m48t59_write(nvram, 0x2D, smp_cpus & 0xff); |
133 | m48t59_write(nvram, 0x2E, 0); | |
819385c5 | 134 | m48t59_write(nvram, 0x2F, nographic & 0xff); |
6f7e9aec | 135 | nvram_set_lword(nvram, 0x30, RAM_size); |
819385c5 | 136 | m48t59_write(nvram, 0x34, boot_device & 0xff); |
6f7e9aec FB |
137 | nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR); |
138 | nvram_set_lword(nvram, 0x3C, kernel_size); | |
b6f479d3 | 139 | if (cmdline) { |
b6f479d3 | 140 | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
6f7e9aec FB |
141 | nvram_set_lword(nvram, 0x40, CMDLINE_ADDR); |
142 | nvram_set_lword(nvram, 0x44, strlen(cmdline)); | |
b6f479d3 | 143 | } |
6f7e9aec FB |
144 | // initrd_image, initrd_size passed differently |
145 | nvram_set_word(nvram, 0x54, width); | |
146 | nvram_set_word(nvram, 0x56, height); | |
147 | nvram_set_word(nvram, 0x58, depth); | |
b6f479d3 | 148 | |
6f7e9aec | 149 | // Sun4m specific use |
e80cfcfc | 150 | i = 0x1fd8; |
819385c5 FB |
151 | m48t59_write(nvram, i++, 0x01); |
152 | m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */ | |
e80cfcfc | 153 | j = 0; |
819385c5 FB |
154 | m48t59_write(nvram, i++, macaddr[j++]); |
155 | m48t59_write(nvram, i++, macaddr[j++]); | |
156 | m48t59_write(nvram, i++, macaddr[j++]); | |
157 | m48t59_write(nvram, i++, macaddr[j++]); | |
158 | m48t59_write(nvram, i++, macaddr[j++]); | |
159 | m48t59_write(nvram, i, macaddr[j]); | |
e80cfcfc FB |
160 | |
161 | /* Calculate checksum */ | |
162 | for (i = 0x1fd8; i < 0x1fe7; i++) { | |
819385c5 | 163 | tmp ^= m48t59_read(nvram, i); |
e80cfcfc | 164 | } |
819385c5 | 165 | m48t59_write(nvram, 0x1fe7, tmp); |
e80cfcfc FB |
166 | } |
167 | ||
168 | static void *slavio_intctl; | |
169 | ||
170 | void pic_info() | |
171 | { | |
172 | slavio_pic_info(slavio_intctl); | |
173 | } | |
174 | ||
175 | void irq_info() | |
176 | { | |
177 | slavio_irq_info(slavio_intctl); | |
178 | } | |
179 | ||
180 | void pic_set_irq(int irq, int level) | |
181 | { | |
182 | slavio_pic_set_irq(slavio_intctl, irq, level); | |
183 | } | |
184 | ||
ba3c64fb FB |
185 | void pic_set_irq_cpu(int irq, int level, unsigned int cpu) |
186 | { | |
187 | slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu); | |
188 | } | |
189 | ||
e80cfcfc FB |
190 | static void *tcx; |
191 | ||
192 | void vga_update_display() | |
193 | { | |
194 | tcx_update_display(tcx); | |
195 | } | |
196 | ||
197 | void vga_invalidate_display() | |
198 | { | |
199 | tcx_invalidate_display(tcx); | |
200 | } | |
201 | ||
202 | void vga_screen_dump(const char *filename) | |
203 | { | |
204 | tcx_screen_dump(tcx, filename); | |
205 | } | |
206 | ||
207 | static void *iommu; | |
208 | ||
209 | uint32_t iommu_translate(uint32_t addr) | |
210 | { | |
211 | return iommu_translate_local(iommu, addr); | |
212 | } | |
213 | ||
3475187d FB |
214 | static void *slavio_misc; |
215 | ||
216 | void qemu_system_powerdown(void) | |
217 | { | |
218 | slavio_set_power_fail(slavio_misc, 1); | |
219 | } | |
220 | ||
c68ea704 FB |
221 | static void main_cpu_reset(void *opaque) |
222 | { | |
223 | CPUState *env = opaque; | |
224 | cpu_reset(env); | |
225 | } | |
226 | ||
420557e8 | 227 | /* Sun4m hardware initialisation */ |
c0e564d5 FB |
228 | static void sun4m_init(int ram_size, int vga_ram_size, int boot_device, |
229 | DisplayState *ds, const char **fd_filename, int snapshot, | |
230 | const char *kernel_filename, const char *kernel_cmdline, | |
231 | const char *initrd_filename) | |
420557e8 | 232 | { |
ba3c64fb | 233 | CPUState *env, *envs[MAX_CPUS]; |
420557e8 | 234 | char buf[1024]; |
8d5f07fa | 235 | int ret, linux_boot; |
713c45fa | 236 | unsigned int i; |
6f7e9aec | 237 | long vram_size = 0x100000, prom_offset, initrd_size, kernel_size; |
420557e8 FB |
238 | |
239 | linux_boot = (kernel_filename != NULL); | |
240 | ||
ba3c64fb FB |
241 | /* init CPUs */ |
242 | for(i = 0; i < smp_cpus; i++) { | |
243 | env = cpu_init(); | |
244 | envs[i] = env; | |
245 | if (i != 0) | |
246 | env->halted = 1; | |
247 | register_savevm("cpu", i, 3, cpu_save, cpu_load, env); | |
248 | qemu_register_reset(main_cpu_reset, env); | |
249 | } | |
420557e8 FB |
250 | /* allocate RAM */ |
251 | cpu_register_physical_memory(0, ram_size, 0); | |
420557e8 | 252 | |
e80cfcfc FB |
253 | iommu = iommu_init(PHYS_JJ_IOMMU); |
254 | slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); | |
ba3c64fb FB |
255 | for(i = 0; i < smp_cpus; i++) { |
256 | slavio_intctl_set_cpu(slavio_intctl, i, envs[i]); | |
257 | } | |
258 | ||
6f7e9aec | 259 | tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height); |
8d5f07fa | 260 | lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA); |
819385c5 | 261 | nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8); |
ba3c64fb FB |
262 | for (i = 0; i < MAX_CPUS; i++) { |
263 | slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i); | |
264 | } | |
265 | slavio_timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ, 2, (unsigned int)-1); | |
e80cfcfc | 266 | slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
b81b3b10 FB |
267 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
268 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
269 | slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]); | |
e80cfcfc | 270 | fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table); |
6f7e9aec | 271 | esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA); |
3475187d | 272 | slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ); |
420557e8 | 273 | |
e80cfcfc FB |
274 | prom_offset = ram_size + vram_size; |
275 | ||
276 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE); | |
277 | ret = load_elf(buf, phys_ram_base + prom_offset); | |
278 | if (ret < 0) { | |
8d5f07fa | 279 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB); |
e80cfcfc FB |
280 | ret = load_image(buf, phys_ram_base + prom_offset); |
281 | } | |
282 | if (ret < 0) { | |
283 | fprintf(stderr, "qemu: could not load prom '%s'\n", | |
284 | buf); | |
285 | exit(1); | |
286 | } | |
287 | cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, | |
288 | prom_offset | IO_MEM_ROM); | |
289 | ||
6f7e9aec | 290 | kernel_size = 0; |
e80cfcfc | 291 | if (linux_boot) { |
6f7e9aec FB |
292 | kernel_size = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
293 | if (kernel_size < 0) | |
294 | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
295 | if (kernel_size < 0) | |
296 | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
297 | if (kernel_size < 0) { | |
420557e8 | 298 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
e80cfcfc FB |
299 | kernel_filename); |
300 | exit(1); | |
420557e8 | 301 | } |
713c45fa FB |
302 | |
303 | /* load initrd */ | |
304 | initrd_size = 0; | |
305 | if (initrd_filename) { | |
306 | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); | |
307 | if (initrd_size < 0) { | |
308 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
309 | initrd_filename); | |
310 | exit(1); | |
311 | } | |
312 | } | |
313 | if (initrd_size > 0) { | |
314 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
315 | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) | |
316 | == 0x48647253) { // HdrS | |
317 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
318 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
319 | break; | |
320 | } | |
321 | } | |
322 | } | |
420557e8 | 323 | } |
6f7e9aec | 324 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth); |
420557e8 | 325 | } |
c0e564d5 FB |
326 | |
327 | QEMUMachine sun4m_machine = { | |
328 | "sun4m", | |
329 | "Sun4m platform", | |
330 | sun4m_init, | |
331 | }; |