[mirror_qemu.git] / hw / timer / pxa2xx_timer.c

/*
 * Intel XScale PXA255/270 OS Timers.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"

#define OSMR0	0x00
#define OSMR1	0x04
#define OSMR2	0x08
#define OSMR3	0x0c
#define OSMR4	0x80
#define OSMR5	0x84
#define OSMR6	0x88
#define OSMR7	0x8c
#define OSMR8	0x90
#define OSMR9	0x94
#define OSMR10	0x98
#define OSMR11	0x9c
#define OSCR	0x10	/* OS Timer Count */
#define OSCR4	0x40
#define OSCR5	0x44
#define OSCR6	0x48
#define OSCR7	0x4c
#define OSCR8	0x50
#define OSCR9	0x54
#define OSCR10	0x58
#define OSCR11	0x5c
#define OSSR	0x14	/* Timer status register */
#define OWER	0x18
#define OIER	0x1c	/* Interrupt enable register  3-0 to E3-E0 */
#define OMCR4	0xc0	/* OS Match Control registers */
#define OMCR5	0xc4
#define OMCR6	0xc8
#define OMCR7	0xcc
#define OMCR8	0xd0
#define OMCR9	0xd4
#define OMCR10	0xd8
#define OMCR11	0xdc
#define OSNR	0x20

#define PXA25X_FREQ	3686400	/* 3.6864 MHz */
#define PXA27X_FREQ	3250000	/* 3.25 MHz */

static int pxa2xx_timer4_freq[8] = {
    [0] = 0,
    [1] = 32768,
    [2] = 1000,
    [3] = 1,
    [4] = 1000000,
    /* [5] is the "Externally supplied clock".  Assign if necessary.  */
    [5 ... 7] = 0,
};

#define TYPE_PXA2XX_TIMER "pxa2xx-timer"
#define PXA2XX_TIMER(obj) \
    OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)

typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;

typedef struct {
    uint32_t value;
    qemu_irq irq;
    QEMUTimer *qtimer;
    int num;
    PXA2xxTimerInfo *info;
} PXA2xxTimer0;

typedef struct {
    PXA2xxTimer0 tm;
    int32_t oldclock;
    int32_t clock;
    uint64_t lastload;
    uint32_t freq;
    uint32_t control;
} PXA2xxTimer4;

struct PXA2xxTimerInfo {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint32_t flags;

    int32_t clock;
    int32_t oldclock;
    uint64_t lastload;
    uint32_t freq;
    PXA2xxTimer0 timer[4];
    uint32_t events;
    uint32_t irq_enabled;
    uint32_t reset3;
    uint32_t snapshot;

    qemu_irq irq4;
    PXA2xxTimer4 tm4[8];
};

#define PXA2XX_TIMER_HAVE_TM4	0

static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
{
    return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
}

static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int i;
    uint32_t now_vm;
    uint64_t new_qemu;

    now_vm = s->clock +
            muldiv64(now_qemu - s->lastload, s->freq, NANOSECONDS_PER_SECOND);

    for (i = 0; i < 4; i ++) {
        new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
                        NANOSECONDS_PER_SECOND, s->freq);
        timer_mod(s->timer[i].qtimer, new_qemu);
    }
}

static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    uint32_t now_vm;
    uint64_t new_qemu;
    static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
    int counter;

    if (s->tm4[n].control & (1 << 7))
        counter = n;
    else
        counter = counters[n];

    if (!s->tm4[counter].freq) {
        timer_del(s->tm4[n].tm.qtimer);
        return;
    }

    now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
                    s->tm4[counter].lastload,
                    s->tm4[counter].freq, NANOSECONDS_PER_SECOND);

    new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
                    NANOSECONDS_PER_SECOND, s->tm4[counter].freq);
    timer_mod(s->tm4[n].tm.qtimer, new_qemu);
}

static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
                                  unsigned size)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int tm = 0;

    switch (offset) {
    case OSMR3:  tm ++;
        /* fall through */
    case OSMR2:  tm ++;
        /* fall through */
    case OSMR1:  tm ++;
        /* fall through */
    case OSMR0:
        return s->timer[tm].value;
    case OSMR11: tm ++;
        /* fall through */
    case OSMR10: tm ++;
        /* fall through */
    case OSMR9:  tm ++;
        /* fall through */
    case OSMR8:  tm ++;
        /* fall through */
    case OSMR7:  tm ++;
        /* fall through */
    case OSMR6:  tm ++;
        /* fall through */
    case OSMR5:  tm ++;
        /* fall through */
    case OSMR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        return s->tm4[tm].tm.value;
    case OSCR:
        return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
                        s->lastload, s->freq, NANOSECONDS_PER_SECOND);
    case OSCR11: tm ++;
        /* fall through */
    case OSCR10: tm ++;
        /* fall through */
    case OSCR9:  tm ++;
        /* fall through */
    case OSCR8:  tm ++;
        /* fall through */
    case OSCR7:  tm ++;
        /* fall through */
    case OSCR6:  tm ++;
        /* fall through */
    case OSCR5:  tm ++;
        /* fall through */
    case OSCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;

        if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
            if (s->tm4[tm - 1].freq)
                s->snapshot = s->tm4[tm - 1].clock + muldiv64(
                                qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
                                s->tm4[tm - 1].lastload,
                                s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND);
            else
                s->snapshot = s->tm4[tm - 1].clock;
        }

        if (!s->tm4[tm].freq)
            return s->tm4[tm].clock;
        return s->tm4[tm].clock +
            muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
                     s->tm4[tm].lastload, s->tm4[tm].freq,
                     NANOSECONDS_PER_SECOND);
    case OIER:
        return s->irq_enabled;
    case OSSR:	/* Status register */
        return s->events;
    case OWER:
        return s->reset3;
    case OMCR11: tm ++;
        /* fall through */
    case OMCR10: tm ++;
        /* fall through */
    case OMCR9:  tm ++;
        /* fall through */
    case OMCR8:  tm ++;
        /* fall through */
    case OMCR7:  tm ++;
        /* fall through */
    case OMCR6:  tm ++;
        /* fall through */
    case OMCR5:  tm ++;
        /* fall through */
    case OMCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        return s->tm4[tm].control;
    case OSNR:
        return s->snapshot;
    default:
    badreg:
        hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
    }

    return 0;
}

static void pxa2xx_timer_write(void *opaque, hwaddr offset,
                               uint64_t value, unsigned size)
{
    int i, tm = 0;
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;

    switch (offset) {
    case OSMR3:  tm ++;
        /* fall through */
    case OSMR2:  tm ++;
        /* fall through */
    case OSMR1:  tm ++;
        /* fall through */
    case OSMR0:
        s->timer[tm].value = value;
        pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
        break;
    case OSMR11: tm ++;
        /* fall through */
    case OSMR10: tm ++;
        /* fall through */
    case OSMR9:  tm ++;
        /* fall through */
    case OSMR8:  tm ++;
        /* fall through */
    case OSMR7:  tm ++;
        /* fall through */
    case OSMR6:  tm ++;
        /* fall through */
    case OSMR5:  tm ++;
        /* fall through */
    case OSMR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].tm.value = value;
        pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
        break;
    case OSCR:
        s->oldclock = s->clock;
        s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
        s->clock = value;
        pxa2xx_timer_update(s, s->lastload);
        break;
    case OSCR11: tm ++;
        /* fall through */
    case OSCR10: tm ++;
        /* fall through */
    case OSCR9:  tm ++;
        /* fall through */
    case OSCR8:  tm ++;
        /* fall through */
    case OSCR7:  tm ++;
        /* fall through */
    case OSCR6:  tm ++;
        /* fall through */
    case OSCR5:  tm ++;
        /* fall through */
    case OSCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].oldclock = s->tm4[tm].clock;
        s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
        s->tm4[tm].clock = value;
        pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
        break;
    case OIER:
        s->irq_enabled = value & 0xfff;
        break;
    case OSSR:	/* Status register */
        value &= s->events;
        s->events &= ~value;
        for (i = 0; i < 4; i ++, value >>= 1)
            if (value & 1)
                qemu_irq_lower(s->timer[i].irq);
        if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
            qemu_irq_lower(s->irq4);
        break;
    case OWER:	/* XXX: Reset on OSMR3 match? */
        s->reset3 = value;
        break;
    case OMCR7:  tm ++;
        /* fall through */
    case OMCR6:  tm ++;
        /* fall through */
    case OMCR5:  tm ++;
        /* fall through */
    case OMCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].control = value & 0x0ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || tm == 0)
            s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
        }
        break;
    case OMCR11: tm ++;
        /* fall through */
    case OMCR10: tm ++;
        /* fall through */
    case OMCR9:  tm ++;
        /* fall through */
    case OMCR8:  tm += 4;
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].control = value & 0x3ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || !(tm & 1))
            s->tm4[tm].freq =
                    pxa2xx_timer4_freq[(value & (1 << 8)) ?  0 : (value & 7)];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
        }
        break;
    default:
    badreg:
        hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
    }
}

static const MemoryRegionOps pxa2xx_timer_ops = {
    .read = pxa2xx_timer_read,
    .write = pxa2xx_timer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pxa2xx_timer_tick(void *opaque)
{
    PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
    PXA2xxTimerInfo *i = t->info;

    if (i->irq_enabled & (1 << t->num)) {
        i->events |= 1 << t->num;
        qemu_irq_raise(t->irq);
    }

    if (t->num == 3)
        if (i->reset3 & 1) {
            i->reset3 = 0;
            qemu_system_reset_request();
        }
}

static void pxa2xx_timer_tick4(void *opaque)
{
    PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
    PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;

    pxa2xx_timer_tick(&t->tm);
    if (t->control & (1 << 3))
        t->clock = 0;
    if (t->control & (1 << 6))
        pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
    if (i->events & 0xff0)
        qemu_irq_raise(i->irq4);
}

static int pxa25x_timer_post_load(void *opaque, int version_id)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int64_t now;
    int i;

    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    pxa2xx_timer_update(s, now);

    if (pxa2xx_timer_has_tm4(s))
        for (i = 0; i < 8; i ++)
            pxa2xx_timer_update4(s, now, i);

    return 0;
}

static void pxa2xx_timer_init(Object *obj)
{
    PXA2xxTimerInfo *s = PXA2XX_TIMER(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);

    s->irq_enabled = 0;
    s->oldclock = 0;
    s->clock = 0;
    s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    s->reset3 = 0;

    memory_region_init_io(&s->iomem, obj, &pxa2xx_timer_ops, s,
                          "pxa2xx-timer", 0x00001000);
    sysbus_init_mmio(dev, &s->iomem);
}

static void pxa2xx_timer_realize(DeviceState *dev, Error **errp)
{
    PXA2xxTimerInfo *s = PXA2XX_TIMER(dev);
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    int i;

    for (i = 0; i < 4; i ++) {
        s->timer[i].value = 0;
        sysbus_init_irq(sbd, &s->timer[i].irq);
        s->timer[i].info = s;
        s->timer[i].num = i;
        s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                          pxa2xx_timer_tick, &s->timer[i]);
    }

    if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
        sysbus_init_irq(sbd, &s->irq4);

        for (i = 0; i < 8; i ++) {
            s->tm4[i].tm.value = 0;
            s->tm4[i].tm.info = s;
            s->tm4[i].tm.num = i + 4;
            s->tm4[i].freq = 0;
            s->tm4[i].control = 0x0;
            s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                               pxa2xx_timer_tick4, &s->tm4[i]);
        }
    }
}

static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
    .name = "pxa2xx_timer0",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(value, PXA2xxTimer0),
        VMSTATE_END_OF_LIST(),
    },
};

static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
    .name = "pxa2xx_timer4",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
                        vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
        VMSTATE_INT32(oldclock, PXA2xxTimer4),
        VMSTATE_INT32(clock, PXA2xxTimer4),
        VMSTATE_UINT64(lastload, PXA2xxTimer4),
        VMSTATE_UINT32(freq, PXA2xxTimer4),
        VMSTATE_UINT32(control, PXA2xxTimer4),
        VMSTATE_END_OF_LIST(),
    },
};

static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
{
    return pxa2xx_timer_has_tm4(opaque);
}

static const VMStateDescription vmstate_pxa2xx_timer_regs = {
    .name = "pxa2xx_timer",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = pxa25x_timer_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(clock, PXA2xxTimerInfo),
        VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
        VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
        VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
                        vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
        VMSTATE_UINT32(events, PXA2xxTimerInfo),
        VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
        VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
        VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
        VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
                        pxa2xx_timer_has_tm4_test, 0,
                        vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
        VMSTATE_END_OF_LIST(),
    }
};

static Property pxa25x_timer_dev_properties[] = {
    DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
    DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
                    PXA2XX_TIMER_HAVE_TM4, false),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA25x timer";
    dc->props = pxa25x_timer_dev_properties;
}

static const TypeInfo pxa25x_timer_dev_info = {
    .name          = "pxa25x-timer",
    .parent        = TYPE_PXA2XX_TIMER,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .class_init    = pxa25x_timer_dev_class_init,
};

static Property pxa27x_timer_dev_properties[] = {
    DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
    DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
                    PXA2XX_TIMER_HAVE_TM4, true),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa27x_timer_dev_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA27x timer";
    dc->props = pxa27x_timer_dev_properties;
}

static const TypeInfo pxa27x_timer_dev_info = {
    .name          = "pxa27x-timer",
    .parent        = TYPE_PXA2XX_TIMER,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .class_init    = pxa27x_timer_dev_class_init,
};

static void pxa2xx_timer_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize  = pxa2xx_timer_realize;
    dc->vmsd = &vmstate_pxa2xx_timer_regs;
}

static const TypeInfo pxa2xx_timer_type_info = {
    .name          = TYPE_PXA2XX_TIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .instance_init = pxa2xx_timer_init,
    .abstract      = true,
    .class_init    = pxa2xx_timer_class_init,
};

static void pxa2xx_timer_register_types(void)
{
    type_register_static(&pxa2xx_timer_type_info);
    type_register_static(&pxa25x_timer_dev_info);
    type_register_static(&pxa27x_timer_dev_info);
}

type_init(pxa2xx_timer_register_types)
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 OS Timers.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	*
8e31bf38	7	* This code is licensed under the GPL.
a171fe39 AZ	8	*/
a171fe39 AZ	9
8ef94f0b	10	#include "qemu/osdep.h"
83c9f4ca	11	#include "hw/hw.h"
1de7afc9	12	#include "qemu/timer.h"
9c17d615	13	#include "sysemu/sysemu.h"
0d09e41a	14	#include "hw/arm/pxa.h"
83c9f4ca	15	#include "hw/sysbus.h"
a171fe39 AZ	16
	17	#define OSMR0 0x00
	18	#define OSMR1 0x04
	19	#define OSMR2 0x08
	20	#define OSMR3 0x0c
	21	#define OSMR4 0x80
	22	#define OSMR5 0x84
	23	#define OSMR6 0x88
	24	#define OSMR7 0x8c
	25	#define OSMR8 0x90
	26	#define OSMR9 0x94
	27	#define OSMR10 0x98
	28	#define OSMR11 0x9c
	29	#define OSCR 0x10 /* OS Timer Count */
	30	#define OSCR4 0x40
	31	#define OSCR5 0x44
	32	#define OSCR6 0x48
	33	#define OSCR7 0x4c
	34	#define OSCR8 0x50
	35	#define OSCR9 0x54
	36	#define OSCR10 0x58
	37	#define OSCR11 0x5c
	38	#define OSSR 0x14 /* Timer status register */
	39	#define OWER 0x18
	40	#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
	41	#define OMCR4 0xc0 /* OS Match Control registers */
	42	#define OMCR5 0xc4
	43	#define OMCR6 0xc8
	44	#define OMCR7 0xcc
	45	#define OMCR8 0xd0
	46	#define OMCR9 0xd4
	47	#define OMCR10 0xd8
	48	#define OMCR11 0xdc
	49	#define OSNR 0x20
	50
	51	#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
	52	#define PXA27X_FREQ 3250000 /* 3.25 MHz */
	53
	54	static int pxa2xx_timer4_freq[8] = {
	55	[0] = 0,
	56	[1] = 32768,
	57	[2] = 1000,
	58	[3] = 1,
	59	[4] = 1000000,
	60	/* [5] is the "Externally supplied clock". Assign if necessary. */
	61	[5 ... 7] = 0,
	62	};
	63
feea4361 AF	64	#define TYPE_PXA2XX_TIMER "pxa2xx-timer"
	65	#define PXA2XX_TIMER(obj) \
	66	OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)
	67
797e9542 DES	68	typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
797e9542 DES	69
bc24a225	70	typedef struct {
a171fe39	71	uint32_t value;
5251d196	72	qemu_irq irq;
a171fe39 AZ	73	QEMUTimer *qtimer;
a171fe39 AZ	74	int num;
797e9542	75	PXA2xxTimerInfo *info;
bc24a225	76	} PXA2xxTimer0;
a171fe39	77
bc24a225 PB	78	typedef struct {
bc24a225 PB	79	PXA2xxTimer0 tm;
a171fe39 AZ	80	int32_t oldclock;
	81	int32_t clock;
	82	uint64_t lastload;
	83	uint32_t freq;
	84	uint32_t control;
bc24a225	85	} PXA2xxTimer4;
a171fe39	86
797e9542	87	struct PXA2xxTimerInfo {
feea4361 AF	88	SysBusDevice parent_obj;
feea4361 AF	89
b755bde3	90	MemoryRegion iomem;
797e9542 DES	91	uint32_t flags;
797e9542 DES	92
a171fe39 AZ	93	int32_t clock;
	94	int32_t oldclock;
	95	uint64_t lastload;
	96	uint32_t freq;
bc24a225	97	PXA2xxTimer0 timer[4];
a171fe39 AZ	98	uint32_t events;
	99	uint32_t irq_enabled;
	100	uint32_t reset3;
a171fe39	101	uint32_t snapshot;
797e9542	102
4ff927cc	103	qemu_irq irq4;
797e9542	104	PXA2xxTimer4 tm4[8];
797e9542 DES	105	};
	106
	107	#define PXA2XX_TIMER_HAVE_TM4 0
	108
	109	static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
	110	{
	111	return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
	112	}
a171fe39 AZ	113
	114	static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
	115	{
d353eb43	116	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	117	int i;
	118	uint32_t now_vm;
	119	uint64_t new_qemu;
	120
	121	now_vm = s->clock +
73bcb24d	122	muldiv64(now_qemu - s->lastload, s->freq, NANOSECONDS_PER_SECOND);
a171fe39 AZ	123
	124	for (i = 0; i < 4; i ++) {
	125	new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
73bcb24d	126	NANOSECONDS_PER_SECOND, s->freq);
bc72ad67	127	timer_mod(s->timer[i].qtimer, new_qemu);
a171fe39 AZ	128	}
	129	}
	130
	131	static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
	132	{
d353eb43	133	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	134	uint32_t now_vm;
	135	uint64_t new_qemu;
	136	static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
	137	int counter;
	138
	139	if (s->tm4[n].control & (1 << 7))
	140	counter = n;
	141	else
	142	counter = counters[n];
	143
	144	if (!s->tm4[counter].freq) {
bc72ad67	145	timer_del(s->tm4[n].tm.qtimer);
a171fe39 AZ	146	return;
	147	}
	148
	149	now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
	150	s->tm4[counter].lastload,
73bcb24d	151	s->tm4[counter].freq, NANOSECONDS_PER_SECOND);
a171fe39	152
3bdd58a4	153	new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
73bcb24d	154	NANOSECONDS_PER_SECOND, s->tm4[counter].freq);
bc72ad67	155	timer_mod(s->tm4[n].tm.qtimer, new_qemu);
a171fe39 AZ	156	}
a171fe39 AZ	157
a8170e5e	158	static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
b755bde3	159	unsigned size)
a171fe39	160	{
d353eb43	161	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	162	int tm = 0;
a171fe39 AZ	163
a171fe39 AZ	164	switch (offset) {
a171fe39 AZ	165	case OSMR3: tm ++;
de16017d	166	/* fall through */
a171fe39	167	case OSMR2: tm ++;
de16017d	168	/* fall through */
a171fe39	169	case OSMR1: tm ++;
de16017d	170	/* fall through */
a171fe39 AZ	171	case OSMR0:
	172	return s->timer[tm].value;
	173	case OSMR11: tm ++;
de16017d	174	/* fall through */
a171fe39	175	case OSMR10: tm ++;
de16017d	176	/* fall through */
a171fe39	177	case OSMR9: tm ++;
de16017d	178	/* fall through */
a171fe39	179	case OSMR8: tm ++;
de16017d	180	/* fall through */
a171fe39	181	case OSMR7: tm ++;
de16017d	182	/* fall through */
a171fe39	183	case OSMR6: tm ++;
de16017d	184	/* fall through */
a171fe39	185	case OSMR5: tm ++;
de16017d	186	/* fall through */
a171fe39	187	case OSMR4:
797e9542	188	if (!pxa2xx_timer_has_tm4(s))
a171fe39	189	goto badreg;
3bdd58a4	190	return s->tm4[tm].tm.value;
a171fe39	191	case OSCR:
bc72ad67	192	return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
73bcb24d	193	s->lastload, s->freq, NANOSECONDS_PER_SECOND);
a171fe39	194	case OSCR11: tm ++;
de16017d	195	/* fall through */
a171fe39	196	case OSCR10: tm ++;
de16017d	197	/* fall through */
a171fe39	198	case OSCR9: tm ++;
de16017d	199	/* fall through */
a171fe39	200	case OSCR8: tm ++;
de16017d	201	/* fall through */
a171fe39	202	case OSCR7: tm ++;
de16017d	203	/* fall through */
a171fe39	204	case OSCR6: tm ++;
de16017d	205	/* fall through */
a171fe39	206	case OSCR5: tm ++;
de16017d	207	/* fall through */
a171fe39	208	case OSCR4:
797e9542	209	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	210	goto badreg;
	211
	212	if ((tm == 9 - 4 \|\| tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
	213	if (s->tm4[tm - 1].freq)
	214	s->snapshot = s->tm4[tm - 1].clock + muldiv64(
bc72ad67	215	qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
a171fe39	216	s->tm4[tm - 1].lastload,
73bcb24d	217	s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND);
a171fe39 AZ	218	else
	219	s->snapshot = s->tm4[tm - 1].clock;
	220	}
	221
	222	if (!s->tm4[tm].freq)
	223	return s->tm4[tm].clock;
73bcb24d RS	224	return s->tm4[tm].clock +
	225	muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
	226	s->tm4[tm].lastload, s->tm4[tm].freq,
	227	NANOSECONDS_PER_SECOND);
a171fe39 AZ	228	case OIER:
	229	return s->irq_enabled;
	230	case OSSR: /* Status register */
	231	return s->events;
	232	case OWER:
	233	return s->reset3;
	234	case OMCR11: tm ++;
de16017d	235	/* fall through */
a171fe39	236	case OMCR10: tm ++;
de16017d	237	/* fall through */
a171fe39	238	case OMCR9: tm ++;
de16017d	239	/* fall through */
a171fe39	240	case OMCR8: tm ++;
de16017d	241	/* fall through */
a171fe39	242	case OMCR7: tm ++;
de16017d	243	/* fall through */
a171fe39	244	case OMCR6: tm ++;
de16017d	245	/* fall through */
a171fe39	246	case OMCR5: tm ++;
de16017d	247	/* fall through */
a171fe39	248	case OMCR4:
797e9542	249	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	250	goto badreg;
	251	return s->tm4[tm].control;
	252	case OSNR:
	253	return s->snapshot;
	254	default:
	255	badreg:
2ac71179	256	hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
a171fe39 AZ	257	}
	258
	259	return 0;
	260	}
	261
a8170e5e	262	static void pxa2xx_timer_write(void *opaque, hwaddr offset,
b755bde3	263	uint64_t value, unsigned size)
a171fe39 AZ	264	{
a171fe39 AZ	265	int i, tm = 0;
d353eb43	266	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39	267
a171fe39 AZ	268	switch (offset) {
a171fe39 AZ	269	case OSMR3: tm ++;
de16017d	270	/* fall through */
a171fe39	271	case OSMR2: tm ++;
de16017d	272	/* fall through */
a171fe39	273	case OSMR1: tm ++;
de16017d	274	/* fall through */
a171fe39 AZ	275	case OSMR0:
a171fe39 AZ	276	s->timer[tm].value = value;
bc72ad67	277	pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
a171fe39 AZ	278	break;
a171fe39 AZ	279	case OSMR11: tm ++;
de16017d	280	/* fall through */
a171fe39	281	case OSMR10: tm ++;
de16017d	282	/* fall through */
a171fe39	283	case OSMR9: tm ++;
de16017d	284	/* fall through */
a171fe39	285	case OSMR8: tm ++;
de16017d	286	/* fall through */
a171fe39	287	case OSMR7: tm ++;
de16017d	288	/* fall through */
a171fe39	289	case OSMR6: tm ++;
de16017d	290	/* fall through */
a171fe39	291	case OSMR5: tm ++;
de16017d	292	/* fall through */
a171fe39	293	case OSMR4:
797e9542	294	if (!pxa2xx_timer_has_tm4(s))
a171fe39	295	goto badreg;
3bdd58a4	296	s->tm4[tm].tm.value = value;
bc72ad67	297	pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
a171fe39 AZ	298	break;
	299	case OSCR:
	300	s->oldclock = s->clock;
bc72ad67	301	s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a171fe39 AZ	302	s->clock = value;
	303	pxa2xx_timer_update(s, s->lastload);
	304	break;
	305	case OSCR11: tm ++;
de16017d	306	/* fall through */
a171fe39	307	case OSCR10: tm ++;
de16017d	308	/* fall through */
a171fe39	309	case OSCR9: tm ++;
de16017d	310	/* fall through */
a171fe39	311	case OSCR8: tm ++;
de16017d	312	/* fall through */
a171fe39	313	case OSCR7: tm ++;
de16017d	314	/* fall through */
a171fe39	315	case OSCR6: tm ++;
de16017d	316	/* fall through */
a171fe39	317	case OSCR5: tm ++;
de16017d	318	/* fall through */
a171fe39	319	case OSCR4:
797e9542	320	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	321	goto badreg;
a171fe39 AZ	322	s->tm4[tm].oldclock = s->tm4[tm].clock;
bc72ad67	323	s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a171fe39 AZ	324	s->tm4[tm].clock = value;
	325	pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
	326	break;
	327	case OIER:
	328	s->irq_enabled = value & 0xfff;
	329	break;
	330	case OSSR: /* Status register */
8034ce7d	331	value &= s->events;
a171fe39	332	s->events &= ~value;
8034ce7d AZ	333	for (i = 0; i < 4; i ++, value >>= 1)
8034ce7d AZ	334	if (value & 1)
5251d196	335	qemu_irq_lower(s->timer[i].irq);
8034ce7d AZ	336	if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
8034ce7d AZ	337	qemu_irq_lower(s->irq4);
a171fe39 AZ	338	break;
	339	case OWER: /* XXX: Reset on OSMR3 match? */
	340	s->reset3 = value;
	341	break;
	342	case OMCR7: tm ++;
de16017d	343	/* fall through */
a171fe39	344	case OMCR6: tm ++;
de16017d	345	/* fall through */
a171fe39	346	case OMCR5: tm ++;
de16017d	347	/* fall through */
a171fe39	348	case OMCR4:
797e9542	349	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	350	goto badreg;
	351	s->tm4[tm].control = value & 0x0ff;
	352	/* XXX Stop if running (shouldn't happen) */
	353	if ((value & (1 << 7)) \|\| tm == 0)
	354	s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
	355	else {
	356	s->tm4[tm].freq = 0;
bc72ad67	357	pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
a171fe39 AZ	358	}
	359	break;
	360	case OMCR11: tm ++;
de16017d	361	/* fall through */
a171fe39	362	case OMCR10: tm ++;
de16017d	363	/* fall through */
a171fe39	364	case OMCR9: tm ++;
de16017d	365	/* fall through */
a171fe39	366	case OMCR8: tm += 4;
797e9542	367	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	368	goto badreg;
	369	s->tm4[tm].control = value & 0x3ff;
	370	/* XXX Stop if running (shouldn't happen) */
	371	if ((value & (1 << 7)) \|\| !(tm & 1))
	372	s->tm4[tm].freq =
	373	pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
	374	else {
	375	s->tm4[tm].freq = 0;
bc72ad67	376	pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
a171fe39 AZ	377	}
	378	break;
	379	default:
	380	badreg:
2ac71179	381	hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
a171fe39 AZ	382	}
	383	}
	384
b755bde3 BC	385	static const MemoryRegionOps pxa2xx_timer_ops = {
	386	.read = pxa2xx_timer_read,
	387	.write = pxa2xx_timer_write,
	388	.endianness = DEVICE_NATIVE_ENDIAN,
a171fe39 AZ	389	};
	390
	391	static void pxa2xx_timer_tick(void *opaque)
	392	{
bc24a225	393	PXA2xxTimer0 t = (PXA2xxTimer0 ) opaque;
797e9542	394	PXA2xxTimerInfo *i = t->info;
a171fe39 AZ	395
a171fe39 AZ	396	if (i->irq_enabled & (1 << t->num)) {
a171fe39	397	i->events \|= 1 << t->num;
5251d196	398	qemu_irq_raise(t->irq);
a171fe39 AZ	399	}
	400
	401	if (t->num == 3)
	402	if (i->reset3 & 1) {
	403	i->reset3 = 0;
3f582262	404	qemu_system_reset_request();
a171fe39 AZ	405	}
	406	}
	407
	408	static void pxa2xx_timer_tick4(void *opaque)
	409	{
bc24a225	410	PXA2xxTimer4 t = (PXA2xxTimer4 ) opaque;
d353eb43	411	PXA2xxTimerInfo i = (PXA2xxTimerInfo ) t->tm.info;
a171fe39	412
3bdd58a4	413	pxa2xx_timer_tick(&t->tm);
a171fe39 AZ	414	if (t->control & (1 << 3))
	415	t->clock = 0;
	416	if (t->control & (1 << 6))
bc72ad67	417	pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
4ff927cc DES	418	if (i->events & 0xff0)
4ff927cc DES	419	qemu_irq_raise(i->irq4);
a171fe39 AZ	420	}
a171fe39 AZ	421
797e9542	422	static int pxa25x_timer_post_load(void *opaque, int version_id)
aa941b94	423	{
d353eb43	424	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
aa941b94 AZ	425	int64_t now;
	426	int i;
	427
bc72ad67	428	now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
aa941b94 AZ	429	pxa2xx_timer_update(s, now);
aa941b94 AZ	430
797e9542 DES	431	if (pxa2xx_timer_has_tm4(s))
797e9542 DES	432	for (i = 0; i < 8; i ++)
aa941b94	433	pxa2xx_timer_update4(s, now, i);
aa941b94 AZ	434
	435	return 0;
	436	}
	437
5d83e348	438	static void pxa2xx_timer_init(Object *obj)
a171fe39	439	{
5d83e348 XZ	440	PXA2xxTimerInfo *s = PXA2XX_TIMER(obj);
5d83e348 XZ	441	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
a171fe39	442
a171fe39 AZ	443	s->irq_enabled = 0;
	444	s->oldclock = 0;
	445	s->clock = 0;
bc72ad67	446	s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a171fe39	447	s->reset3 = 0;
a171fe39	448
5d83e348 XZ	449	memory_region_init_io(&s->iomem, obj, &pxa2xx_timer_ops, s,
	450	"pxa2xx-timer", 0x00001000);
	451	sysbus_init_mmio(dev, &s->iomem);
	452	}
	453
	454	static void pxa2xx_timer_realize(DeviceState dev, Error *errp)
	455	{
	456	PXA2xxTimerInfo *s = PXA2XX_TIMER(dev);
	457	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
	458	int i;
	459
a171fe39 AZ	460	for (i = 0; i < 4; i ++) {
a171fe39 AZ	461	s->timer[i].value = 0;
5d83e348	462	sysbus_init_irq(sbd, &s->timer[i].irq);
a171fe39 AZ	463	s->timer[i].info = s;
a171fe39 AZ	464	s->timer[i].num = i;
bc72ad67	465	s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
5d83e348	466	pxa2xx_timer_tick, &s->timer[i]);
a171fe39	467	}
5d83e348	468
797e9542	469	if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
5d83e348	470	sysbus_init_irq(sbd, &s->irq4);
797e9542 DES	471
	472	for (i = 0; i < 8; i ++) {
	473	s->tm4[i].tm.value = 0;
	474	s->tm4[i].tm.info = s;
	475	s->tm4[i].tm.num = i + 4;
797e9542 DES	476	s->tm4[i].freq = 0;
797e9542 DES	477	s->tm4[i].control = 0x0;
bc72ad67	478	s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
5d83e348	479	pxa2xx_timer_tick4, &s->tm4[i]);
797e9542 DES	480	}
797e9542 DES	481	}
a171fe39 AZ	482	}
a171fe39 AZ	483
797e9542 DES	484	static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
797e9542 DES	485	.name = "pxa2xx_timer0",
8034ce7d AZ	486	.version_id = 2,
8034ce7d AZ	487	.minimum_version_id = 2,
797e9542 DES	488	.fields = (VMStateField[]) {
797e9542 DES	489	VMSTATE_UINT32(value, PXA2xxTimer0),
797e9542 DES	490	VMSTATE_END_OF_LIST(),
	491	},
	492	};
	493
	494	static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
	495	.name = "pxa2xx_timer4",
	496	.version_id = 1,
	497	.minimum_version_id = 1,
797e9542 DES	498	.fields = (VMStateField[]) {
	499	VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
	500	vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
	501	VMSTATE_INT32(oldclock, PXA2xxTimer4),
	502	VMSTATE_INT32(clock, PXA2xxTimer4),
	503	VMSTATE_UINT64(lastload, PXA2xxTimer4),
	504	VMSTATE_UINT32(freq, PXA2xxTimer4),
	505	VMSTATE_UINT32(control, PXA2xxTimer4),
	506	VMSTATE_END_OF_LIST(),
	507	},
	508	};
	509
	510	static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
a171fe39	511	{
797e9542	512	return pxa2xx_timer_has_tm4(opaque);
a171fe39 AZ	513	}
a171fe39 AZ	514
797e9542 DES	515	static const VMStateDescription vmstate_pxa2xx_timer_regs = {
	516	.name = "pxa2xx_timer",
	517	.version_id = 1,
	518	.minimum_version_id = 1,
797e9542 DES	519	.post_load = pxa25x_timer_post_load,
	520	.fields = (VMStateField[]) {
	521	VMSTATE_INT32(clock, PXA2xxTimerInfo),
	522	VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
	523	VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
	524	VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
	525	vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
	526	VMSTATE_UINT32(events, PXA2xxTimerInfo),
	527	VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
	528	VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
	529	VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
	530	VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
	531	pxa2xx_timer_has_tm4_test, 0,
	532	vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
	533	VMSTATE_END_OF_LIST(),
a171fe39	534	}
797e9542 DES	535	};
797e9542 DES	536
999e12bb AL	537	static Property pxa25x_timer_dev_properties[] = {
	538	DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
	539	DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
feea4361	540	PXA2XX_TIMER_HAVE_TM4, false),
999e12bb	541	DEFINE_PROP_END_OF_LIST(),
797e9542 DES	542	};
797e9542 DES	543
999e12bb AL	544	static void pxa25x_timer_dev_class_init(ObjectClass klass, void data)
999e12bb AL	545	{
39bffca2	546	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	547
39bffca2	548	dc->desc = "PXA25x timer";
39bffca2	549	dc->props = pxa25x_timer_dev_properties;
999e12bb AL	550	}
999e12bb AL	551
8c43a6f0	552	static const TypeInfo pxa25x_timer_dev_info = {
39bffca2	553	.name = "pxa25x-timer",
feea4361	554	.parent = TYPE_PXA2XX_TIMER,
39bffca2 AL	555	.instance_size = sizeof(PXA2xxTimerInfo),
39bffca2 AL	556	.class_init = pxa25x_timer_dev_class_init,
999e12bb AL	557	};
	558
	559	static Property pxa27x_timer_dev_properties[] = {
	560	DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
	561	DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
feea4361	562	PXA2XX_TIMER_HAVE_TM4, true),
999e12bb AL	563	DEFINE_PROP_END_OF_LIST(),
	564	};
	565
	566	static void pxa27x_timer_dev_class_init(ObjectClass klass, void data)
	567	{
39bffca2	568	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	569
39bffca2	570	dc->desc = "PXA27x timer";
39bffca2	571	dc->props = pxa27x_timer_dev_properties;
999e12bb AL	572	}
999e12bb AL	573
8c43a6f0	574	static const TypeInfo pxa27x_timer_dev_info = {
39bffca2	575	.name = "pxa27x-timer",
feea4361	576	.parent = TYPE_PXA2XX_TIMER,
39bffca2 AL	577	.instance_size = sizeof(PXA2xxTimerInfo),
39bffca2 AL	578	.class_init = pxa27x_timer_dev_class_init,
797e9542 DES	579	};
797e9542 DES	580
feea4361 AF	581	static void pxa2xx_timer_class_init(ObjectClass oc, void data)
	582	{
	583	DeviceClass *dc = DEVICE_CLASS(oc);
feea4361	584
5d83e348	585	dc->realize = pxa2xx_timer_realize;
feea4361 AF	586	dc->vmsd = &vmstate_pxa2xx_timer_regs;
	587	}
	588
	589	static const TypeInfo pxa2xx_timer_type_info = {
	590	.name = TYPE_PXA2XX_TIMER,
	591	.parent = TYPE_SYS_BUS_DEVICE,
	592	.instance_size = sizeof(PXA2xxTimerInfo),
5d83e348	593	.instance_init = pxa2xx_timer_init,
feea4361 AF	594	.abstract = true,
	595	.class_init = pxa2xx_timer_class_init,
	596	};
	597
83f7d43a	598	static void pxa2xx_timer_register_types(void)
797e9542	599	{
feea4361	600	type_register_static(&pxa2xx_timer_type_info);
39bffca2 AL	601	type_register_static(&pxa25x_timer_dev_info);
39bffca2 AL	602	type_register_static(&pxa27x_timer_dev_info);
83f7d43a AF	603	}
	604
	605	type_init(pxa2xx_timer_register_types)