]> git.proxmox.com Git - mirror_qemu.git/blame - hw/vga.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Rename target_phys_addr_t to hwaddr
[mirror_qemu.git] / hw / vga.c
CommitLineData
e89f66ec 1/*
4fa0f5d2 2 * QEMU VGA Emulator.
5fafdf24 3 *
e89f66ec 4 * Copyright (c) 2003 Fabrice Bellard
5fafdf24 5 *
e89f66ec
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b 24#include "hw.h"
5e55efc9 25#include "vga.h"
87ecb68b
PB		 26#include "console.h"
27#include "pc.h"
28#include "pci.h"
798b0c25 29#include "vga_int.h"
94470844 30#include "pixel_ops.h"
cb5a7aa8 31#include "qemu-timer.h"
c65adf9b 32#include "xen.h"
72750018 33#include "trace.h"
e89f66ec 34
e89f66ec 35//#define DEBUG_VGA
17b0018b 36//#define DEBUG_VGA_MEM
a41bc9af
FB		 37//#define DEBUG_VGA_REG
38
4fa0f5d2
FB		 39//#define DEBUG_BOCHS_VBE
40
9aa0ff0b
JK		 41/* 16 state changes per vertical frame @60 Hz */
42#define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
43
47c012e2
BS		 44/*
45 * Video Graphics Array (VGA)
46 *
47 * Chipset docs for original IBM VGA:
48 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
49 *
50 * FreeVGA site:
51 * http://www.osdever.net/FreeVGA/home.htm
52 *
53 * Standard VGA features and Bochs VBE extensions are implemented.
54 */
55
e89f66ec 56/* force some bits to zero */
798b0c25 57const uint8_t sr_mask[8] = {
9e622b15
BS		 58 0x03,
59 0x3d,
60 0x0f,
61 0x3f,
62 0x0e,
63 0x00,
64 0x00,
65 0xff,
e89f66ec
FB		 66};
67
798b0c25 68const uint8_t gr_mask[16] = {
9e622b15
BS		 69 0x0f, /* 0x00 */
70 0x0f, /* 0x01 */
71 0x0f, /* 0x02 */
72 0x1f, /* 0x03 */
73 0x03, /* 0x04 */
74 0x7b, /* 0x05 */
75 0x0f, /* 0x06 */
76 0x0f, /* 0x07 */
77 0xff, /* 0x08 */
78 0x00, /* 0x09 */
79 0x00, /* 0x0a */
80 0x00, /* 0x0b */
81 0x00, /* 0x0c */
82 0x00, /* 0x0d */
83 0x00, /* 0x0e */
84 0x00, /* 0x0f */
e89f66ec
FB		 85};
86
87#define cbswap_32(__x) \
88((uint32_t)( \
89 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
90 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
91 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
92 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
93
e2542fe2 94#ifdef HOST_WORDS_BIGENDIAN
e89f66ec
FB		 95#define PAT(x) cbswap_32(x)
96#else
97#define PAT(x) (x)
98#endif
99
e2542fe2 100#ifdef HOST_WORDS_BIGENDIAN
b8ed223b
FB		 101#define BIG 1
102#else
103#define BIG 0
104#endif
105
e2542fe2 106#ifdef HOST_WORDS_BIGENDIAN
b8ed223b
FB		 107#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
108#else
109#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
110#endif
111
e89f66ec
FB		 112static const uint32_t mask16[16] = {
113 PAT(0x00000000),
114 PAT(0x000000ff),
115 PAT(0x0000ff00),
116 PAT(0x0000ffff),
117 PAT(0x00ff0000),
118 PAT(0x00ff00ff),
119 PAT(0x00ffff00),
120 PAT(0x00ffffff),
121 PAT(0xff000000),
122 PAT(0xff0000ff),
123 PAT(0xff00ff00),
124 PAT(0xff00ffff),
125 PAT(0xffff0000),
126 PAT(0xffff00ff),
127 PAT(0xffffff00),
128 PAT(0xffffffff),
129};
130
131#undef PAT
132
e2542fe2 133#ifdef HOST_WORDS_BIGENDIAN
e89f66ec
FB		 134#define PAT(x) (x)
135#else
136#define PAT(x) cbswap_32(x)
137#endif
138
139static const uint32_t dmask16[16] = {
140 PAT(0x00000000),
141 PAT(0x000000ff),
142 PAT(0x0000ff00),
143 PAT(0x0000ffff),
144 PAT(0x00ff0000),
145 PAT(0x00ff00ff),
146 PAT(0x00ffff00),
147 PAT(0x00ffffff),
148 PAT(0xff000000),
149 PAT(0xff0000ff),
150 PAT(0xff00ff00),
151 PAT(0xff00ffff),
152 PAT(0xffff0000),
153 PAT(0xffff00ff),
154 PAT(0xffffff00),
155 PAT(0xffffffff),
156};
157
158static const uint32_t dmask4[4] = {
159 PAT(0x00000000),
160 PAT(0x0000ffff),
161 PAT(0xffff0000),
162 PAT(0xffffffff),
163};
164
165static uint32_t expand4[256];
166static uint16_t expand2[256];
17b0018b 167static uint8_t expand4to8[16];
e89f66ec 168
d7098135
LC		 169static void vga_screen_dump(void *opaque, const char *filename, bool cswitch,
170 Error **errp);
95219897 171
80763888
JK		 172static void vga_update_memory_access(VGACommonState *s)
173{
174 MemoryRegion *region, *old_region = s->chain4_alias;
a8170e5e 175 hwaddr base, offset, size;
80763888
JK		 176
177 s->chain4_alias = NULL;
178
5e55efc9
BS		 179 if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==
180 VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
80763888 181 offset = 0;
5e55efc9 182 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
80763888
JK		 183 case 0:
184 base = 0xa0000;
185 size = 0x20000;
186 break;
187 case 1:
188 base = 0xa0000;
189 size = 0x10000;
190 offset = s->bank_offset;
191 break;
192 case 2:
193 base = 0xb0000;
194 size = 0x8000;
195 break;
196 case 3:
f065aa0a 197 default:
80763888
JK		 198 base = 0xb8000;
199 size = 0x8000;
200 break;
201 }
71579cae 202 base += isa_mem_base;
80763888
JK		 203 region = g_malloc(sizeof(*region));
204 memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size);
205 memory_region_add_subregion_overlap(s->legacy_address_space, base,
206 region, 2);
207 s->chain4_alias = region;
208 }
209 if (old_region) {
210 memory_region_del_subregion(s->legacy_address_space, old_region);
211 memory_region_destroy(old_region);
212 g_free(old_region);
213 s->plane_updated = 0xf;
214 }
215}
216
cedd91d2 217static void vga_dumb_update_retrace_info(VGACommonState *s)
cb5a7aa8 218{
219 (void) s;
220}
221
cedd91d2 222static void vga_precise_update_retrace_info(VGACommonState *s)
cb5a7aa8 223{
224 int htotal_chars;
225 int hretr_start_char;
226 int hretr_skew_chars;
227 int hretr_end_char;
228
229 int vtotal_lines;
230 int vretr_start_line;
231 int vretr_end_line;
232
7f5b7d3e
BS		 233 int dots;
234#if 0
235 int div2, sldiv2;
236#endif
cb5a7aa8 237 int clocking_mode;
238 int clock_sel;
b0f74c87 239 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
cb5a7aa8 240 int64_t chars_per_sec;
241 struct vga_precise_retrace *r = &s->retrace_info.precise;
242
5e55efc9
BS		 243 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
244 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
245 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
246 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
cb5a7aa8 247
5e55efc9
BS		 248 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
249 (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
250 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
251 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
252 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
253 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
254 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
cb5a7aa8 255
5e55efc9 256 clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1;
cb5a7aa8 257 clock_sel = (s->msr >> 2) & 3;
f87fc09b 258 dots = (s->msr & 1) ? 8 : 9;
cb5a7aa8 259
b0f74c87 260 chars_per_sec = clk_hz[clock_sel] / dots;
cb5a7aa8 261
262 htotal_chars <<= clocking_mode;
263
264 r->total_chars = vtotal_lines * htotal_chars;
cb5a7aa8 265 if (r->freq) {
6ee093c9 266 r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);
cb5a7aa8 267 } else {
6ee093c9 268 r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;
cb5a7aa8 269 }
270
271 r->vstart = vretr_start_line;
272 r->vend = r->vstart + vretr_end_line + 1;
273
274 r->hstart = hretr_start_char + hretr_skew_chars;
275 r->hend = r->hstart + hretr_end_char + 1;
276 r->htotal = htotal_chars;
277
f87fc09b 278#if 0
5e55efc9
BS		 279 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
280 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
cb5a7aa8 281 printf (
f87fc09b 282 "hz=%f\n"
cb5a7aa8 283 "htotal = %d\n"
284 "hretr_start = %d\n"
285 "hretr_skew = %d\n"
286 "hretr_end = %d\n"
287 "vtotal = %d\n"
288 "vretr_start = %d\n"
289 "vretr_end = %d\n"
290 "div2 = %d sldiv2 = %d\n"
291 "clocking_mode = %d\n"
292 "clock_sel = %d %d\n"
293 "dots = %d\n"
0bfcd599 294 "ticks/char = %" PRId64 "\n"
cb5a7aa8 295 "\n",
6ee093c9 296 (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
cb5a7aa8 297 htotal_chars,
298 hretr_start_char,
299 hretr_skew_chars,
300 hretr_end_char,
301 vtotal_lines,
302 vretr_start_line,
303 vretr_end_line,
304 div2, sldiv2,
305 clocking_mode,
306 clock_sel,
b0f74c87 307 clk_hz[clock_sel],
cb5a7aa8 308 dots,
309 r->ticks_per_char
310 );
311#endif
312}
313
cedd91d2 314static uint8_t vga_precise_retrace(VGACommonState *s)
cb5a7aa8 315{
316 struct vga_precise_retrace *r = &s->retrace_info.precise;
317 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
318
319 if (r->total_chars) {
320 int cur_line, cur_line_char, cur_char;
321 int64_t cur_tick;
322
74475455 323 cur_tick = qemu_get_clock_ns(vm_clock);
cb5a7aa8 324
325 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
326 cur_line = cur_char / r->htotal;
327
328 if (cur_line >= r->vstart && cur_line <= r->vend) {
329 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
f87fc09b 330 } else {
331 cur_line_char = cur_char % r->htotal;
332 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
333 val |= ST01_DISP_ENABLE;
334 }
cb5a7aa8 335 }
336
337 return val;
338 } else {
339 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
340 }
341}
342
cedd91d2 343static uint8_t vga_dumb_retrace(VGACommonState *s)
cb5a7aa8 344{
345 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
346}
347
25a18cbd
JQ		 348int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
349{
5e55efc9 350 if (s->msr & VGA_MIS_COLOR) {
25a18cbd
JQ		 351 /* Color */
352 return (addr >= 0x3b0 && addr <= 0x3bf);
353 } else {
354 /* Monochrome */
355 return (addr >= 0x3d0 && addr <= 0x3df);
356 }
357}
358
43bf782b 359uint32_t vga_ioport_read(void *opaque, uint32_t addr)
e89f66ec 360{
43bf782b 361 VGACommonState *s = opaque;
e89f66ec
FB		 362 int val, index;
363
bd8f2f5d
JK		 364 qemu_flush_coalesced_mmio_buffer();
365
25a18cbd 366 if (vga_ioport_invalid(s, addr)) {
e89f66ec
FB		 367 val = 0xff;
368 } else {
369 switch(addr) {
5e55efc9 370 case VGA_ATT_W:
e89f66ec
FB		 371 if (s->ar_flip_flop == 0) {
372 val = s->ar_index;
373 } else {
374 val = 0;
375 }
376 break;
5e55efc9 377 case VGA_ATT_R:
e89f66ec 378 index = s->ar_index & 0x1f;
5e55efc9 379 if (index < VGA_ATT_C) {
e89f66ec 380 val = s->ar[index];
5e55efc9 381 } else {
e89f66ec 382 val = 0;
5e55efc9 383 }
e89f66ec 384 break;
5e55efc9 385 case VGA_MIS_W:
e89f66ec
FB		 386 val = s->st00;
387 break;
5e55efc9 388 case VGA_SEQ_I:
e89f66ec
FB		 389 val = s->sr_index;
390 break;
5e55efc9 391 case VGA_SEQ_D:
e89f66ec 392 val = s->sr[s->sr_index];
a41bc9af
FB		 393#ifdef DEBUG_VGA_REG
394 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
395#endif
e89f66ec 396 break;
5e55efc9 397 case VGA_PEL_IR:
e89f66ec
FB		 398 val = s->dac_state;
399 break;
5e55efc9 400 case VGA_PEL_IW:
e9b43ea3
JQ		 401 val = s->dac_write_index;
402 break;
5e55efc9 403 case VGA_PEL_D:
e89f66ec
FB		 404 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
405 if (++s->dac_sub_index == 3) {
406 s->dac_sub_index = 0;
407 s->dac_read_index++;
408 }
409 break;
5e55efc9 410 case VGA_FTC_R:
e89f66ec
FB		 411 val = s->fcr;
412 break;
5e55efc9 413 case VGA_MIS_R:
e89f66ec
FB		 414 val = s->msr;
415 break;
5e55efc9 416 case VGA_GFX_I:
e89f66ec
FB		 417 val = s->gr_index;
418 break;
5e55efc9 419 case VGA_GFX_D:
e89f66ec 420 val = s->gr[s->gr_index];
a41bc9af
FB		 421#ifdef DEBUG_VGA_REG
422 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
423#endif
e89f66ec 424 break;
5e55efc9
BS		 425 case VGA_CRT_IM:
426 case VGA_CRT_IC:
e89f66ec
FB		 427 val = s->cr_index;
428 break;
5e55efc9
BS		 429 case VGA_CRT_DM:
430 case VGA_CRT_DC:
e89f66ec 431 val = s->cr[s->cr_index];
a41bc9af
FB		 432#ifdef DEBUG_VGA_REG
433 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
a41bc9af 434#endif
e89f66ec 435 break;
5e55efc9
BS		 436 case VGA_IS1_RM:
437 case VGA_IS1_RC:
e89f66ec 438 /* just toggle to fool polling */
cb5a7aa8 439 val = s->st01 = s->retrace(s);
e89f66ec
FB		 440 s->ar_flip_flop = 0;
441 break;
442 default:
443 val = 0x00;
444 break;
445 }
446 }
4fa0f5d2 447#if defined(DEBUG_VGA)
e89f66ec
FB		 448 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
449#endif
450 return val;
451}
452
43bf782b 453void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e89f66ec 454{
43bf782b 455 VGACommonState *s = opaque;
5467a722 456 int index;
e89f66ec 457
bd8f2f5d
JK		 458 qemu_flush_coalesced_mmio_buffer();
459
e89f66ec 460 /* check port range access depending on color/monochrome mode */
25a18cbd 461 if (vga_ioport_invalid(s, addr)) {
e89f66ec 462 return;
25a18cbd 463 }
e89f66ec
FB		 464#ifdef DEBUG_VGA
465 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
466#endif
467
468 switch(addr) {
5e55efc9 469 case VGA_ATT_W:
e89f66ec
FB		 470 if (s->ar_flip_flop == 0) {
471 val &= 0x3f;
472 s->ar_index = val;
473 } else {
474 index = s->ar_index & 0x1f;
475 switch(index) {
5e55efc9 476 case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
e89f66ec
FB		 477 s->ar[index] = val & 0x3f;
478 break;
5e55efc9 479 case VGA_ATC_MODE:
e89f66ec
FB		 480 s->ar[index] = val & ~0x10;
481 break;
5e55efc9 482 case VGA_ATC_OVERSCAN:
e89f66ec
FB		 483 s->ar[index] = val;
484 break;
5e55efc9 485 case VGA_ATC_PLANE_ENABLE:
e89f66ec
FB		 486 s->ar[index] = val & ~0xc0;
487 break;
5e55efc9 488 case VGA_ATC_PEL:
e89f66ec
FB		 489 s->ar[index] = val & ~0xf0;
490 break;
5e55efc9 491 case VGA_ATC_COLOR_PAGE:
e89f66ec
FB		 492 s->ar[index] = val & ~0xf0;
493 break;
494 default:
495 break;
496 }
497 }
498 s->ar_flip_flop ^= 1;
499 break;
5e55efc9 500 case VGA_MIS_W:
e89f66ec 501 s->msr = val & ~0x10;
cb5a7aa8 502 s->update_retrace_info(s);
e89f66ec 503 break;
5e55efc9 504 case VGA_SEQ_I:
e89f66ec
FB		 505 s->sr_index = val & 7;
506 break;
5e55efc9 507 case VGA_SEQ_D:
a41bc9af
FB		 508#ifdef DEBUG_VGA_REG
509 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
510#endif
e89f66ec 511 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
5e55efc9
BS		 512 if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
513 s->update_retrace_info(s);
514 }
80763888 515 vga_update_memory_access(s);
e89f66ec 516 break;
5e55efc9 517 case VGA_PEL_IR:
e89f66ec
FB		 518 s->dac_read_index = val;
519 s->dac_sub_index = 0;
520 s->dac_state = 3;
521 break;
5e55efc9 522 case VGA_PEL_IW:
e89f66ec
FB		 523 s->dac_write_index = val;
524 s->dac_sub_index = 0;
525 s->dac_state = 0;
526 break;
5e55efc9 527 case VGA_PEL_D:
e89f66ec
FB		 528 s->dac_cache[s->dac_sub_index] = val;
529 if (++s->dac_sub_index == 3) {
530 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
531 s->dac_sub_index = 0;
532 s->dac_write_index++;
533 }
534 break;
5e55efc9 535 case VGA_GFX_I:
e89f66ec
FB		 536 s->gr_index = val & 0x0f;
537 break;
5e55efc9 538 case VGA_GFX_D:
a41bc9af
FB		 539#ifdef DEBUG_VGA_REG
540 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
541#endif
e89f66ec 542 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
80763888 543 vga_update_memory_access(s);
e89f66ec 544 break;
5e55efc9
BS		 545 case VGA_CRT_IM:
546 case VGA_CRT_IC:
e89f66ec
FB		 547 s->cr_index = val;
548 break;
5e55efc9
BS		 549 case VGA_CRT_DM:
550 case VGA_CRT_DC:
a41bc9af
FB		 551#ifdef DEBUG_VGA_REG
552 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
553#endif
e89f66ec 554 /* handle CR0-7 protection */
df800210 555 if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
556 s->cr_index <= VGA_CRTC_OVERFLOW) {
557 /* can always write bit 4 of CR7 */
558 if (s->cr_index == VGA_CRTC_OVERFLOW) {
559 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
560 (val & 0x10);
5e55efc9 561 }
df800210 562 return;
e89f66ec 563 }
a46007a0 564 s->cr[s->cr_index] = val;
cb5a7aa8 565
566 switch(s->cr_index) {
5e55efc9
BS		 567 case VGA_CRTC_H_TOTAL:
568 case VGA_CRTC_H_SYNC_START:
569 case VGA_CRTC_H_SYNC_END:
570 case VGA_CRTC_V_TOTAL:
571 case VGA_CRTC_OVERFLOW:
572 case VGA_CRTC_V_SYNC_END:
573 case VGA_CRTC_MODE:
cb5a7aa8 574 s->update_retrace_info(s);
575 break;
576 }
e89f66ec 577 break;
5e55efc9
BS		 578 case VGA_IS1_RM:
579 case VGA_IS1_RC:
e89f66ec
FB		 580 s->fcr = val & 0x10;
581 break;
582 }
583}
584
09a79b49 585static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
4fa0f5d2 586{
cedd91d2 587 VGACommonState *s = opaque;
4fa0f5d2 588 uint32_t val;
09a79b49
FB		 589 val = s->vbe_index;
590 return val;
591}
4fa0f5d2 592
803ff052 593uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
09a79b49 594{
cedd91d2 595 VGACommonState *s = opaque;
09a79b49
FB		 596 uint32_t val;
597
af92284b 598 if (s->vbe_index < VBE_DISPI_INDEX_NB) {
8454df8b
FB		 599 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
600 switch(s->vbe_index) {
601 /* XXX: do not hardcode ? */
602 case VBE_DISPI_INDEX_XRES:
603 val = VBE_DISPI_MAX_XRES;
604 break;
605 case VBE_DISPI_INDEX_YRES:
606 val = VBE_DISPI_MAX_YRES;
607 break;
608 case VBE_DISPI_INDEX_BPP:
609 val = VBE_DISPI_MAX_BPP;
610 break;
611 default:
5fafdf24 612 val = s->vbe_regs[s->vbe_index];
8454df8b
FB		 613 break;
614 }
615 } else {
5fafdf24 616 val = s->vbe_regs[s->vbe_index];
8454df8b 617 }
af92284b
GH		 618 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
619 val = s->vram_size / (64 * 1024);
8454df8b 620 } else {
09a79b49 621 val = 0;
8454df8b 622 }
4fa0f5d2 623#ifdef DEBUG_BOCHS_VBE
09a79b49 624 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
4fa0f5d2 625#endif
4fa0f5d2
FB		 626 return val;
627}
628
803ff052 629void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
09a79b49 630{
cedd91d2 631 VGACommonState *s = opaque;
09a79b49
FB		 632 s->vbe_index = val;
633}
634
803ff052 635void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
4fa0f5d2 636{
cedd91d2 637 VGACommonState *s = opaque;
4fa0f5d2 638
09a79b49 639 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
4fa0f5d2
FB		 640#ifdef DEBUG_BOCHS_VBE
641 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
642#endif
643 switch(s->vbe_index) {
644 case VBE_DISPI_INDEX_ID:
cae61cef
FB		 645 if (val == VBE_DISPI_ID0 ||
646 val == VBE_DISPI_ID1 ||
37dd208d
FB		 647 val == VBE_DISPI_ID2 ||
648 val == VBE_DISPI_ID3 ||
649 val == VBE_DISPI_ID4) {
cae61cef
FB		 650 s->vbe_regs[s->vbe_index] = val;
651 }
4fa0f5d2
FB		 652 break;
653 case VBE_DISPI_INDEX_XRES:
cae61cef
FB		 654 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
655 s->vbe_regs[s->vbe_index] = val;
656 }
4fa0f5d2
FB		 657 break;
658 case VBE_DISPI_INDEX_YRES:
cae61cef
FB		 659 if (val <= VBE_DISPI_MAX_YRES) {
660 s->vbe_regs[s->vbe_index] = val;
661 }
4fa0f5d2
FB		 662 break;
663 case VBE_DISPI_INDEX_BPP:
664 if (val == 0)
665 val = 8;
5fafdf24 666 if (val == 4 || val == 8 || val == 15 ||
cae61cef
FB		 667 val == 16 || val == 24 || val == 32) {
668 s->vbe_regs[s->vbe_index] = val;
669 }
4fa0f5d2
FB		 670 break;
671 case VBE_DISPI_INDEX_BANK:
42fc925e
FB		 672 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
673 val &= (s->vbe_bank_mask >> 2);
674 } else {
675 val &= s->vbe_bank_mask;
676 }
cae61cef 677 s->vbe_regs[s->vbe_index] = val;
26aa7d72 678 s->bank_offset = (val << 16);
80763888 679 vga_update_memory_access(s);
4fa0f5d2
FB		 680 break;
681 case VBE_DISPI_INDEX_ENABLE:
8454df8b
FB		 682 if ((val & VBE_DISPI_ENABLED) &&
683 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
4fa0f5d2
FB		 684 int h, shift_control;
685
5fafdf24 686 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
4fa0f5d2 687 s->vbe_regs[VBE_DISPI_INDEX_XRES];
5fafdf24 688 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
4fa0f5d2
FB		 689 s->vbe_regs[VBE_DISPI_INDEX_YRES];
690 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
691 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
3b46e624 692
4fa0f5d2
FB		 693 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
694 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
695 else
5fafdf24 696 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
4fa0f5d2
FB		 697 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
698 s->vbe_start_addr = 0;
8454df8b 699
4fa0f5d2
FB		 700 /* clear the screen (should be done in BIOS) */
701 if (!(val & VBE_DISPI_NOCLEARMEM)) {
5fafdf24 702 memset(s->vram_ptr, 0,
4fa0f5d2
FB		 703 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
704 }
3b46e624 705
cae61cef
FB		 706 /* we initialize the VGA graphic mode (should be done
707 in BIOS) */
5e55efc9
BS		 708 /* graphic mode + memory map 1 */
709 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
710 VGA_GR06_GRAPHICS_MODE;
711 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
712 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
4fa0f5d2 713 /* width */
5e55efc9
BS		 714 s->cr[VGA_CRTC_H_DISP] =
715 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
8454df8b 716 /* height (only meaningful if < 1024) */
4fa0f5d2 717 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
5e55efc9
BS		 718 s->cr[VGA_CRTC_V_DISP_END] = h;
719 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
4fa0f5d2
FB		 720 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
721 /* line compare to 1023 */
5e55efc9
BS		 722 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
723 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
724 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
3b46e624 725
4fa0f5d2
FB		 726 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
727 shift_control = 0;
5e55efc9 728 s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
4fa0f5d2
FB		 729 } else {
730 shift_control = 2;
5e55efc9
BS		 731 /* set chain 4 mode */
732 s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
733 /* activate all planes */
734 s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
4fa0f5d2 735 }
5e55efc9
BS		 736 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
737 (shift_control << 5);
738 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
cae61cef
FB		 739 } else {
740 /* XXX: the bios should do that */
26aa7d72 741 s->bank_offset = 0;
cae61cef 742 }
37dd208d 743 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
141253b2 744 s->vbe_regs[s->vbe_index] = val;
80763888 745 vga_update_memory_access(s);
cae61cef
FB		 746 break;
747 case VBE_DISPI_INDEX_VIRT_WIDTH:
748 {
749 int w, h, line_offset;
750
751 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
752 return;
753 w = val;
754 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
755 line_offset = w >> 1;
756 else
757 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
758 h = s->vram_size / line_offset;
759 /* XXX: support weird bochs semantics ? */
760 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
761 return;
762 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
763 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
764 s->vbe_line_offset = line_offset;
765 }
766 break;
767 case VBE_DISPI_INDEX_X_OFFSET:
768 case VBE_DISPI_INDEX_Y_OFFSET:
769 {
770 int x;
771 s->vbe_regs[s->vbe_index] = val;
772 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
773 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
774 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
775 s->vbe_start_addr += x >> 1;
776 else
777 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
778 s->vbe_start_addr >>= 2;
4fa0f5d2
FB		 779 }
780 break;
781 default:
782 break;
783 }
4fa0f5d2
FB		 784 }
785}
4fa0f5d2 786
e89f66ec 787/* called for accesses between 0xa0000 and 0xc0000 */
a8170e5e 788uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
e89f66ec 789{
e89f66ec
FB		 790 int memory_map_mode, plane;
791 uint32_t ret;
3b46e624 792
e89f66ec 793 /* convert to VGA memory offset */
5e55efc9 794 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
26aa7d72 795 addr &= 0x1ffff;
e89f66ec
FB		 796 switch(memory_map_mode) {
797 case 0:
e89f66ec
FB		 798 break;
799 case 1:
26aa7d72 800 if (addr >= 0x10000)
e89f66ec 801 return 0xff;
cae61cef 802 addr += s->bank_offset;
e89f66ec
FB		 803 break;
804 case 2:
26aa7d72 805 addr -= 0x10000;
e89f66ec
FB		 806 if (addr >= 0x8000)
807 return 0xff;
808 break;
809 default:
810 case 3:
26aa7d72 811 addr -= 0x18000;
c92b2e84
FB		 812 if (addr >= 0x8000)
813 return 0xff;
e89f66ec
FB		 814 break;
815 }
3b46e624 816
5e55efc9 817 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
e89f66ec
FB		 818 /* chain 4 mode : simplest access */
819 ret = s->vram_ptr[addr];
5e55efc9 820 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
e89f66ec 821 /* odd/even mode (aka text mode mapping) */
5e55efc9 822 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
e89f66ec
FB		 823 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
824 } else {
825 /* standard VGA latched access */
826 s->latch = ((uint32_t *)s->vram_ptr)[addr];
827
5e55efc9 828 if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
e89f66ec 829 /* read mode 0 */
5e55efc9 830 plane = s->gr[VGA_GFX_PLANE_READ];
b8ed223b 831 ret = GET_PLANE(s->latch, plane);
e89f66ec
FB		 832 } else {
833 /* read mode 1 */
5e55efc9
BS		 834 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
835 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
e89f66ec
FB		 836 ret |= ret >> 16;
837 ret |= ret >> 8;
838 ret = (~ret) & 0xff;
839 }
840 }
841 return ret;
842}
843
e89f66ec 844/* called for accesses between 0xa0000 and 0xc0000 */
a8170e5e 845void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
e89f66ec 846{
546fa6ab 847 int memory_map_mode, plane, write_mode, b, func_select, mask;
e89f66ec
FB		 848 uint32_t write_mask, bit_mask, set_mask;
849
17b0018b 850#ifdef DEBUG_VGA_MEM
0bf9e31a 851 printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
e89f66ec
FB		 852#endif
853 /* convert to VGA memory offset */
5e55efc9 854 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
26aa7d72 855 addr &= 0x1ffff;
e89f66ec
FB		 856 switch(memory_map_mode) {
857 case 0:
e89f66ec
FB		 858 break;
859 case 1:
26aa7d72 860 if (addr >= 0x10000)
e89f66ec 861 return;
cae61cef 862 addr += s->bank_offset;
e89f66ec
FB		 863 break;
864 case 2:
26aa7d72 865 addr -= 0x10000;
e89f66ec
FB		 866 if (addr >= 0x8000)
867 return;
868 break;
869 default:
870 case 3:
26aa7d72 871 addr -= 0x18000;
c92b2e84
FB		 872 if (addr >= 0x8000)
873 return;
e89f66ec
FB		 874 break;
875 }
3b46e624 876
5e55efc9 877 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
e89f66ec
FB		 878 /* chain 4 mode : simplest access */
879 plane = addr & 3;
546fa6ab 880 mask = (1 << plane);
5e55efc9 881 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
e89f66ec 882 s->vram_ptr[addr] = val;
17b0018b 883#ifdef DEBUG_VGA_MEM
0bf9e31a 884 printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
e89f66ec 885#endif
546fa6ab 886 s->plane_updated |= mask; /* only used to detect font change */
fd4aa979 887 memory_region_set_dirty(&s->vram, addr, 1);
e89f66ec 888 }
5e55efc9 889 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
e89f66ec 890 /* odd/even mode (aka text mode mapping) */
5e55efc9 891 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
546fa6ab 892 mask = (1 << plane);
5e55efc9 893 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
e89f66ec
FB		 894 addr = ((addr & ~1) << 1) | plane;
895 s->vram_ptr[addr] = val;
17b0018b 896#ifdef DEBUG_VGA_MEM
0bf9e31a 897 printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
e89f66ec 898#endif
546fa6ab 899 s->plane_updated |= mask; /* only used to detect font change */
fd4aa979 900 memory_region_set_dirty(&s->vram, addr, 1);
e89f66ec
FB		 901 }
902 } else {
903 /* standard VGA latched access */
5e55efc9 904 write_mode = s->gr[VGA_GFX_MODE] & 3;
e89f66ec
FB		 905 switch(write_mode) {
906 default:
907 case 0:
908 /* rotate */
5e55efc9 909 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
e89f66ec
FB		 910 val = ((val >> b) | (val << (8 - b))) & 0xff;
911 val |= val << 8;
912 val |= val << 16;
913
914 /* apply set/reset mask */
5e55efc9
BS		 915 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
916 val = (val & ~set_mask) |
917 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
918 bit_mask = s->gr[VGA_GFX_BIT_MASK];
e89f66ec
FB		 919 break;
920 case 1:
921 val = s->latch;
922 goto do_write;
923 case 2:
924 val = mask16[val & 0x0f];
5e55efc9 925 bit_mask = s->gr[VGA_GFX_BIT_MASK];
e89f66ec
FB		 926 break;
927 case 3:
928 /* rotate */
5e55efc9 929 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
a41bc9af 930 val = (val >> b) | (val << (8 - b));
e89f66ec 931
5e55efc9
BS		 932 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
933 val = mask16[s->gr[VGA_GFX_SR_VALUE]];
e89f66ec
FB		 934 break;
935 }
936
937 /* apply logical operation */
5e55efc9 938 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
e89f66ec
FB		 939 switch(func_select) {
940 case 0:
941 default:
942 /* nothing to do */
943 break;
944 case 1:
945 /* and */
946 val &= s->latch;
947 break;
948 case 2:
949 /* or */
950 val |= s->latch;
951 break;
952 case 3:
953 /* xor */
954 val ^= s->latch;
955 break;
956 }
957
958 /* apply bit mask */
959 bit_mask |= bit_mask << 8;
960 bit_mask |= bit_mask << 16;
961 val = (val & bit_mask) | (s->latch & ~bit_mask);
962
963 do_write:
964 /* mask data according to sr[2] */
5e55efc9 965 mask = s->sr[VGA_SEQ_PLANE_WRITE];
546fa6ab
FB		 966 s->plane_updated |= mask; /* only used to detect font change */
967 write_mask = mask16[mask];
5fafdf24
TS		 968 ((uint32_t *)s->vram_ptr)[addr] =
969 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
e89f66ec 970 (val & write_mask);
17b0018b 971#ifdef DEBUG_VGA_MEM
0bf9e31a
BS		 972 printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
973 addr * 4, write_mask, val);
e89f66ec 974#endif
fd4aa979 975 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
e89f66ec
FB		 976 }
977}
978
e89f66ec
FB		 979typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
980 const uint8_t *font_ptr, int h,
981 uint32_t fgcol, uint32_t bgcol);
982typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
5fafdf24 983 const uint8_t *font_ptr, int h,
e89f66ec 984 uint32_t fgcol, uint32_t bgcol, int dup9);
cedd91d2 985typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
e89f66ec
FB		 986 const uint8_t *s, int width);
987
e89f66ec
FB		 988#define DEPTH 8
989#include "vga_template.h"
990
991#define DEPTH 15
992#include "vga_template.h"
993
a2502b58
BS		 994#define BGR_FORMAT
995#define DEPTH 15
996#include "vga_template.h"
997
998#define DEPTH 16
999#include "vga_template.h"
1000
1001#define BGR_FORMAT
e89f66ec
FB		 1002#define DEPTH 16
1003#include "vga_template.h"
1004
1005#define DEPTH 32
1006#include "vga_template.h"
1007
d3079cd2
FB		 1008#define BGR_FORMAT
1009#define DEPTH 32
1010#include "vga_template.h"
1011
17b0018b
FB		 1012static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1013{
1014 unsigned int col;
1015 col = rgb_to_pixel8(r, g, b);
1016 col |= col << 8;
1017 col |= col << 16;
1018 return col;
1019}
1020
1021static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1022{
1023 unsigned int col;
1024 col = rgb_to_pixel15(r, g, b);
1025 col |= col << 16;
1026 return col;
1027}
1028
b29169d2
BS		 1029static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1030 unsigned int b)
1031{
1032 unsigned int col;
1033 col = rgb_to_pixel15bgr(r, g, b);
1034 col |= col << 16;
1035 return col;
1036}
1037
17b0018b
FB		 1038static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1039{
1040 unsigned int col;
1041 col = rgb_to_pixel16(r, g, b);
1042 col |= col << 16;
1043 return col;
1044}
1045
b29169d2
BS		 1046static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1047 unsigned int b)
1048{
1049 unsigned int col;
1050 col = rgb_to_pixel16bgr(r, g, b);
1051 col |= col << 16;
1052 return col;
1053}
1054
17b0018b
FB		 1055static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1056{
1057 unsigned int col;
1058 col = rgb_to_pixel32(r, g, b);
1059 return col;
1060}
1061
d3079cd2
FB		 1062static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1063{
1064 unsigned int col;
1065 col = rgb_to_pixel32bgr(r, g, b);
1066 return col;
1067}
1068
e89f66ec 1069/* return true if the palette was modified */
cedd91d2 1070static int update_palette16(VGACommonState *s)
e89f66ec 1071{
17b0018b 1072 int full_update, i;
e89f66ec 1073 uint32_t v, col, *palette;
e89f66ec
FB		 1074
1075 full_update = 0;
1076 palette = s->last_palette;
1077 for(i = 0; i < 16; i++) {
1078 v = s->ar[i];
5e55efc9
BS		 1079 if (s->ar[VGA_ATC_MODE] & 0x80) {
1080 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1081 } else {
1082 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1083 }
e89f66ec 1084 v = v * 3;
5fafdf24
TS		 1085 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1086 c6_to_8(s->palette[v + 1]),
17b0018b
FB		 1087 c6_to_8(s->palette[v + 2]));
1088 if (col != palette[i]) {
1089 full_update = 1;
1090 palette[i] = col;
e89f66ec 1091 }
17b0018b
FB		 1092 }
1093 return full_update;
1094}
1095
1096/* return true if the palette was modified */
cedd91d2 1097static int update_palette256(VGACommonState *s)
17b0018b
FB		 1098{
1099 int full_update, i;
1100 uint32_t v, col, *palette;
1101
1102 full_update = 0;
1103 palette = s->last_palette;
1104 v = 0;
1105 for(i = 0; i < 256; i++) {
37dd208d 1106 if (s->dac_8bit) {
5fafdf24
TS		 1107 col = s->rgb_to_pixel(s->palette[v],
1108 s->palette[v + 1],
37dd208d
FB		 1109 s->palette[v + 2]);
1110 } else {
5fafdf24
TS		 1111 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1112 c6_to_8(s->palette[v + 1]),
37dd208d
FB		 1113 c6_to_8(s->palette[v + 2]));
1114 }
e89f66ec
FB		 1115 if (col != palette[i]) {
1116 full_update = 1;
1117 palette[i] = col;
1118 }
17b0018b 1119 v += 3;
e89f66ec
FB		 1120 }
1121 return full_update;
1122}
1123
cedd91d2 1124static void vga_get_offsets(VGACommonState *s,
5fafdf24 1125 uint32_t *pline_offset,
83acc96b
FB		 1126 uint32_t *pstart_addr,
1127 uint32_t *pline_compare)
e89f66ec 1128{
83acc96b 1129 uint32_t start_addr, line_offset, line_compare;
a96d8bea 1130
4fa0f5d2
FB		 1131 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1132 line_offset = s->vbe_line_offset;
1133 start_addr = s->vbe_start_addr;
83acc96b 1134 line_compare = 65535;
a96d8bea 1135 } else {
4fa0f5d2 1136 /* compute line_offset in bytes */
5e55efc9 1137 line_offset = s->cr[VGA_CRTC_OFFSET];
4fa0f5d2 1138 line_offset <<= 3;
08e48902 1139
4fa0f5d2 1140 /* starting address */
5e55efc9
BS		 1141 start_addr = s->cr[VGA_CRTC_START_LO] |
1142 (s->cr[VGA_CRTC_START_HI] << 8);
83acc96b
FB		 1143
1144 /* line compare */
5e55efc9
BS		 1145 line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1146 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1147 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
4fa0f5d2 1148 }
798b0c25
FB		 1149 *pline_offset = line_offset;
1150 *pstart_addr = start_addr;
83acc96b 1151 *pline_compare = line_compare;
798b0c25
FB		 1152}
1153
1154/* update start_addr and line_offset. Return TRUE if modified */
cedd91d2 1155static int update_basic_params(VGACommonState *s)
798b0c25
FB		 1156{
1157 int full_update;
1158 uint32_t start_addr, line_offset, line_compare;
3b46e624 1159
798b0c25
FB		 1160 full_update = 0;
1161
83acc96b 1162 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
e89f66ec
FB		 1163
1164 if (line_offset != s->line_offset ||
1165 start_addr != s->start_addr ||
1166 line_compare != s->line_compare) {
1167 s->line_offset = line_offset;
1168 s->start_addr = start_addr;
1169 s->line_compare = line_compare;
1170 full_update = 1;
1171 }
1172 return full_update;
1173}
1174
b29169d2 1175#define NB_DEPTHS 7
d3079cd2
FB		 1176
1177static inline int get_depth_index(DisplayState *s)
e89f66ec 1178{
0e1f5a0c 1179 switch(ds_get_bits_per_pixel(s)) {
e89f66ec
FB		 1180 default:
1181 case 8:
1182 return 0;
1183 case 15:
8927bcfd 1184 return 1;
e89f66ec 1185 case 16:
8927bcfd 1186 return 2;
e89f66ec 1187 case 32:
7b5d76da
AL		 1188 if (is_surface_bgr(s->surface))
1189 return 4;
1190 else
1191 return 3;
e89f66ec
FB		 1192 }
1193}
1194
68f04a3c 1195static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = {
e89f66ec
FB		 1196 vga_draw_glyph8_8,
1197 vga_draw_glyph8_16,
1198 vga_draw_glyph8_16,
1199 vga_draw_glyph8_32,
d3079cd2 1200 vga_draw_glyph8_32,
b29169d2
BS		 1201 vga_draw_glyph8_16,
1202 vga_draw_glyph8_16,
e89f66ec
FB		 1203};
1204
68f04a3c 1205static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = {
17b0018b
FB		 1206 vga_draw_glyph16_8,
1207 vga_draw_glyph16_16,
1208 vga_draw_glyph16_16,
1209 vga_draw_glyph16_32,
d3079cd2 1210 vga_draw_glyph16_32,
b29169d2
BS		 1211 vga_draw_glyph16_16,
1212 vga_draw_glyph16_16,
17b0018b
FB		 1213};
1214
68f04a3c 1215static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = {
e89f66ec
FB		 1216 vga_draw_glyph9_8,
1217 vga_draw_glyph9_16,
1218 vga_draw_glyph9_16,
1219 vga_draw_glyph9_32,
d3079cd2 1220 vga_draw_glyph9_32,
b29169d2
BS		 1221 vga_draw_glyph9_16,
1222 vga_draw_glyph9_16,
e89f66ec 1223};
3b46e624 1224
e89f66ec
FB		 1225static const uint8_t cursor_glyph[32 * 4] = {
1226 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1227 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1228 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1229 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1230 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1231 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1232 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1233 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1234 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1235 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1236 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1237 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1238 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1239 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1240 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1241 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
3b46e624 1242};
e89f66ec 1243
cedd91d2 1244static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
4c5e8c5c
BS		 1245 int *pcwidth, int *pcheight)
1246{
1247 int width, cwidth, height, cheight;
1248
1249 /* total width & height */
5e55efc9 1250 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
4c5e8c5c 1251 cwidth = 8;
5e55efc9 1252 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
4c5e8c5c 1253 cwidth = 9;
5e55efc9
BS		 1254 }
1255 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
4c5e8c5c 1256 cwidth = 16; /* NOTE: no 18 pixel wide */
5e55efc9
BS		 1257 }
1258 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1259 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
4c5e8c5c
BS		 1260 /* ugly hack for CGA 160x100x16 - explain me the logic */
1261 height = 100;
1262 } else {
5e55efc9
BS		 1263 height = s->cr[VGA_CRTC_V_DISP_END] |
1264 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1265 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
4c5e8c5c
BS		 1266 height = (height + 1) / cheight;
1267 }
1268
1269 *pwidth = width;
1270 *pheight = height;
1271 *pcwidth = cwidth;
1272 *pcheight = cheight;
1273}
1274
7d957bd8
AL		 1275typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1276
68f04a3c 1277static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = {
bdb19571
AL		 1278 rgb_to_pixel8_dup,
1279 rgb_to_pixel15_dup,
1280 rgb_to_pixel16_dup,
1281 rgb_to_pixel32_dup,
1282 rgb_to_pixel32bgr_dup,
1283 rgb_to_pixel15bgr_dup,
1284 rgb_to_pixel16bgr_dup,
1285};
7d957bd8 1286
5fafdf24
TS		 1287/*
1288 * Text mode update
e89f66ec
FB		 1289 * Missing:
1290 * - double scan
5fafdf24 1291 * - double width
e89f66ec
FB		 1292 * - underline
1293 * - flashing
1294 */
cedd91d2 1295static void vga_draw_text(VGACommonState *s, int full_update)
e89f66ec
FB		 1296{
1297 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
cae334cd 1298 int cx_min, cx_max, linesize, x_incr, line, line1;
e89f66ec 1299 uint32_t offset, fgcol, bgcol, v, cursor_offset;
d1984194 1300 uint8_t *d1, *d, *src, *dest, *cursor_ptr;
e89f66ec
FB		 1301 const uint8_t *font_ptr, *font_base[2];
1302 int dup9, line_offset, depth_index;
1303 uint32_t *palette;
1304 uint32_t *ch_attr_ptr;
1305 vga_draw_glyph8_func *vga_draw_glyph8;
1306 vga_draw_glyph9_func *vga_draw_glyph9;
9aa0ff0b 1307 int64_t now = qemu_get_clock_ms(vm_clock);
e89f66ec 1308
e89f66ec 1309 /* compute font data address (in plane 2) */
5e55efc9 1310 v = s->sr[VGA_SEQ_CHARACTER_MAP];
1078f663 1311 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
e89f66ec
FB		 1312 if (offset != s->font_offsets[0]) {
1313 s->font_offsets[0] = offset;
1314 full_update = 1;
1315 }
1316 font_base[0] = s->vram_ptr + offset;
1317
1078f663 1318 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
e89f66ec
FB		 1319 font_base[1] = s->vram_ptr + offset;
1320 if (offset != s->font_offsets[1]) {
1321 s->font_offsets[1] = offset;
1322 full_update = 1;
1323 }
80763888 1324 if (s->plane_updated & (1 << 2) || s->chain4_alias) {
546fa6ab
FB		 1325 /* if the plane 2 was modified since the last display, it
1326 indicates the font may have been modified */
1327 s->plane_updated = 0;
1328 full_update = 1;
1329 }
799e709b 1330 full_update |= update_basic_params(s);
e89f66ec
FB		 1331
1332 line_offset = s->line_offset;
e89f66ec 1333
4c5e8c5c 1334 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1b296044
SW		 1335 if ((height * width) <= 1) {
1336 /* better than nothing: exit if transient size is too small */
1337 return;
1338 }
3294b949
FB		 1339 if ((height * width) > CH_ATTR_SIZE) {
1340 /* better than nothing: exit if transient size is too big */
1341 return;
1342 }
1343
799e709b
AL		 1344 if (width != s->last_width || height != s->last_height ||
1345 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1346 s->last_scr_width = width * cw;
1347 s->last_scr_height = height * cheight;
1348 qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
1349 s->last_depth = 0;
1350 s->last_width = width;
1351 s->last_height = height;
1352 s->last_ch = cheight;
1353 s->last_cw = cw;
1354 full_update = 1;
1355 }
7d957bd8
AL		 1356 s->rgb_to_pixel =
1357 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1358 full_update |= update_palette16(s);
1359 palette = s->last_palette;
1360 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1361
5e55efc9
BS		 1362 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1363 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
e89f66ec 1364 if (cursor_offset != s->cursor_offset ||
5e55efc9
BS		 1365 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1366 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
e89f66ec
FB		 1367 /* if the cursor position changed, we update the old and new
1368 chars */
1369 if (s->cursor_offset < CH_ATTR_SIZE)
1370 s->last_ch_attr[s->cursor_offset] = -1;
1371 if (cursor_offset < CH_ATTR_SIZE)
1372 s->last_ch_attr[cursor_offset] = -1;
1373 s->cursor_offset = cursor_offset;
5e55efc9
BS		 1374 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1375 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
e89f66ec 1376 }
39cf7803 1377 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
9aa0ff0b
JK		 1378 if (now >= s->cursor_blink_time) {
1379 s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2;
1380 s->cursor_visible_phase = !s->cursor_visible_phase;
1381 }
3b46e624 1382
d3079cd2 1383 depth_index = get_depth_index(s->ds);
17b0018b
FB		 1384 if (cw == 16)
1385 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1386 else
1387 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
e89f66ec 1388 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
3b46e624 1389
0e1f5a0c
AL		 1390 dest = ds_get_data(s->ds);
1391 linesize = ds_get_linesize(s->ds);
e89f66ec 1392 ch_attr_ptr = s->last_ch_attr;
d1984194 1393 line = 0;
1394 offset = s->start_addr * 4;
e89f66ec
FB		 1395 for(cy = 0; cy < height; cy++) {
1396 d1 = dest;
d1984194 1397 src = s->vram_ptr + offset;
e89f66ec
FB		 1398 cx_min = width;
1399 cx_max = -1;
1400 for(cx = 0; cx < width; cx++) {
1401 ch_attr = *(uint16_t *)src;
9aa0ff0b 1402 if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) {
e89f66ec
FB		 1403 if (cx < cx_min)
1404 cx_min = cx;
1405 if (cx > cx_max)
1406 cx_max = cx;
1407 *ch_attr_ptr = ch_attr;
e2542fe2 1408#ifdef HOST_WORDS_BIGENDIAN
e89f66ec
FB		 1409 ch = ch_attr >> 8;
1410 cattr = ch_attr & 0xff;
1411#else
1412 ch = ch_attr & 0xff;
1413 cattr = ch_attr >> 8;
1414#endif
1415 font_ptr = font_base[(cattr >> 3) & 1];
1416 font_ptr += 32 * 4 * ch;
1417 bgcol = palette[cattr >> 4];
1418 fgcol = palette[cattr & 0x0f];
17b0018b 1419 if (cw != 9) {
5fafdf24 1420 vga_draw_glyph8(d1, linesize,
e89f66ec
FB		 1421 font_ptr, cheight, fgcol, bgcol);
1422 } else {
1423 dup9 = 0;
5e55efc9
BS		 1424 if (ch >= 0xb0 && ch <= 0xdf &&
1425 (s->ar[VGA_ATC_MODE] & 0x04)) {
e89f66ec 1426 dup9 = 1;
5e55efc9 1427 }
5fafdf24 1428 vga_draw_glyph9(d1, linesize,
e89f66ec
FB		 1429 font_ptr, cheight, fgcol, bgcol, dup9);
1430 }
1431 if (src == cursor_ptr &&
9aa0ff0b
JK		 1432 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) &&
1433 s->cursor_visible_phase) {
e89f66ec
FB		 1434 int line_start, line_last, h;
1435 /* draw the cursor */
5e55efc9
BS		 1436 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1437 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
e89f66ec
FB		 1438 /* XXX: check that */
1439 if (line_last > cheight - 1)
1440 line_last = cheight - 1;
1441 if (line_last >= line_start && line_start < cheight) {
1442 h = line_last - line_start + 1;
1443 d = d1 + linesize * line_start;
17b0018b 1444 if (cw != 9) {
5fafdf24 1445 vga_draw_glyph8(d, linesize,
e89f66ec
FB		 1446 cursor_glyph, h, fgcol, bgcol);
1447 } else {
5fafdf24 1448 vga_draw_glyph9(d, linesize,
e89f66ec
FB		 1449 cursor_glyph, h, fgcol, bgcol, 1);
1450 }
1451 }
1452 }
1453 }
1454 d1 += x_incr;
1455 src += 4;
1456 ch_attr_ptr++;
1457 }
1458 if (cx_max != -1) {
5fafdf24 1459 dpy_update(s->ds, cx_min * cw, cy * cheight,
e89f66ec
FB		 1460 (cx_max - cx_min + 1) * cw, cheight);
1461 }
1462 dest += linesize * cheight;
cae334cd 1463 line1 = line + cheight;
1464 offset += line_offset;
1465 if (line < s->line_compare && line1 >= s->line_compare) {
d1984194 1466 offset = 0;
1467 }
cae334cd 1468 line = line1;
e89f66ec
FB		 1469 }
1470}
1471
17b0018b
FB		 1472enum {
1473 VGA_DRAW_LINE2,
1474 VGA_DRAW_LINE2D2,
1475 VGA_DRAW_LINE4,
1476 VGA_DRAW_LINE4D2,
1477 VGA_DRAW_LINE8D2,
1478 VGA_DRAW_LINE8,
1479 VGA_DRAW_LINE15,
1480 VGA_DRAW_LINE16,
4fa0f5d2 1481 VGA_DRAW_LINE24,
17b0018b
FB		 1482 VGA_DRAW_LINE32,
1483 VGA_DRAW_LINE_NB,
1484};
1485
68f04a3c 1486static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
e89f66ec
FB		 1487 vga_draw_line2_8,
1488 vga_draw_line2_16,
1489 vga_draw_line2_16,
1490 vga_draw_line2_32,
d3079cd2 1491 vga_draw_line2_32,
b29169d2
BS		 1492 vga_draw_line2_16,
1493 vga_draw_line2_16,
e89f66ec 1494
17b0018b
FB		 1495 vga_draw_line2d2_8,
1496 vga_draw_line2d2_16,
1497 vga_draw_line2d2_16,
1498 vga_draw_line2d2_32,
d3079cd2 1499 vga_draw_line2d2_32,
b29169d2
BS		 1500 vga_draw_line2d2_16,
1501 vga_draw_line2d2_16,
17b0018b 1502
e89f66ec
FB		 1503 vga_draw_line4_8,
1504 vga_draw_line4_16,
1505 vga_draw_line4_16,
1506 vga_draw_line4_32,
d3079cd2 1507 vga_draw_line4_32,
b29169d2
BS		 1508 vga_draw_line4_16,
1509 vga_draw_line4_16,
e89f66ec 1510
17b0018b
FB		 1511 vga_draw_line4d2_8,
1512 vga_draw_line4d2_16,
1513 vga_draw_line4d2_16,
1514 vga_draw_line4d2_32,
d3079cd2 1515 vga_draw_line4d2_32,
b29169d2
BS		 1516 vga_draw_line4d2_16,
1517 vga_draw_line4d2_16,
17b0018b
FB		 1518
1519 vga_draw_line8d2_8,
1520 vga_draw_line8d2_16,
1521 vga_draw_line8d2_16,
1522 vga_draw_line8d2_32,
d3079cd2 1523 vga_draw_line8d2_32,
b29169d2
BS		 1524 vga_draw_line8d2_16,
1525 vga_draw_line8d2_16,
17b0018b 1526
e89f66ec
FB		 1527 vga_draw_line8_8,
1528 vga_draw_line8_16,
1529 vga_draw_line8_16,
1530 vga_draw_line8_32,
d3079cd2 1531 vga_draw_line8_32,
b29169d2
BS		 1532 vga_draw_line8_16,
1533 vga_draw_line8_16,
e89f66ec
FB		 1534
1535 vga_draw_line15_8,
1536 vga_draw_line15_15,
1537 vga_draw_line15_16,
1538 vga_draw_line15_32,
d3079cd2 1539 vga_draw_line15_32bgr,
b29169d2
BS		 1540 vga_draw_line15_15bgr,
1541 vga_draw_line15_16bgr,
e89f66ec
FB		 1542
1543 vga_draw_line16_8,
1544 vga_draw_line16_15,
1545 vga_draw_line16_16,
1546 vga_draw_line16_32,
d3079cd2 1547 vga_draw_line16_32bgr,
b29169d2
BS		 1548 vga_draw_line16_15bgr,
1549 vga_draw_line16_16bgr,
e89f66ec 1550
4fa0f5d2
FB		 1551 vga_draw_line24_8,
1552 vga_draw_line24_15,
1553 vga_draw_line24_16,
1554 vga_draw_line24_32,
d3079cd2 1555 vga_draw_line24_32bgr,
b29169d2
BS		 1556 vga_draw_line24_15bgr,
1557 vga_draw_line24_16bgr,
4fa0f5d2 1558
e89f66ec
FB		 1559 vga_draw_line32_8,
1560 vga_draw_line32_15,
1561 vga_draw_line32_16,
1562 vga_draw_line32_32,
d3079cd2 1563 vga_draw_line32_32bgr,
b29169d2
BS		 1564 vga_draw_line32_15bgr,
1565 vga_draw_line32_16bgr,
d3079cd2
FB		 1566};
1567
cedd91d2 1568static int vga_get_bpp(VGACommonState *s)
798b0c25
FB		 1569{
1570 int ret;
a96d8bea 1571
798b0c25
FB		 1572 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1573 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
a96d8bea 1574 } else {
798b0c25
FB		 1575 ret = 0;
1576 }
1577 return ret;
1578}
1579
cedd91d2 1580static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
a130a41e
FB		 1581{
1582 int width, height;
3b46e624 1583
8454df8b
FB		 1584 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1585 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1586 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
a96d8bea 1587 } else {
5e55efc9
BS		 1588 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1589 height = s->cr[VGA_CRTC_V_DISP_END] |
1590 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1591 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
8454df8b
FB		 1592 height = (height + 1);
1593 }
a130a41e
FB		 1594 *pwidth = width;
1595 *pheight = height;
1596}
1597
cedd91d2 1598void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
a8aa669b
FB		 1599{
1600 int y;
1601 if (y1 >= VGA_MAX_HEIGHT)
1602 return;
1603 if (y2 >= VGA_MAX_HEIGHT)
1604 y2 = VGA_MAX_HEIGHT;
1605 for(y = y1; y < y2; y++) {
1606 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1607 }
1608}
1609
cedd91d2 1610static void vga_sync_dirty_bitmap(VGACommonState *s)
2bec46dc 1611{
b1950430 1612 memory_region_sync_dirty_bitmap(&s->vram);
2bec46dc
AL		 1613}
1614
50af3246
JQ		 1615void vga_dirty_log_start(VGACommonState *s)
1616{
b1950430 1617 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
b5cc6e32
AL		 1618}
1619
1620void vga_dirty_log_stop(VGACommonState *s)
1621{
b1950430 1622 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
b5cc6e32
AL		 1623}
1624
799e709b
AL		 1625/*
1626 * graphic modes
1627 */
cedd91d2 1628static void vga_draw_graphic(VGACommonState *s, int full_update)
e89f66ec 1629{
12c7e75a
AK		 1630 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1631 int width, height, shift_control, line_offset, bwidth, bits;
c227f099 1632 ram_addr_t page0, page1, page_min, page_max;
a07cf92a 1633 int disp_width, multi_scan, multi_run;
799e709b
AL		 1634 uint8_t *d;
1635 uint32_t v, addr1, addr;
1636 vga_draw_line_func *vga_draw_line;
1637
1638 full_update |= update_basic_params(s);
1639
1640 if (!full_update)
1641 vga_sync_dirty_bitmap(s);
2bec46dc 1642
a130a41e 1643 s->get_resolution(s, &width, &height);
17b0018b 1644 disp_width = width;
09a79b49 1645
5e55efc9
BS		 1646 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1647 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
799e709b 1648 if (shift_control != 1) {
5e55efc9
BS		 1649 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1650 - 1;
799e709b
AL		 1651 } else {
1652 /* in CGA modes, multi_scan is ignored */
1653 /* XXX: is it correct ? */
1654 multi_scan = double_scan;
1655 }
1656 multi_run = multi_scan;
17b0018b
FB		 1657 if (shift_control != s->shift_control ||
1658 double_scan != s->double_scan) {
799e709b 1659 full_update = 1;
e89f66ec 1660 s->shift_control = shift_control;
17b0018b 1661 s->double_scan = double_scan;
e89f66ec 1662 }
3b46e624 1663
aba35a6c 1664 if (shift_control == 0) {
5e55efc9 1665 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
aba35a6c 1666 disp_width <<= 1;
1667 }
1668 } else if (shift_control == 1) {
5e55efc9 1669 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
aba35a6c 1670 disp_width <<= 1;
1671 }
1672 }
1673
799e709b 1674 depth = s->get_bpp(s);
e3697092
AJ		 1675 if (s->line_offset != s->last_line_offset ||
1676 disp_width != s->last_width ||
1677 height != s->last_height ||
799e709b 1678 s->last_depth != depth) {
e2542fe2 1679#if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
e3697092 1680 if (depth == 16 || depth == 32) {
0da2ea1b 1681#else
1682 if (depth == 32) {
1683#endif
b8c18e4c
AL		 1684 qemu_free_displaysurface(s->ds);
1685 s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
1686 s->line_offset,
1687 s->vram_ptr + (s->start_addr * 4));
e2542fe2 1688#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
b8c18e4c 1689 s->ds->surface->pf = qemu_different_endianness_pixelformat(depth);
0da2ea1b 1690#endif
b8c18e4c 1691 dpy_resize(s->ds);
e3697092
AJ		 1692 } else {
1693 qemu_console_resize(s->ds, disp_width, height);
1694 }
1695 s->last_scr_width = disp_width;
1696 s->last_scr_height = height;
1697 s->last_width = disp_width;
1698 s->last_height = height;
1699 s->last_line_offset = s->line_offset;
1700 s->last_depth = depth;
799e709b
AL		 1701 full_update = 1;
1702 } else if (is_buffer_shared(s->ds->surface) &&
e3697092
AJ		 1703 (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) {
1704 s->ds->surface->data = s->vram_ptr + (s->start_addr * 4);
1705 dpy_setdata(s->ds);
1706 }
1707
1708 s->rgb_to_pixel =
1709 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1710
799e709b 1711 if (shift_control == 0) {
17b0018b 1712 full_update |= update_palette16(s);
5e55efc9 1713 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
17b0018b 1714 v = VGA_DRAW_LINE4D2;
17b0018b
FB		 1715 } else {
1716 v = VGA_DRAW_LINE4;
1717 }
15342721 1718 bits = 4;
799e709b 1719 } else if (shift_control == 1) {
17b0018b 1720 full_update |= update_palette16(s);
5e55efc9 1721 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
17b0018b 1722 v = VGA_DRAW_LINE2D2;
17b0018b
FB		 1723 } else {
1724 v = VGA_DRAW_LINE2;
1725 }
15342721 1726 bits = 4;
17b0018b 1727 } else {
798b0c25
FB		 1728 switch(s->get_bpp(s)) {
1729 default:
1730 case 0:
4fa0f5d2
FB		 1731 full_update |= update_palette256(s);
1732 v = VGA_DRAW_LINE8D2;
15342721 1733 bits = 4;
798b0c25
FB		 1734 break;
1735 case 8:
1736 full_update |= update_palette256(s);
1737 v = VGA_DRAW_LINE8;
15342721 1738 bits = 8;
798b0c25
FB		 1739 break;
1740 case 15:
1741 v = VGA_DRAW_LINE15;
15342721 1742 bits = 16;
798b0c25
FB		 1743 break;
1744 case 16:
1745 v = VGA_DRAW_LINE16;
15342721 1746 bits = 16;
798b0c25
FB		 1747 break;
1748 case 24:
1749 v = VGA_DRAW_LINE24;
15342721 1750 bits = 24;
798b0c25
FB		 1751 break;
1752 case 32:
1753 v = VGA_DRAW_LINE32;
15342721 1754 bits = 32;
798b0c25 1755 break;
4fa0f5d2 1756 }
17b0018b 1757 }
d3079cd2 1758 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
17b0018b 1759
7d957bd8 1760 if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
a8aa669b 1761 s->cursor_invalidate(s);
3b46e624 1762
e89f66ec 1763 line_offset = s->line_offset;
17b0018b 1764#if 0
f6c958c8 1765 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
5e55efc9
BS		 1766 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1767 s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]);
17b0018b 1768#endif
e89f66ec 1769 addr1 = (s->start_addr * 4);
15342721 1770 bwidth = (width * bits + 7) / 8;
39cf7803 1771 y_start = -1;
12c7e75a
AK		 1772 page_min = -1;
1773 page_max = 0;
0e1f5a0c
AL		 1774 d = ds_get_data(s->ds);
1775 linesize = ds_get_linesize(s->ds);
17b0018b 1776 y1 = 0;
e89f66ec
FB		 1777 for(y = 0; y < height; y++) {
1778 addr = addr1;
5e55efc9 1779 if (!(s->cr[VGA_CRTC_MODE] & 1)) {
17b0018b 1780 int shift;
e89f66ec 1781 /* CGA compatibility handling */
5e55efc9 1782 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
17b0018b 1783 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
e89f66ec 1784 }
5e55efc9 1785 if (!(s->cr[VGA_CRTC_MODE] & 2)) {
17b0018b 1786 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
e89f66ec 1787 }
734781c9 1788 update = full_update;
cd7a45c9
BS		 1789 page0 = addr;
1790 page1 = addr + bwidth - 1;
734781c9
JK		 1791 update |= memory_region_get_dirty(&s->vram, page0, page1 - page0,
1792 DIRTY_MEMORY_VGA);
a8aa669b
FB		 1793 /* explicit invalidation for the hardware cursor */
1794 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
e89f66ec 1795 if (update) {
39cf7803
FB		 1796 if (y_start < 0)
1797 y_start = y;
e89f66ec
FB		 1798 if (page0 < page_min)
1799 page_min = page0;
1800 if (page1 > page_max)
1801 page_max = page1;
7d957bd8
AL		 1802 if (!(is_buffer_shared(s->ds->surface))) {
1803 vga_draw_line(s, d, s->vram_ptr + addr, width);
1804 if (s->cursor_draw_line)
1805 s->cursor_draw_line(s, d, y);
1806 }
39cf7803
FB		 1807 } else {
1808 if (y_start >= 0) {
1809 /* flush to display */
5fafdf24 1810 dpy_update(s->ds, 0, y_start,
799e709b 1811 disp_width, y - y_start);
39cf7803
FB		 1812 y_start = -1;
1813 }
e89f66ec 1814 }
a07cf92a 1815 if (!multi_run) {
5e55efc9 1816 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
f6c958c8
FB		 1817 if ((y1 & mask) == mask)
1818 addr1 += line_offset;
1819 y1++;
799e709b 1820 multi_run = multi_scan;
a07cf92a
FB		 1821 } else {
1822 multi_run--;
e89f66ec 1823 }
f6c958c8
FB		 1824 /* line compare acts on the displayed lines */
1825 if (y == s->line_compare)
1826 addr1 = 0;
e89f66ec
FB		 1827 d += linesize;
1828 }
39cf7803
FB		 1829 if (y_start >= 0) {
1830 /* flush to display */
5fafdf24 1831 dpy_update(s->ds, 0, y_start,
799e709b 1832 disp_width, y - y_start);
39cf7803 1833 }
e89f66ec 1834 /* reset modified pages */
12c7e75a 1835 if (page_max >= page_min) {
b1950430
AK		 1836 memory_region_reset_dirty(&s->vram,
1837 page_min,
cd7a45c9 1838 page_max - page_min,
b1950430 1839 DIRTY_MEMORY_VGA);
e89f66ec 1840 }
a8aa669b 1841 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
e89f66ec
FB		 1842}
1843
cedd91d2 1844static void vga_draw_blank(VGACommonState *s, int full_update)
2aebb3eb
FB		 1845{
1846 int i, w, val;
1847 uint8_t *d;
1848
1849 if (!full_update)
1850 return;
1851 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1852 return;
2bec46dc 1853
7d957bd8
AL		 1854 s->rgb_to_pixel =
1855 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
0e1f5a0c 1856 if (ds_get_bits_per_pixel(s->ds) == 8)
2aebb3eb
FB		 1857 val = s->rgb_to_pixel(0, 0, 0);
1858 else
1859 val = 0;
0e1f5a0c
AL		 1860 w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1861 d = ds_get_data(s->ds);
2aebb3eb
FB		 1862 for(i = 0; i < s->last_scr_height; i++) {
1863 memset(d, val, w);
0e1f5a0c 1864 d += ds_get_linesize(s->ds);
2aebb3eb 1865 }
5fafdf24 1866 dpy_update(s->ds, 0, 0,
2aebb3eb
FB		 1867 s->last_scr_width, s->last_scr_height);
1868}
1869
799e709b
AL		 1870#define GMODE_TEXT 0
1871#define GMODE_GRAPH 1
1872#define GMODE_BLANK 2
1873
95219897 1874static void vga_update_display(void *opaque)
e89f66ec 1875{
cedd91d2 1876 VGACommonState *s = opaque;
799e709b 1877 int full_update, graphic_mode;
e89f66ec 1878
e9a07334
JK		 1879 qemu_flush_coalesced_mmio_buffer();
1880
0e1f5a0c 1881 if (ds_get_bits_per_pixel(s->ds) == 0) {
0f35920c 1882 /* nothing to do */
59a983b9 1883 } else {
3098b9fd 1884 full_update = 0;
df800210 1885 if (!(s->ar_index & 0x20)) {
799e709b
AL		 1886 graphic_mode = GMODE_BLANK;
1887 } else {
5e55efc9 1888 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
799e709b
AL		 1889 }
1890 if (graphic_mode != s->graphic_mode) {
1891 s->graphic_mode = graphic_mode;
9aa0ff0b 1892 s->cursor_blink_time = qemu_get_clock_ms(vm_clock);
799e709b
AL		 1893 full_update = 1;
1894 }
1895 switch(graphic_mode) {
2aebb3eb 1896 case GMODE_TEXT:
e89f66ec 1897 vga_draw_text(s, full_update);
2aebb3eb
FB		 1898 break;
1899 case GMODE_GRAPH:
1900 vga_draw_graphic(s, full_update);
1901 break;
1902 case GMODE_BLANK:
1903 default:
1904 vga_draw_blank(s, full_update);
1905 break;
1906 }
e89f66ec
FB		 1907 }
1908}
1909
a130a41e 1910/* force a full display refresh */
95219897 1911static void vga_invalidate_display(void *opaque)
a130a41e 1912{
cedd91d2 1913 VGACommonState *s = opaque;
3b46e624 1914
3098b9fd
AJ		 1915 s->last_width = -1;
1916 s->last_height = -1;
a130a41e
FB		 1917}
1918
03a3e7ba 1919void vga_common_reset(VGACommonState *s)
e89f66ec 1920{
6e6b7363
BS		 1921 s->sr_index = 0;
1922 memset(s->sr, '\0', sizeof(s->sr));
1923 s->gr_index = 0;
1924 memset(s->gr, '\0', sizeof(s->gr));
1925 s->ar_index = 0;
1926 memset(s->ar, '\0', sizeof(s->ar));
1927 s->ar_flip_flop = 0;
1928 s->cr_index = 0;
1929 memset(s->cr, '\0', sizeof(s->cr));
1930 s->msr = 0;
1931 s->fcr = 0;
1932 s->st00 = 0;
1933 s->st01 = 0;
1934 s->dac_state = 0;
1935 s->dac_sub_index = 0;
1936 s->dac_read_index = 0;
1937 s->dac_write_index = 0;
1938 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1939 s->dac_8bit = 0;
1940 memset(s->palette, '\0', sizeof(s->palette));
1941 s->bank_offset = 0;
6e6b7363
BS		 1942 s->vbe_index = 0;
1943 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
af92284b 1944 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
6e6b7363
BS		 1945 s->vbe_start_addr = 0;
1946 s->vbe_line_offset = 0;
1947 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
6e6b7363 1948 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
799e709b 1949 s->graphic_mode = -1; /* force full update */
6e6b7363
BS		 1950 s->shift_control = 0;
1951 s->double_scan = 0;
1952 s->line_offset = 0;
1953 s->line_compare = 0;
1954 s->start_addr = 0;
1955 s->plane_updated = 0;
1956 s->last_cw = 0;
1957 s->last_ch = 0;
1958 s->last_width = 0;
1959 s->last_height = 0;
1960 s->last_scr_width = 0;
1961 s->last_scr_height = 0;
1962 s->cursor_start = 0;
1963 s->cursor_end = 0;
1964 s->cursor_offset = 0;
1965 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1966 memset(s->last_palette, '\0', sizeof(s->last_palette));
1967 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1968 switch (vga_retrace_method) {
1969 case VGA_RETRACE_DUMB:
1970 break;
1971 case VGA_RETRACE_PRECISE:
1972 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1973 break;
1974 }
80763888 1975 vga_update_memory_access(s);
e89f66ec
FB		 1976}
1977
03a3e7ba
JQ		 1978static void vga_reset(void *opaque)
1979{
cedd91d2 1980 VGACommonState *s = opaque;
03a3e7ba
JQ		 1981 vga_common_reset(s);
1982}
1983
4d3b6f6e
AZ		 1984#define TEXTMODE_X(x) ((x) % width)
1985#define TEXTMODE_Y(x) ((x) / width)
1986#define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1987 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1988/* relay text rendering to the display driver
1989 * instead of doing a full vga_update_display() */
c227f099 1990static void vga_update_text(void *opaque, console_ch_t *chardata)
4d3b6f6e 1991{
cedd91d2 1992 VGACommonState *s = opaque;
799e709b 1993 int graphic_mode, i, cursor_offset, cursor_visible;
4d3b6f6e
AZ		 1994 int cw, cheight, width, height, size, c_min, c_max;
1995 uint32_t *src;
c227f099 1996 console_ch_t *dst, val;
4d3b6f6e 1997 char msg_buffer[80];
799e709b
AL		 1998 int full_update = 0;
1999
e9a07334
JK		 2000 qemu_flush_coalesced_mmio_buffer();
2001
799e709b
AL		 2002 if (!(s->ar_index & 0x20)) {
2003 graphic_mode = GMODE_BLANK;
2004 } else {
5e55efc9 2005 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
799e709b
AL		 2006 }
2007 if (graphic_mode != s->graphic_mode) {
2008 s->graphic_mode = graphic_mode;
2009 full_update = 1;
2010 }
2011 if (s->last_width == -1) {
2012 s->last_width = 0;
2013 full_update = 1;
2014 }
4d3b6f6e 2015
799e709b 2016 switch (graphic_mode) {
4d3b6f6e
AZ		 2017 case GMODE_TEXT:
2018 /* TODO: update palette */
799e709b 2019 full_update |= update_basic_params(s);
4d3b6f6e 2020
799e709b 2021 /* total width & height */
5e55efc9 2022 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
799e709b 2023 cw = 8;
5e55efc9 2024 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
799e709b 2025 cw = 9;
5e55efc9
BS		 2026 }
2027 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
799e709b 2028 cw = 16; /* NOTE: no 18 pixel wide */
5e55efc9
BS		 2029 }
2030 width = (s->cr[VGA_CRTC_H_DISP] + 1);
2031 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
799e709b
AL		 2032 /* ugly hack for CGA 160x100x16 - explain me the logic */
2033 height = 100;
2034 } else {
5e55efc9
BS		 2035 height = s->cr[VGA_CRTC_V_DISP_END] |
2036 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
2037 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
799e709b 2038 height = (height + 1) / cheight;
4d3b6f6e
AZ		 2039 }
2040
2041 size = (height * width);
2042 if (size > CH_ATTR_SIZE) {
2043 if (!full_update)
2044 return;
2045
363a37d5
BS		 2046 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2047 width, height);
4d3b6f6e
AZ		 2048 break;
2049 }
2050
799e709b
AL		 2051 if (width != s->last_width || height != s->last_height ||
2052 cw != s->last_cw || cheight != s->last_ch) {
2053 s->last_scr_width = width * cw;
2054 s->last_scr_height = height * cheight;
2055 s->ds->surface->width = width;
2056 s->ds->surface->height = height;
2057 dpy_resize(s->ds);
2058 s->last_width = width;
2059 s->last_height = height;
2060 s->last_ch = cheight;
2061 s->last_cw = cw;
2062 full_update = 1;
2063 }
2064
4d3b6f6e 2065 /* Update "hardware" cursor */
5e55efc9
BS		 2066 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
2067 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
4d3b6f6e 2068 if (cursor_offset != s->cursor_offset ||
5e55efc9
BS		 2069 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
2070 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
2071 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
4d3b6f6e
AZ		 2072 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
2073 dpy_cursor(s->ds,
2074 TEXTMODE_X(cursor_offset),
2075 TEXTMODE_Y(cursor_offset));
2076 else
2077 dpy_cursor(s->ds, -1, -1);
2078 s->cursor_offset = cursor_offset;
5e55efc9
BS		 2079 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
2080 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
4d3b6f6e
AZ		 2081 }
2082
2083 src = (uint32_t *) s->vram_ptr + s->start_addr;
2084 dst = chardata;
2085
2086 if (full_update) {
2087 for (i = 0; i < size; src ++, dst ++, i ++)
9ae19b65 2088 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
4d3b6f6e
AZ		 2089
2090 dpy_update(s->ds, 0, 0, width, height);
2091 } else {
2092 c_max = 0;
2093
2094 for (i = 0; i < size; src ++, dst ++, i ++) {
9ae19b65 2095 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
4d3b6f6e
AZ		 2096 if (*dst != val) {
2097 *dst = val;
2098 c_max = i;
2099 break;
2100 }
2101 }
2102 c_min = i;
2103 for (; i < size; src ++, dst ++, i ++) {
9ae19b65 2104 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
4d3b6f6e
AZ		 2105 if (*dst != val) {
2106 *dst = val;
2107 c_max = i;
2108 }
2109 }
2110
2111 if (c_min <= c_max) {
2112 i = TEXTMODE_Y(c_min);
2113 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2114 }
2115 }
2116
2117 return;
2118 case GMODE_GRAPH:
2119 if (!full_update)
2120 return;
2121
2122 s->get_resolution(s, &width, &height);
363a37d5
BS		 2123 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2124 width, height);
4d3b6f6e
AZ		 2125 break;
2126 case GMODE_BLANK:
2127 default:
2128 if (!full_update)
2129 return;
2130
363a37d5 2131 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
4d3b6f6e
AZ		 2132 break;
2133 }
2134
2135 /* Display a message */
5228c2d3
AZ		 2136 s->last_width = 60;
2137 s->last_height = height = 3;
4d3b6f6e 2138 dpy_cursor(s->ds, -1, -1);
7d957bd8
AL		 2139 s->ds->surface->width = s->last_width;
2140 s->ds->surface->height = height;
2141 dpy_resize(s->ds);
4d3b6f6e 2142
5228c2d3 2143 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
4d3b6f6e
AZ		 2144 console_write_ch(dst ++, ' ');
2145
2146 size = strlen(msg_buffer);
5228c2d3
AZ		 2147 width = (s->last_width - size) / 2;
2148 dst = chardata + s->last_width + width;
4d3b6f6e
AZ		 2149 for (i = 0; i < size; i ++)
2150 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2151
5228c2d3 2152 dpy_update(s->ds, 0, 0, s->last_width, height);
4d3b6f6e
AZ		 2153}
2154
a8170e5e 2155static uint64_t vga_mem_read(void *opaque, hwaddr addr,
b1950430
AK		 2156 unsigned size)
2157{
2158 VGACommonState *s = opaque;
2159
b2a5e761 2160 return vga_mem_readb(s, addr);
b1950430 2161}
e89f66ec 2162
a8170e5e 2163static void vga_mem_write(void *opaque, hwaddr addr,
b1950430
AK		 2164 uint64_t data, unsigned size)
2165{
2166 VGACommonState *s = opaque;
2167
b2a5e761 2168 return vga_mem_writeb(s, addr, data);
b1950430
AK		 2169}
2170
2171const MemoryRegionOps vga_mem_ops = {
2172 .read = vga_mem_read,
2173 .write = vga_mem_write,
2174 .endianness = DEVICE_LITTLE_ENDIAN,
b2a5e761
AK		 2175 .impl = {
2176 .min_access_size = 1,
2177 .max_access_size = 1,
2178 },
e89f66ec
FB		 2179};
2180
11b6b345 2181static int vga_common_post_load(void *opaque, int version_id)
b0a21b53 2182{
0d65ddc3 2183 VGACommonState *s = opaque;
11b6b345
JQ		 2184
2185 /* force refresh */
2186 s->graphic_mode = -1;
2187 return 0;
2188}
2189
2190const VMStateDescription vmstate_vga_common = {
2191 .name = "vga",
2192 .version_id = 2,
2193 .minimum_version_id = 2,
2194 .minimum_version_id_old = 2,
2195 .post_load = vga_common_post_load,
2196 .fields = (VMStateField []) {
2197 VMSTATE_UINT32(latch, VGACommonState),
2198 VMSTATE_UINT8(sr_index, VGACommonState),
2199 VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2200 VMSTATE_UINT8(gr_index, VGACommonState),
2201 VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2202 VMSTATE_UINT8(ar_index, VGACommonState),
2203 VMSTATE_BUFFER(ar, VGACommonState),
2204 VMSTATE_INT32(ar_flip_flop, VGACommonState),
2205 VMSTATE_UINT8(cr_index, VGACommonState),
2206 VMSTATE_BUFFER(cr, VGACommonState),
2207 VMSTATE_UINT8(msr, VGACommonState),
2208 VMSTATE_UINT8(fcr, VGACommonState),
2209 VMSTATE_UINT8(st00, VGACommonState),
2210 VMSTATE_UINT8(st01, VGACommonState),
2211
2212 VMSTATE_UINT8(dac_state, VGACommonState),
2213 VMSTATE_UINT8(dac_sub_index, VGACommonState),
2214 VMSTATE_UINT8(dac_read_index, VGACommonState),
2215 VMSTATE_UINT8(dac_write_index, VGACommonState),
2216 VMSTATE_BUFFER(dac_cache, VGACommonState),
2217 VMSTATE_BUFFER(palette, VGACommonState),
2218
2219 VMSTATE_INT32(bank_offset, VGACommonState),
2220 VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
11b6b345
JQ		 2221 VMSTATE_UINT16(vbe_index, VGACommonState),
2222 VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2223 VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2224 VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2225 VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
11b6b345
JQ		 2226 VMSTATE_END_OF_LIST()
2227 }
2228};
2229
4a1e244e 2230void vga_common_init(VGACommonState *s)
e89f66ec 2231{
17b0018b 2232 int i, j, v, b;
e89f66ec
FB		 2233
2234 for(i = 0;i < 256; i++) {
2235 v = 0;
2236 for(j = 0; j < 8; j++) {
2237 v |= ((i >> j) & 1) << (j * 4);
2238 }
2239 expand4[i] = v;
2240
2241 v = 0;
2242 for(j = 0; j < 4; j++) {
2243 v |= ((i >> (2 * j)) & 3) << (j * 4);
2244 }
2245 expand2[i] = v;
2246 }
17b0018b
FB		 2247 for(i = 0; i < 16; i++) {
2248 v = 0;
2249 for(j = 0; j < 4; j++) {
2250 b = ((i >> j) & 1);
2251 v |= b << (2 * j);
2252 v |= b << (2 * j + 1);
2253 }
2254 expand4to8[i] = v;
2255 }
e89f66ec 2256
4a1e244e
GH		 2257 /* valid range: 1 MB -> 256 MB */
2258 s->vram_size = 1024 * 1024;
2259 while (s->vram_size < (s->vram_size_mb << 20) &&
2260 s->vram_size < (256 << 20)) {
2261 s->vram_size <<= 1;
2262 }
2263 s->vram_size_mb = s->vram_size >> 20;
2264
2a3138ab 2265 s->is_vbe_vmstate = 1;
4a1e244e 2266 memory_region_init_ram(&s->vram, "vga.vram", s->vram_size);
c5705a77 2267 vmstate_register_ram_global(&s->vram);
c65adf9b 2268 xen_register_framebuffer(&s->vram);
b1950430 2269 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
798b0c25
FB		 2270 s->get_bpp = vga_get_bpp;
2271 s->get_offsets = vga_get_offsets;
a130a41e 2272 s->get_resolution = vga_get_resolution;
d34cab9f
TS		 2273 s->update = vga_update_display;
2274 s->invalidate = vga_invalidate_display;
2275 s->screen_dump = vga_screen_dump;
4d3b6f6e 2276 s->text_update = vga_update_text;
cb5a7aa8 2277 switch (vga_retrace_method) {
2278 case VGA_RETRACE_DUMB:
2279 s->retrace = vga_dumb_retrace;
2280 s->update_retrace_info = vga_dumb_update_retrace_info;
2281 break;
2282
2283 case VGA_RETRACE_PRECISE:
2284 s->retrace = vga_precise_retrace;
2285 s->update_retrace_info = vga_precise_update_retrace_info;
cb5a7aa8 2286 break;
2287 }
b1950430 2288 vga_dirty_log_start(s);
798b0c25
FB		 2289}
2290
0a039dc7
RH		 2291static const MemoryRegionPortio vga_portio_list[] = {
2292 { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2293 { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2294 { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2295 { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2296 { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2297 PORTIO_END_OF_LIST(),
2298};
e89f66ec 2299
0a039dc7
RH		 2300static const MemoryRegionPortio vbe_portio_list[] = {
2301 { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2302# ifdef TARGET_I386
2303 { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2304# else
2305 { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2306# endif
2307 PORTIO_END_OF_LIST(),
2308};
4fa0f5d2 2309
0a039dc7
RH		 2310/* Used by both ISA and PCI */
2311MemoryRegion *vga_init_io(VGACommonState *s,
2312 const MemoryRegionPortio **vga_ports,
2313 const MemoryRegionPortio **vbe_ports)
2314{
2315 MemoryRegion *vga_mem;
09a79b49 2316
0a039dc7 2317 *vga_ports = vga_portio_list;
0a039dc7 2318 *vbe_ports = vbe_portio_list;
4fa0f5d2 2319
7267c094 2320 vga_mem = g_malloc(sizeof(*vga_mem));
b1950430
AK		 2321 memory_region_init_io(vga_mem, &vga_mem_ops, s,
2322 "vga-lowmem", 0x20000);
bd8f2f5d 2323 memory_region_set_flush_coalesced(vga_mem);
b1950430
AK		 2324
2325 return vga_mem;
7435b791
BS		 2326}
2327
0a039dc7
RH		 2328void vga_init(VGACommonState *s, MemoryRegion *address_space,
2329 MemoryRegion *address_space_io, bool init_vga_ports)
7435b791 2330{
b1950430 2331 MemoryRegion *vga_io_memory;
0a039dc7
RH		 2332 const MemoryRegionPortio *vga_ports, *vbe_ports;
2333 PortioList *vga_port_list = g_new(PortioList, 1);
2334 PortioList *vbe_port_list = g_new(PortioList, 1);
7435b791
BS		 2335
2336 qemu_register_reset(vga_reset, s);
2337
2338 s->bank_offset = 0;
2339
80763888
JK		 2340 s->legacy_address_space = address_space;
2341
0a039dc7 2342 vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports);
be20f9e9 2343 memory_region_add_subregion_overlap(address_space,
b1950430
AK		 2344 isa_mem_base + 0x000a0000,
2345 vga_io_memory,
2346 1);
2347 memory_region_set_coalescing(vga_io_memory);
0a039dc7
RH		 2348 if (init_vga_ports) {
2349 portio_list_init(vga_port_list, vga_ports, s, "vga");
2350 portio_list_add(vga_port_list, address_space_io, 0x3b0);
2351 }
2352 if (vbe_ports) {
2353 portio_list_init(vbe_port_list, vbe_ports, s, "vbe");
2354 portio_list_add(vbe_port_list, address_space_io, 0x1ce);
2355 }
d2269f6f
FB		 2356}
2357
be20f9e9 2358void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
f0138a63 2359{
8294a64d
AK		 2360 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2361 * so use an alias to avoid double-mapping the same region.
2362 */
2363 memory_region_init_alias(&s->vram_vbe, "vram.vbe",
2364 &s->vram, 0, memory_region_size(&s->vram));
f0138a63 2365 /* XXX: use optimized standard vga accesses */
be20f9e9 2366 memory_region_add_subregion(system_memory,
b1950430 2367 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
8294a64d 2368 &s->vram_vbe);
f0138a63 2369 s->vbe_mapped = 1;
f0138a63 2370}
59a983b9
FB		 2371/********************************************************/
2372/* vga screen dump */
2373
d663174d 2374void ppm_save(const char *filename, struct DisplaySurface *ds, Error **errp)
59a983b9
FB		 2375{
2376 FILE *f;
2377 uint8_t *d, *d1;
e07d630a 2378 uint32_t v;
59a983b9 2379 int y, x;
e07d630a 2380 uint8_t r, g, b;
f8e378f2
AK		 2381 int ret;
2382 char *linebuf, *pbuf;
59a983b9 2383
72750018 2384 trace_ppm_save(filename, ds);
59a983b9 2385 f = fopen(filename, "wb");
d663174d
LC		 2386 if (!f) {
2387 error_setg(errp, "failed to open file '%s': %s", filename,
2388 strerror(errno));
2389 return;
2390 }
2391 ret = fprintf(f, "P6\n%d %d\n%d\n", ds->width, ds->height, 255);
2392 if (ret < 0) {
2393 linebuf = NULL;
2394 goto write_err;
2395 }
7267c094 2396 linebuf = g_malloc(ds->width * 3);
e07d630a
AL		 2397 d1 = ds->data;
2398 for(y = 0; y < ds->height; y++) {
59a983b9 2399 d = d1;
f8e378f2 2400 pbuf = linebuf;
e07d630a
AL		 2401 for(x = 0; x < ds->width; x++) {
2402 if (ds->pf.bits_per_pixel == 32)
2403 v = *(uint32_t *)d;
2404 else
2405 v = (uint32_t) (*(uint16_t *)d);
a0f42610
AK		 2406 /* Limited to 8 or fewer bits per channel: */
2407 r = ((v >> ds->pf.rshift) & ds->pf.rmax) << (8 - ds->pf.rbits);
2408 g = ((v >> ds->pf.gshift) & ds->pf.gmax) << (8 - ds->pf.gbits);
2409 b = ((v >> ds->pf.bshift) & ds->pf.bmax) << (8 - ds->pf.bbits);
f8e378f2
AK		 2410 *pbuf++ = r;
2411 *pbuf++ = g;
2412 *pbuf++ = b;
e07d630a 2413 d += ds->pf.bytes_per_pixel;
59a983b9 2414 }
e07d630a 2415 d1 += ds->linesize;
d663174d 2416 clearerr(f);
f8e378f2
AK		 2417 ret = fwrite(linebuf, 1, pbuf - linebuf, f);
2418 (void)ret;
d663174d
LC		 2419 if (ferror(f)) {
2420 goto write_err;
2421 }
59a983b9 2422 }
d663174d
LC		 2423
2424out:
7267c094 2425 g_free(linebuf);
59a983b9 2426 fclose(f);
d663174d
LC		 2427 return;
2428
2429write_err:
2430 error_setg(errp, "failed to write to file '%s': %s", filename,
2431 strerror(errno));
2432 unlink(filename);
2433 goto out;
59a983b9
FB		 2434}
2435
4c5e8c5c
BS		 2436/* save the vga display in a PPM image even if no display is
2437 available */
d7098135
LC		 2438static void vga_screen_dump(void *opaque, const char *filename, bool cswitch,
2439 Error **errp)
4c5e8c5c 2440{
cedd91d2 2441 VGACommonState *s = opaque;
4c5e8c5c 2442
45efb161
GH		 2443 if (cswitch) {
2444 vga_invalidate_display(s);
45efb161 2445 }
08c4ea29 2446 vga_hw_update();
d663174d 2447 ppm_save(filename, s->ds->surface, errp);
4c5e8c5c 2448}
QEMU mirror