[mirror_qemu.git] / hw / vga_int.h

/*
 * QEMU internal VGA defines.
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#define MSR_COLOR_EMULATION 0x01
#define MSR_PAGE_SELECT     0x20

#define ST01_V_RETRACE      0x08
#define ST01_DISP_ENABLE    0x01

/* bochs VBE support */
#define CONFIG_BOCHS_VBE

#define VBE_DISPI_MAX_XRES              1600
#define VBE_DISPI_MAX_YRES              1200
#define VBE_DISPI_MAX_BPP               32

#define VBE_DISPI_INDEX_ID              0x0
#define VBE_DISPI_INDEX_XRES            0x1
#define VBE_DISPI_INDEX_YRES            0x2
#define VBE_DISPI_INDEX_BPP             0x3
#define VBE_DISPI_INDEX_ENABLE          0x4
#define VBE_DISPI_INDEX_BANK            0x5
#define VBE_DISPI_INDEX_VIRT_WIDTH      0x6
#define VBE_DISPI_INDEX_VIRT_HEIGHT     0x7
#define VBE_DISPI_INDEX_X_OFFSET        0x8
#define VBE_DISPI_INDEX_Y_OFFSET        0x9
#define VBE_DISPI_INDEX_NB              0xa
     
#define VBE_DISPI_ID0                   0xB0C0
#define VBE_DISPI_ID1                   0xB0C1
#define VBE_DISPI_ID2                   0xB0C2
#define VBE_DISPI_ID3                   0xB0C3
#define VBE_DISPI_ID4                   0xB0C4
 
#define VBE_DISPI_DISABLED              0x00
#define VBE_DISPI_ENABLED               0x01
#define VBE_DISPI_GETCAPS               0x02
#define VBE_DISPI_8BIT_DAC              0x20
#define VBE_DISPI_LFB_ENABLED           0x40
#define VBE_DISPI_NOCLEARMEM            0x80
 
#define VBE_DISPI_LFB_PHYSICAL_ADDRESS  0xE0000000

#ifdef CONFIG_BOCHS_VBE

#define VGA_STATE_COMMON_BOCHS_VBE              \
    uint16_t vbe_index;                         \
    uint16_t vbe_regs[VBE_DISPI_INDEX_NB];      \
    uint32_t vbe_start_addr;                    \
    uint32_t vbe_line_offset;                   \
    uint32_t vbe_bank_mask;

#else

#define VGA_STATE_COMMON_BOCHS_VBE

#endif /* !CONFIG_BOCHS_VBE */

#define CH_ATTR_SIZE (160 * 100)
#define VGA_MAX_HEIGHT 2048

#define VGA_STATE_COMMON                                                \
    uint8_t *vram_ptr;                                                  \
    unsigned long vram_offset;                                          \
    unsigned int vram_size;                                             \
    unsigned long bios_offset;                                          \
    unsigned int bios_size;                                             \
    target_phys_addr_t base_ctrl;                                       \
    int it_shift;                                                       \
    PCIDevice *pci_dev;                                                 \
    uint32_t latch;                                                     \
    uint8_t sr_index;                                                   \
    uint8_t sr[256];                                                    \
    uint8_t gr_index;                                                   \
    uint8_t gr[256];                                                    \
    uint8_t ar_index;                                                   \
    uint8_t ar[21];                                                     \
    int ar_flip_flop;                                                   \
    uint8_t cr_index;                                                   \
    uint8_t cr[256]; /* CRT registers */                                \
    uint8_t msr; /* Misc Output Register */                             \
    uint8_t fcr; /* Feature Control Register */                         \
    uint8_t st00; /* status 0 */                                        \
    uint8_t st01; /* status 1 */                                        \
    uint8_t dac_state;                                                  \
    uint8_t dac_sub_index;                                              \
    uint8_t dac_read_index;                                             \
    uint8_t dac_write_index;                                            \
    uint8_t dac_cache[3]; /* used when writing */                       \
    int dac_8bit;                                                       \
    uint8_t palette[768];                                               \
    int32_t bank_offset;                                                \
    int (*get_bpp)(struct VGAState *s);                                 \
    void (*get_offsets)(struct VGAState *s,                             \
                        uint32_t *pline_offset,                         \
                        uint32_t *pstart_addr,                          \
                        uint32_t *pline_compare);                       \
    void (*get_resolution)(struct VGAState *s,                          \
                        int *pwidth,                                    \
                        int *pheight);                                  \
    VGA_STATE_COMMON_BOCHS_VBE                                          \
    /* display refresh support */                                       \
    DisplayState *ds;                                                   \
    uint32_t font_offsets[2];                                           \
    int graphic_mode;                                                   \
    uint8_t shift_control;                                              \
    uint8_t double_scan;                                                \
    uint32_t line_offset;                                               \
    uint32_t line_compare;                                              \
    uint32_t start_addr;                                                \
    uint32_t plane_updated;                                             \
    uint8_t last_cw, last_ch;                                           \
    uint32_t last_width, last_height; /* in chars or pixels */          \
    uint32_t last_scr_width, last_scr_height; /* in pixels */           \
    uint8_t cursor_start, cursor_end;                                   \
    uint32_t cursor_offset;                                             \
    unsigned int (*rgb_to_pixel)(unsigned int r,                        \
                                 unsigned int g, unsigned b);           \
    vga_hw_update_ptr update;                                           \
    vga_hw_invalidate_ptr invalidate;                                   \
    vga_hw_screen_dump_ptr screen_dump;                                 \
    /* hardware mouse cursor support */                                 \
    uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];                  \
    void (*cursor_invalidate)(struct VGAState *s);                      \
    void (*cursor_draw_line)(struct VGAState *s, uint8_t *d, int y);    \
    /* tell for each page if it has been updated since the last time */ \
    uint32_t last_palette[256];                                         \
    uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */


typedef struct VGAState {
    VGA_STATE_COMMON
} VGAState;

static inline int c6_to_8(int v)
{
    int b;
    v &= 0x3f;
    b = v & 1;
    return (v << 2) | (b << 1) | b;
}

void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
                     unsigned long vga_ram_offset, int vga_ram_size);
void vga_init(VGAState *s);
uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
void vga_invalidate_scanlines(VGAState *s, int y1, int y2);
int ppm_save(const char *filename, uint8_t *data,
             int w, int h, int linesize);

void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1,
                            int poffset, int w,
                            unsigned int color0, unsigned int color1,
                            unsigned int color_xor);
void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1,
                             int poffset, int w,
                             unsigned int color0, unsigned int color1,
                             unsigned int color_xor);
void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
                             int poffset, int w,
                             unsigned int color0, unsigned int color1,
                             unsigned int color_xor);

extern const uint8_t sr_mask[8];
extern const uint8_t gr_mask[16];
Commit	Line	Data
798b0c25 FB	1	/*
798b0c25 FB	2	* QEMU internal VGA defines.
5fafdf24	3	*
798b0c25	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
798b0c25 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#define MSR_COLOR_EMULATION 0x01
	25	#define MSR_PAGE_SELECT 0x20
	26
	27	#define ST01_V_RETRACE 0x08
	28	#define ST01_DISP_ENABLE 0x01
	29
	30	/* bochs VBE support */
	31	#define CONFIG_BOCHS_VBE
	32
8454df8b FB	33	#define VBE_DISPI_MAX_XRES 1600
	34	#define VBE_DISPI_MAX_YRES 1200
	35	#define VBE_DISPI_MAX_BPP 32
798b0c25 FB	36
	37	#define VBE_DISPI_INDEX_ID 0x0
	38	#define VBE_DISPI_INDEX_XRES 0x1
	39	#define VBE_DISPI_INDEX_YRES 0x2
	40	#define VBE_DISPI_INDEX_BPP 0x3
	41	#define VBE_DISPI_INDEX_ENABLE 0x4
	42	#define VBE_DISPI_INDEX_BANK 0x5
	43	#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
	44	#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
	45	#define VBE_DISPI_INDEX_X_OFFSET 0x8
	46	#define VBE_DISPI_INDEX_Y_OFFSET 0x9
	47	#define VBE_DISPI_INDEX_NB 0xa
5fafdf24	48
798b0c25 FB	49	#define VBE_DISPI_ID0 0xB0C0
	50	#define VBE_DISPI_ID1 0xB0C1
	51	#define VBE_DISPI_ID2 0xB0C2
37dd208d FB	52	#define VBE_DISPI_ID3 0xB0C3
37dd208d FB	53	#define VBE_DISPI_ID4 0xB0C4
5fafdf24	54
798b0c25 FB	55	#define VBE_DISPI_DISABLED 0x00
798b0c25 FB	56	#define VBE_DISPI_ENABLED 0x01
8454df8b FB	57	#define VBE_DISPI_GETCAPS 0x02
8454df8b FB	58	#define VBE_DISPI_8BIT_DAC 0x20
798b0c25 FB	59	#define VBE_DISPI_LFB_ENABLED 0x40
798b0c25 FB	60	#define VBE_DISPI_NOCLEARMEM 0x80
5fafdf24	61
798b0c25 FB	62	#define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
798b0c25 FB	63
798b0c25	64	#ifdef CONFIG_BOCHS_VBE
4e3e9d0b FB	65
	66	#define VGA_STATE_COMMON_BOCHS_VBE \
	67	uint16_t vbe_index; \
	68	uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
	69	uint32_t vbe_start_addr; \
	70	uint32_t vbe_line_offset; \
798b0c25	71	uint32_t vbe_bank_mask;
4e3e9d0b FB	72
	73	#else
	74
	75	#define VGA_STATE_COMMON_BOCHS_VBE
	76
	77	#endif /* !CONFIG_BOCHS_VBE */
	78
798b0c25	79	#define CH_ATTR_SIZE (160 * 100)
8454df8b	80	#define VGA_MAX_HEIGHT 2048
4e3e9d0b FB	81
	82	#define VGA_STATE_COMMON \
	83	uint8_t *vram_ptr; \
	84	unsigned long vram_offset; \
	85	unsigned int vram_size; \
d5295253 FB	86	unsigned long bios_offset; \
d5295253 FB	87	unsigned int bios_size; \
2abec30b TS	88	target_phys_addr_t base_ctrl; \
2abec30b TS	89	int it_shift; \
d2269f6f	90	PCIDevice *pci_dev; \
4e3e9d0b FB	91	uint32_t latch; \
	92	uint8_t sr_index; \
	93	uint8_t sr[256]; \
	94	uint8_t gr_index; \
	95	uint8_t gr[256]; \
	96	uint8_t ar_index; \
	97	uint8_t ar[21]; \
	98	int ar_flip_flop; \
	99	uint8_t cr_index; \
	100	uint8_t cr[256]; /* CRT registers */ \
	101	uint8_t msr; /* Misc Output Register */ \
	102	uint8_t fcr; /* Feature Control Register */ \
	103	uint8_t st00; /* status 0 */ \
	104	uint8_t st01; /* status 1 */ \
	105	uint8_t dac_state; \
	106	uint8_t dac_sub_index; \
	107	uint8_t dac_read_index; \
	108	uint8_t dac_write_index; \
	109	uint8_t dac_cache[3]; /* used when writing */ \
37dd208d	110	int dac_8bit; \
4e3e9d0b FB	111	uint8_t palette[768]; \
	112	int32_t bank_offset; \
	113	int (get_bpp)(struct VGAState s); \
	114	void (get_offsets)(struct VGAState s, \
	115	uint32_t *pline_offset, \
83acc96b FB	116	uint32_t *pstart_addr, \
83acc96b FB	117	uint32_t *pline_compare); \
a130a41e FB	118	void (get_resolution)(struct VGAState s, \
	119	int *pwidth, \
	120	int *pheight); \
4e3e9d0b FB	121	VGA_STATE_COMMON_BOCHS_VBE \
	122	/* display refresh support */ \
	123	DisplayState *ds; \
	124	uint32_t font_offsets[2]; \
	125	int graphic_mode; \
	126	uint8_t shift_control; \
	127	uint8_t double_scan; \
	128	uint32_t line_offset; \
	129	uint32_t line_compare; \
	130	uint32_t start_addr; \
546fa6ab	131	uint32_t plane_updated; \
4e3e9d0b FB	132	uint8_t last_cw, last_ch; \
	133	uint32_t last_width, last_height; /* in chars or pixels */ \
	134	uint32_t last_scr_width, last_scr_height; /* in pixels */ \
	135	uint8_t cursor_start, cursor_end; \
	136	uint32_t cursor_offset; \
	137	unsigned int (*rgb_to_pixel)(unsigned int r, \
	138	unsigned int g, unsigned b); \
d34cab9f TS	139	vga_hw_update_ptr update; \
	140	vga_hw_invalidate_ptr invalidate; \
	141	vga_hw_screen_dump_ptr screen_dump; \
a8aa669b FB	142	/* hardware mouse cursor support */ \
	143	uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \
	144	void (cursor_invalidate)(struct VGAState s); \
	145	void (cursor_draw_line)(struct VGAState s, uint8_t *d, int y); \
4e3e9d0b FB	146	/* tell for each page if it has been updated since the last time */ \
4e3e9d0b FB	147	uint32_t last_palette[256]; \
798b0c25	148	uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
4e3e9d0b FB	149
	150
	151	typedef struct VGAState {
	152	VGA_STATE_COMMON
798b0c25 FB	153	} VGAState;
798b0c25 FB	154
a8aa669b FB	155	static inline int c6_to_8(int v)
	156	{
	157	int b;
	158	v &= 0x3f;
	159	b = v & 1;
	160	return (v << 2) \| (b << 1) \| b;
	161	}
	162
5fafdf24	163	void vga_common_init(VGAState s, DisplayState ds, uint8_t *vga_ram_base,
798b0c25	164	unsigned long vga_ram_offset, int vga_ram_size);
d34cab9f	165	void vga_init(VGAState *s);
798b0c25 FB	166	uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
798b0c25 FB	167	void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
a8aa669b	168	void vga_invalidate_scanlines(VGAState *s, int y1, int y2);
5fafdf24	169	int ppm_save(const char filename, uint8_t data,
f707cfba	170	int w, int h, int linesize);
a8aa669b	171
5fafdf24 TS	172	void vga_draw_cursor_line_8(uint8_t d1, const uint8_t src1,
5fafdf24 TS	173	int poffset, int w,
a8aa669b FB	174	unsigned int color0, unsigned int color1,
a8aa669b FB	175	unsigned int color_xor);
5fafdf24 TS	176	void vga_draw_cursor_line_16(uint8_t d1, const uint8_t src1,
5fafdf24 TS	177	int poffset, int w,
a8aa669b FB	178	unsigned int color0, unsigned int color1,
a8aa669b FB	179	unsigned int color_xor);
5fafdf24 TS	180	void vga_draw_cursor_line_32(uint8_t d1, const uint8_t src1,
5fafdf24 TS	181	int poffset, int w,
a8aa669b FB	182	unsigned int color0, unsigned int color1,
a8aa669b FB	183	unsigned int color_xor);
798b0c25 FB	184
	185	extern const uint8_t sr_mask[8];
	186	extern const uint8_t gr_mask[16];